United States Patent (19)
`Brucculeri et al.
`
`11
`45
`
`Patent Number:
`Date of Patent:
`
`5,036,221
`Jul. 30, 1991
`
`(54 CIRCUIT FOR ELIMINATING
`METASTABLE EVENTS ASSOCATED WITH
`A DATA SIGNAL ASYNCHRONOUS TO A
`CLOCK SIGNAL
`75) Inventors: Louis S. Brucculeri, Dallas; James N.
`Giddings, Mesquite, both of Tex.
`73 Assignee: Texas Instruments Incorporated,
`Dallas, Tex.
`(21) Appl. No.: 331,477
`22 Filed:
`Mar. 31, 1989
`5
`(51) Int. Cl. ........................ H03K 5/13; H03K 19/00
`52) U.S. Cl
`307/443: 307/480;
`kVo a/ke a new na as or a soon esse as a o307/269. 328/. 69. 328/63
`58) Field of Search
`G/480 A. 269, 600
`307/605, 234, 272. 1, 272.3; 328/63, 72, i05.
`10, 11
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`3,979,732 9/1976 Hepworth et al. .................
`4,518,865 5/1985 Iwasaki .................
`... 307/592
`4,694,196 9/1987 Hasley et al. ....................... 307/269
`
`
`
`4,789,959 12/1988 Hung et al. ........................... 328/72
`4,799,023 1/1989 Firooz et al. ..................... 307/234
`4,851,710 7/1989 Grivna ................................ 307/269
`Primary Examiner-Timothy P. Callahan
`Attorney, Agent, or Firm-Ronald O. Neerings; Thomas
`W. Demond; Melvin Sharp
`57
`ABSTRACT
`-
`A circuit for reducing the metastable events produced
`by a data signal asynchronous to a system clock signal is
`provided. The circuit includes an edge detector (32) for
`detecting a transistion of the data signal. The edge de
`tector (32) controls a clock disable/reenable circuit (46)
`which will disable a system clock directed to a clocked
`device (36). The period of disablement is the minimum
`setup time for the clocked device (36). After the mini
`mum setup time has passed, the disable/reenable circuit
`(42) will reenable the system clock to the clocked de
`vice (36). The system clock may be modified by a dura
`tion limit circuit (68). Data directed to the clocked
`device (36) may be delayed via a delay circuit (70).
`16 Claims, 2 Drawing Sheets
`
`M
`
`------------------
`
`DATA o
`
`32
`
`112
`
`114
`Do
`
`68-1-Do KIONS
`L
`
`104
`
`42
`108
`- - - - - - - - - - - - - - - - - - - - - - -
`
`C4ONS)
`
`D 126
`110
`118 120
`) Dr. V
`111
`
`H-C4ONS
`
`122
`
`.
`
`X
`124
`
`{1ONS
`72 ------- 74
`
`34
`
`48
`
`Samsung Electronics Co., Ltd.
`Ex. 1033, p. 1
`
`

`

`U.S. Patent
`
`July 30, 1991
`
`Sheet 1 of 2
`
`5,036,221
`
`12
`
`14
`
`DATA
`
`FIG. 1
`CLOCK
`
`16
`
`10
`
`OUTPUT
`
`1822
`
`o, R. H)
`* -->
`20
`26
`t3
`SSE - \
`Y \-
`t2
`
`CLOCK
`
`t
`
`FIG. 3O.
`
`54
`
`DATAO
`SYSTEM
`CLOCK
`
`
`
`o OUTPUT
`
`CLOCK DISABLE
`REENABLE
`
`44-s) is
`
`43
`
`Samsung Electronics Co., Ltd.
`Ex. 1033, p. 2
`
`

`

`U.S. Patent
`
`July 30, 1991
`
`Sheet 2 of 2
`
`5,035,221
`
`DATA
`
`SYSTEM
`CLOCK
`
`------- -70
`KONSO
`72 ------- 74
`
`FIG. 5
`
`48
`
`54
`
`31
`
`OUTPUT
`
`Samsung Electronics Co., Ltd.
`Ex. 1033, p. 3
`
`

`

`1.
`
`CRCUT FOR ELMINATING METASTABLE
`EVENTS ASSOCATED WITH AIDATA SIGNAL
`ASYNCHRONOUS TO A CLOCKSIGNAL
`
`0.
`
`5,036,221
`2
`drawings taken in conjunction with the following de
`scriptions, in which:
`FIG. 1 illustrates a circuit diagram of clocked device
`having a data and clock input, and an output dependent
`therefrom;
`FIG. 2 illustrates a timing diagram of a data signal
`asynchronous to a system clock;
`FIG. 3a illustrates a block diagram of the present
`invention;
`FIG. 3b illustrates a timing diagram produced by the
`block diagram of FIG. 3a,
`FIG. 4a illustrates a block diagram of the preferred
`embodiment of the present invention;
`FIG. 4b illustrates a timing diagram produced by the
`block diagram of FIG. 4a, and
`FIG. 5 illustrates a circuit diagram of the preferred
`embodiment of the present invention.
`DETAILED DESCRIPTION OF THE
`INVENTION
`The preferred embodiment of the present invention is
`best understood by referring to FIGS. 1-5 of the draw
`ings, like numerals being used for like and correspond
`ing parts of the various drawings.
`FIG. 1 illustrates a typical clocked device 10 as used
`with the present invention. Device 10 has a data line 12
`and a clock line 14 connected thereto. An output line 16
`is further provided with device 10. In operation of de
`vice 10, data is input on data line 12 in accordance with
`a subsequent clock signal provided along clock line 14.
`For all clocked devices, there exists a minimum setup
`time associated with the device. In order for a valid
`output to occur after data appears at data line 12, a time
`greater than or equal to the minimum setup time must
`pass between receiving a valid data signal on data line
`12 and receiving the clock signal on clock line 14. If the
`setup time is violated, then a metastable (i.e., invalid)
`output may result.
`FIG. 2 illustrates a timing diagram of the relationship
`between a data signal 18 which is asynchronous (i.e.,
`has no phase relationship) to a system clock signal 20.
`Data signal 18 has a high transition 22 or a low transi
`tion 24 at time t1. System clock signal 20 is asynchro
`nous to data signal 18 and therefore has an active edge
`26 at a time t2 which has no predictable relationship to
`time t1. It is to be understood that active edge may be
`either a high or low transition. A time t3 is defined for
`data signal 18 in relation to time t1. The difference in
`time between t3 and t1 represents the necessary setup
`time (ts) for a clocked device 10. This setup time is a
`device specification which varies among different
`clocked devices.
`In FIG. 2, active edge 26 of system clock signal 20 is
`shown to occur during the setup time tsu associated with
`data signal 18. When this occurs, the output signal along
`output line 16 may be metastable or invalid. In other
`words, where the system clock signal 20 violates the
`setup time associated with data signal 18, a metastable
`event occurs creating an erroneous signal from clocked
`device 10 which may further propagate to any circuitry
`connected thereto.
`FIG. 3a illustrates a block diagram of the present
`invention. The data signal is received on the input 30 of
`an edge detector 32 and the input 34 of clocked device
`36. It is to be noted that clocked device 36 may be any
`clocked circuit, including one formed among other
`devices on an integrated circuit. An output 38 of edge
`detector 32 is a control signal connected to the input 40
`
`TECHNICAL FIELD OF THE INVENTION
`This invention relates to asynchronous data in syn
`chronous networks, and more particularly to a circuit
`for eliminating metastable events arising from a clock
`signal asynchronous to a data signal.
`BACKGROUND OF THE INVENTION
`In digital logic circuitry, all clocked elements have a
`minimum specified setup time which defines the re
`15
`quired time period which must pass between receipt of
`data and receipt of a clock signal. The specified setup
`time varies for different digital devices. Where the data
`signal is asynchronous to the clock signal, the setup time
`will usually be violated. If the setup time is violated,
`then the recipient chip may produce a metastable (i.e.,
`invalid) result. This metastable result can further propa
`gate through the network containing the recipient chip,
`thereby creating invalid data therethrough.
`Under one current solution, the asynchronous data
`signal is routed through a series of two flip-flops in
`order to reduce the probability of violation of the setup
`time. However, this configuration requires an additional
`two clock periods to move the data through the flip
`flops and to the recipient clocked device. Further, there
`still exists some probability that the setup time will be
`violated thereby giving rise to a metastable result.
`Therefore, a need has arisen for a circuit to eliminate
`metastable events arising from a data signal asynchro
`35
`nous to a clock signal.
`SUMMARY OF THE INVENTION
`In accordance with the present invention, a circuit
`for eliminating metastable results is provided which
`substantially eliminates or reduces disadvantages and
`problems associated with prior asynchronous clock and
`data signals.
`A circuit for eliminating the metastable events pro
`duced by a data signal asynchronous to a clock signal is
`45
`provided which includes a disabling circuit which dis
`ables the system clock signal for a predetermined time
`period following detection of a transition of the data
`signal. The system clock is reenabled following comple
`tion of the predetermined time period. An edge detect
`50
`ing circuit is also provided to detect the transition of the
`data signal in order to trigger the disabling circuit. A
`duration circuit may be used to limit the high period of
`the system clock. Another aspect of the present inven
`tion includes a delay circuit to inhibit the data signal for
`55
`a minimal delay time prior to transfer of the signal to the
`clocked device.
`The present invention provides the technical advan
`tage of eliminating metastable outputs associated with
`clock signals asynchronous to data signals. Another
`60
`technical advantage of the present invention is minimi
`zation of the propagation delay between the time the
`system clock is reenabled and the occurrence of an
`output by the clocked device.
`BRIEF DESCRIPTION OF THE DRAWINGS
`For a more complete understanding of the present
`invention, reference is now made to the following
`
`20
`
`25
`
`65
`
`Samsung Electronics Co., Ltd.
`Ex. 1033, p. 4
`
`

`

`5,036,221
`4.
`3
`t3. Without the circuit of FIG. 3a, clocked device 36
`of a clock disable/reenable circuit 42. The system clock
`would have received active edge 58 at time t2. How
`signal is received on the input 44 of clock disable/reena
`ever, the addition of the FIG. 3a circuit results in
`ble circuit 42. The output 46 of disable/reenable circuit
`clocked device 36 receiving an active edge 62 at time t3.
`42 is connected to the clock input 48 of clocked device
`Therefore, while the metastable event has been
`36.
`avoided, there has been a shift of time (i.e., t3-t2) of the
`A circuit of FIG. 3a acts to prevent a metastable
`clock signal sent to clocked device 36.
`event from occurring. It is again noted that a metastable
`Quite often the design of a digital network will in
`result will occur when the system clock has a transition
`clude considerations of a parameter known as clock-to
`on its active edge during the setup time following a data
`Q. Clock-to-Q time is a specified parameter for any
`transition. The present invention prevents the metasta
`O
`clocked device which defines the time which must pass
`ble event from occurring by disabling the system clock
`after the device is clocked before the output thereof will
`from the clocked device during the setup period which
`be valid. Thus, in designing a digital circuit, the de
`occurs following transition of the data signal. The sys
`signer must be able to ascertain when the clock signal
`tem clock is then reenabled following the completion of
`occurs in order to allow for the clock-to-Q time to pass
`the setup period.
`15
`thereafter. For example, in FIG. 3b, the designer antici
`FIG. 3b illustrates a timing diagram resulting from
`pating the clock-to-Q time will measure that time from
`operation of a circuit constructed according to the
`t2, the active edge 58 of the system clock signal 56.
`block diagram of FIG. 3a. A data signal 50 has either a
`However, the circuit of FIG. 3a will effectively shift
`high transition 52 or low transition 54 occurring at time
`the active edge time to t3. Accordingly, the clock-to-Q
`t1. The clocked device 36 has a setup time tsu, associated
`time will begin atts rather than t2. Thus, the completion
`therewith which must pass after the data transition time
`of the clock-to-Q time will be delayed by td, that is, the
`t1. If clocked device 36 receives a clock signal within
`additional time between t3 and t2. It is therefore another
`the setup time, then a metastable event may occur. The
`aspect of the present invention to provide a duration
`system clock 56 has an active edge 58 which occurs at
`circuit which will minimize the additional time to be
`an arbitrary time t2. In the situation depicted in FIG. 3b,
`tween t2 and t3 which adds to the clock-to-Q of the
`active edge 58 has occurred during the setup time tsu
`clocked device.
`associated with data signal 50, and therefore, a metasta
`FIG. 4a illustrates a block diagram similar to FIG.3a
`ble event may occur without the addition of the present
`but having a duration circuit 68 and a delay circuit 70
`invention. However, the clock disable/reenable circuit
`added thereto. The data signal is connected to the input
`42 prevents the metastable event from occurring, by
`30
`72 of delay circuit 70. The output 74 of delay circuit 70
`generating disable/reenable clock signal 60 which is
`is connected to input 34 of clocked device 36. The sys
`directed to clock input 48 of clocked device 36. Thus,
`tem clock is connected to the input 76 of duration limit
`system clock 56 is modified by clock disable/reenable
`circuit 68. An output 78 of duration limit circuit 68 is
`circuit 42 prior to reaching clocked device 36.
`connected to input 44 of clock disable/reenable circuit
`The operation of the block diagram of FIG. 3a in
`accordance with the signals shown in FIG. 3b is as
`42.
`FIG. 4b illustrates a timing diagram depicting addi
`follows. When a data signal transition 52 or 54 occurs,
`tional benefits created by duration limit circuit 68. A
`edge detector 32 detects this transition and controls the
`data signal 80 may have either a high transition 82 or
`clock disable/reenable circuit 42 to disable system clock
`low transition 84 occurring at time t. Data signal 80 has
`56 from clocked device 36. This disabling feature is
`a setup time tsu, which commences at time t1 and will be
`effected by disabling disable/reenable clock signal 60
`specified for the clocked device receiving data signal
`which is coupled to clocked device 36. In FIG. 3b, it is
`80. A system clock signal 86 will have an active edge 88
`shown that detection of transition 52 or 54 occurs at a
`at time t2 which is asynchronous to data signal 80 and
`time t1. Thereafter, disable/reenable circuit 42 will dis
`correspondingly, to time t1. System clock signal 86 will
`... able the clock signal sent to clocked device 36 until the
`further have a low transition 90. Limited duration signal
`setup time tsu has elapsed at a time t3. Once this setup
`92 is the signal which will be produced at output 78 of
`time has passed, disable/reenable circuit 42 will reena
`duration limit circuit 68. Limited duration signal 92 will
`ble clock signal 60 to clocked device 36 at time t3. Once
`have an active edge 94 at time t2 and a low transition 96
`clock signal 60 is reenabled, it will track system clock
`at time t3. The difference between times t and t2 repre
`56. Therefore, if system clock 56 is high at time t3, then
`50
`the reenabled clock signal 60 will also go high, creating
`sent the limited time tL that duration limit circuit 68
`permits signal 92 to remain active. Disable/reenable
`an active edge 62 at time t3. Further, once system clock
`signal 98 will be generated at output 46 of clock disa
`56 incurs a low transition 64, the reenabled clock signal
`60 will track low transition 64, thereby creating a low
`ble/reenable circuit 42.
`The signals illustrated in FIG. 4b are generated in
`transition 66 in the reenabled signal 60. Thus, from
`55
`accordance with the same principles discussed with
`FIGS. 3a and 3b, it may be appreciated that clock input
`reference to FIG. 3b. However, clock disable/reenable
`48 of clocked device 36 will receive a disabled/reena
`circuit 42 receives system clock signal 86 after modifica
`bled signal 60 which cannot incur a high transition
`tion by duration limit circuit 68. Further, data sent to
`during the setup time associated with data signal 50. As
`clocked device 36 is delayed by delay circuit 70. Al
`a result, any possibility of a metastable event is elimi
`though active edge 88 of system clock signal 86 occurs
`nated.
`within setup time tsu, the clock signal to clocked device
`While the construction depicted in FIGS. 3a and 3b
`36 is disabled during that time and thus, no clock signal
`forms a circuit to eliminate metastable events, it has
`will appear at clock input 48 of clocked device 36 at
`been found that this construction requires further modi
`time t2. As previously illustrated in reference to FIGS.
`fication in order to provide optimum functional opera
`65
`3a-3b, the disable/reenable clock signal 60 tracked the
`tion. From FIG. 3b, it may be appreciated that the
`system clock signal 56 applied at input 44 of clock disa
`circuit of FIG. 3a may effectively shift the clock signal
`ble/reenable circuit 42. However, in reference to FIGS.
`received by clocked device 36 from a time t2 to a time
`
`45
`
`25
`
`35
`
`Samsung Electronics Co., Ltd.
`Ex. 1033, p. 5
`
`

`

`10
`
`25
`
`5,036,221
`6
`5
`It is to be understood that numerous other embodiments
`4a and 4b, the addition of duration limit circuit 68 will
`known in the art may be used for the toggling function
`cause disable/reenable clock signal 98 to track limited
`provided for herein. The outputs of both toggle flip-flop
`duration signal 92 rather than system clock signal 86.
`112 and toggle flip-flop 116 are connected generally to
`Thus, at time t when disable/reenable clock signal 98 is
`clock disable/reenable circuit 42. More particularly, the
`reenabled, there occurs an active edge 100 as the reena
`output of toggle flip-flop 112 is connected to a forty
`bled clock signal 98 tracks limited duration signal 92.
`nanosecond delay circuit 118 and a first input of exclu
`Further, a low transition 102 of disable/reenable clock
`sive OR gate 120. The delayed signal from forty nano
`signal 98 will track low transition 96 of limited duration
`second delay circuit 118 is connected to the second
`clock signal 92.
`input of exclusive OR gate 120. In a similar fashion, the
`From the foregoing, it may be appreciated that if a
`output of toggle flip-flop 116 is connected to a forty
`high and low transition are to occur along disable/reen
`nanosecond delay circuit 122 and a first input of exclu
`able clock signal 98, they must occur within the limited
`sive OR gate 124. The delayed signal resulting from
`time tL, and prior to t3. As tL is minimized, time t3 ap
`forty nanosecond delay 122 is connected to a second
`proaches time t2 where the original system clock signal
`input of exclusive OR gate 124. The outputs of exclu
`86 has an active edge 88. The difference of time be
`15
`sive OR gate 120 and exclusive OR gate 124 are con
`tween t3 and t2 was defined earlier in reference to FIG.
`nected to the first and second inputs of NOR gate 126,
`3b as the additional delay time td which may arise from
`respectively. The output of NOR gate 126 is used as a
`the present invention. Thus, delay time tip and limited
`control signal for active high enabling buffer 110.
`time tL are both defined as the difference in time be
`The operation of the circuitry in FIG. 5 is as follows.
`tween ts and t2. Therefore, minimization of tL effec
`20
`When a data transition occurs, it is detected by either
`tively reduces added delay time to discussed above. As
`flip-flop 112 or flip-flop. 116 depending on whether the
`a result, there is a minimum amount of time added to the
`transition is positive or negative. For example, when a
`clock-to-Q time of the clocked device.
`positive transition occurs, the signal acts as a clock
`The edge detecting and clock disabling features dis
`signal to the clock input of flip-flop 112. Because the
`cussed above require a minimal amount of propagation
`inverted output is tied to the input of flip-flop 112, a
`delay to occur. It is thus desirable to prevent data sent
`clock signal will cause the output to toggle, that is to
`to clocked device 36 from reaching the device before
`yield an output different to the output existing prior to
`the clock detection and disable features have had an
`the clock signal. This new signal will be transmitted to
`opportunity to occur. Thus, delay circuit 70 has been
`exclusive OR gate 120. However, due to the forty nano
`added in order to delay data from reaching clocked
`30
`second delay 118, the inputs to exclusive OR gate 120
`device 36 for a time period just greater than the propa
`will be different for forty nanoseconds. An exclusive
`gation time required for the detection and disabling
`OR gate with different inputs yields a one in its output
`features associated with the remainder of the compo
`which will be placed at the first input of NOR gate 126.
`nents in FIG. 4a. It is to be noted that in numerous
`Any high signal into a NOR gate causes its output to go
`applications of the present invention, data will inher
`35
`low. This low signal will be placed at the control input
`ently be delayed prior to reaching clocked device 36.
`of active high enabling buffer 110, and will therefore
`Delay circuit 70 may be wholly or partially substituted
`cause buffer 110 to be in a high impedance state. As a
`with this inherent delay associated with the circuit. As
`result, the system clock cannot conduct therethrough
`a result, any loss of efficiency due to circuit delay 70 is
`and is effectively disabled. After forty nanoseconds,
`minimized. Further, if the delay created by delay circuit
`forty nanosecond delay 118 will cause both inputs of
`70 is less than the inherent delay of the circuit, then the
`exclusive OR gate 120 to match. Thus, the output of
`former is subsumed by the latter and no net delay is
`exclusive OR gate 120 will be a zero, which is placed at
`caused by the present invention.
`the input of NOR gate 126. Similarly, since no signal
`FIG. 5 illustrates the preferred embodiment of the
`transition has occurred through flip-flop 116, the inputs
`present invention. The reference numerals associated
`45
`to exclusive OR gate 124 will be identical, yielding a
`with the block diagram of FIG. 4a are correspondingly
`zero output therefrom which will be placed at the sec
`indicated within FIG. 5. The system clock signal is
`ond input of NOR gate 126. The dual low input to NOR
`connected to a duration limit circuit 68. Duration limit
`gate 126 will cause a high output which will permit
`circuit 68 of the preferred embodiment is a one shot
`active buffer 110 to conduct. Once active buffer 110
`circuit. The system signal is connected to the first input 50
`conducts, the system clock signal is allowed to pass
`of an AND gate 104 and an inverter 106. The output of
`therethrough and thus, is reenabled to the clock input
`inverter 106 goes through a ten nanosecond delay cir
`48 of clocked device 36. Thus, it may be appreciated
`cuit 108 and into the second input of AND gate 104.
`that forty nanoseconds must elapse after a data transi
`The output of AND gate 104 connects to the data input
`tion before the system clock is reenabled. This forty
`of an active high enabling buffer 110. The output of
`55
`nanosecond delay corresponds to the minimum setup
`active high enabling buffer 110 is connected both to a
`time associated with clocked device 36. It is to be fur
`resistor 111 which is further connected to ground, and
`ther understood that the forty nanosecond delays 118
`to the clock input 48 of clocked device 36.
`and 122 could be altered to any desirable time to match
`The data signal is connected to edge detector 32 and
`the setup time of clocked device being driven by the
`delay circuit 70. Within edge detector 32, the data sig
`60
`present invention.
`nal is connected to the clock input of a toggle flip-flop
`The various delay circuits shown within FIG. 5 may
`112 and the input of an inverter 114. The inverted out
`be constructed with principles as known in the art. For
`put of toggle flip-flop 112 is fed back to the data input of
`example, an even number of inventors may be cascaded
`toggle flip-flop 112. The output of inverter 114 is con
`in order to delay a signal passing therethrough.
`nected to the clock input of toggle flip-flop 116. The
`65
`Duration circuit 68 is a one shot configuration yield
`inverted output of toggle flip-flop 116 is fed back to the
`ing a high output for a ten nanosecond time period in
`input of toggle flip-flop 116. Toggle flip-flops 112 and
`accordance with ten nanosecond delay circuit 108.
`116 are D flip-flops fashioned in a toggle configuration.
`
`Samsung Electronics Co., Ltd.
`Ex. 1033, p. 6
`
`

`

`10
`
`15
`
`25
`
`30
`
`35
`
`5,036,221
`8
`7
`6. The circuit of claim 1 wherein the clocked circuit
`However, delay circuit 108 may be adjusted to any
`has a minimum setup time, and wherein said predeter
`desirable time thereby rendering the output of AND
`mined time period equals the minimum setup time of the
`gate 104 high for the time associated with delay circuit
`clocked device.
`108. The operation of duration circuit 68 is as follows.
`7. The circuit of claim 6 including a delay circuit
`Prior to a system clock high transition, a "0" is placed at
`coupled to the data line and the clocked circuit for
`the first input of AND gate 104 while a “1” due to
`delaying the data signal for a predetermined delay time
`inverter 106 is placed at the second input of AND gate
`prior to transfer of the data signal to the clocked circuit.
`104. As a result, AND gate 104 will produce a "0"
`8. The circuit of claim 7 wherein said predetermined
`output indicating that no high transition of the system
`delay time is greater than the propagation delay associ
`clock signal has been received. When the system clock
`ated with said disabling circuit.
`signal goes high, a "1" will be immediately placed at the
`9. A circuit for reducing the metastable events in a
`first input of AND gate 104. However, due to the ten
`clocked circuit produced by a data signal asynchronous
`nanosecond delay circuit 108, the preexisting "1" signal
`with respect to a system clock signal input to the
`will remain at the second input of AND gate 104 for ten
`clocked circuit, comprising:
`nanoseconds. As a result, duration circuit 68 will yield
`a data line coupled to the clocked circuit for inputting
`a high output for ten nanoseconds. Again, it is to be
`a data signal;
`understood that the delay time associated with duration
`an edge detecting circuit coupled to the data line for
`circuit 68 may be adjusted in accordance with the prin
`detecting a transition in the data signal;
`ciples and objectives set forth above. Delay circuit 70
`a system clock for generating a system clock signal;
`20
`delays data prior to its receipt at data input 34 of
`and
`clocked device 36 in order to allow the propagation
`a disabling/reenabling circuit coupled to the system
`associated with edge detector 32 and clock disable/-
`clock, the edge detecting circuit and the clocked
`circuit for disabling the system clock from the
`reenable circuit 42 as discussed above.
`Although the present invention has been described in
`clocked circuit for a predetermined time period
`detail, it should be understood that various changes,
`following detection of said transition of the data
`signal, and for reenabling the system clock to the
`substitutions and alterations can be made herein without
`clocked circuit following the predetermined time
`departing from the spirit and scope of the invention as
`period.
`defined by the appended claims.
`10. The circuit of claim 9 wherein the clocked circuit
`What is claimed is:
`has a minimum setup time, and wherein said predeter
`1. A circuit for reducing the metastable events in a
`mined time period equals the minimum setup time of the
`clocked circuit produced by a data signal asynchronous
`with respect to a system clock signal input to the
`clocked device.
`11. The circuit of claim 9 including a duration circuit
`clocked circuit, comprising:
`coupled to the system clock and the disable/reenable
`a data line coupled to the clocked circuit for inputting
`circuit for limiting an active period of the system clock.
`a data signal;
`12. The circuit of claim 10 including a delay circuit
`an edge detecting circuit coupled to the data line for
`coupled to the data line and the clocked circuit for
`detecting a transition in the data signal;
`delaying the data signal prior to its receipt by the
`a system clock for generating a system clock signal;
`clocked circuit.
`and
`13. A method of reducing the metastable events in a
`a disabling circuit coupled to the system clock, the
`clocked circuit having a minimum setup time and pro
`edge detecting circuit and the clocked circuit for
`duced by a data signal asynchronous with respect to a
`disabling the system clock signal from the clocked
`system clock signal input to the clocked circuit, com
`circuit for a predetermined time period following
`prising the steps of:
`detection of said transition of the data signal.
`detecting a transition of the data signal;
`2. The circuit of claim 1 wherein the disabling circuit
`disabling the system clock signal from the clocked
`reenables the system clock signal to the clocked circuit
`circuit for a predetermined time period in response
`after said predetermined time period.
`to detecting the transition; and
`3. The circuit of claim 1 wherein said detecting cir
`reenabling the system clock signal to the clocked
`circuit following the completion of the predeter
`cuit includes:
`w
`a first toggle flip flop, having an input coupled to the
`mined period.
`data line and an output coupled to the disabling
`14. The method of claim 13 including the step of
`circuit, for detecting a positive transition of the
`limiting an active period of the system clock.
`data signal; and
`15. The method of claim 13 wherein said step of dis
`a second toggle flip flop, having an input coupled to
`abling for a predetermined time includes disabling for a
`the data line and an output coupled to the disabling
`time equal to the minimum setup time of the clocked
`circuit, for detecting a negative transition of the
`circuit.
`data signal.
`16. The method of claim 15 including the steps of:
`4. The circuit of claim 1 including a duration circuit
`delaying the data signal for a predetermined delay
`coupled to the system clock and the disabling circuit for
`time, the delay time being greater than a propaga
`limiting the active period of the system clock to the
`tion time for the detection and disabling steps; and
`transferring the data signal to the clocked circuit
`clocked circuit.
`following the predetermined delay time.
`5. The circuit of claim 4 wherein said duration circuit
`comprises a one shot circuit.
`
`60
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`45
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`50
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`55
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`65
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`k
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`k
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`l
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`k
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`:
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`Samsung Electronics Co., Ltd.
`Ex. 1033, p. 7
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