III III 0 II0 III I0 1101 010 II0 1101 0II (cid:9)
`
`US008020022B2
`
`II 0I II
`
`(12) United States Patent
`Tokuhiro
`
`(10) Patent No.: (cid:9)
`(45) Date of Patent: (cid:9)
`
`US 8,020,022 B2
`Sep. 13, 2011
`
`(54) DELAY TIME CONTROL OF MEMORY
`CONTROLLER
`
`(75) Inventor: Noriyuki Tokuhiro, Kawasaki (JP)
`
`(73) Assignee: Fujitsu Limited, Kawasaki (JP)
`
`(*) Notice: (cid:9)
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 334 days.
`
`(21) Appl. No.: 12/209,740
`
`(22)
`
`Filed: (cid:9)
`
`Sep. 12, 2008
`
`(65) (cid:9)
`
`Prior Publication Data
`
`US 2009/0077411 Al (cid:9)
`
`Mar. 19, 2009
`
`(30) (cid:9)
`
`Foreign Application Priority Data
`
`Sep. 18, 2007 (cid:9)
`
`(JP) ................................. 2007-241610
`
`(51)
`
`Int. Cl.
`G06F 13/42 (cid:9)
`(2006.01)
`(52) U.S. Cl . ........................................ 713/401; 713/601
`(58) Field of Classification Search .......... 713/400-401,
`713/500-501, 600-601
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`7,412,616 B2 * (cid:9)
`8/2008 Matsui et al . ................. 713/401
`7,796,465 B2* (cid:9)
`9/2010 Swain et al . ............. 365/233.13
`2005/0047192 Al (cid:9)
`3/2005 Matsui et al.
`2005/0174878 Al (cid:9)
`8/2005 Osaka et al.
`
`FOREIGN PATENT DOCUMENTS
`2003-099321 (cid:9)
`4/2003
`JP (cid:9)
`2005-078547 (cid:9)
`3/2005
`JP (cid:9)
`2005-209168 (cid:9)
`8/2005
`JP (cid:9)
`* cited by examiner
`
`Primary Examiner Raymond Phan
`Staas & Halsey LLP
`(74) Attorney, Agent, or Firm
`
`ABSTRACT
`(57)
`A memory control circuit has a write leveling function and
`controls read/write operations by supplying a clock signal to
`a plurality of memories through a clock signal line which is
`wired to the plurality of memories through daisy chain con-
`nection. For each of the plurality of memories, a first variable
`delay unit delays, in a write operation, a data strobe signal
`output to the memory by a first delay time that is set by
`utilizing the write leveling function and a second variable
`delay unit delays, in a read operation, a data signal input from
`the memory by a second delay time that is set based on the first
`delay time.
`
`16 Claims, 20 Drawing Sheets
`
`CPU
`
`13 (cid:9)
`
`10
``X4
`
`CLK
`
`15-1,15
`
`d1, d2
`------------ --------17-1,17--- (cid:9) ^
`
`DQ-1 [1] (DQ-1:DQ)
`
`14H FIRST CLOCK SIGNAL
`GENERATOR
`CONTROL CIRCUIT UNIT
`DOS SIGNAL GENERATOR
`; (cid:9) FIRST VARIABLE DELAY CIRCUIT
`DQ SIGNAL CONTROL UNIT
`FIRST VARIABLE DELAY CIRCUIT
`
`16
`
`11
`12 (cid:9)
`CK1/Add/CMD (cid:9)
`
`DIMM
`
`--
`
`DQS-1 (DQS)
`DW
`(cid:127) _. DW
`DQ-1[1] (DQ-1:DQ) (cid:9)
`
`SDRAM-1
`
`23 22
`
`DELAY TIME
`CONTROL UNIT
`FIRST DELAY TIME
`CONTROL UNIT
`
`SECOND DELAY TIME
`CONTROL UNIT
`
`17-k,17
`DQ-1[k] (DQ-1:DQ)
`
`SECOND VARIABLE DELAY CIRCUIT ; --
`
`DQ SIGNAL CONTROL UNIT
`F IRST VARIABLE DELAY CIRCUIT
`SECOND VARIABLE DELAY CIRCUIT
`
`
`
`(cid:127)
`
`--
`
`------------ -------
`
`15-n,15
`d1,d2
`
`16
`------ (cid:9) +
`
`CONTROL CIRCUIT UNIT
`DQS SIGNAL GENERATOR
`F1RSTVARlA6LEDELAYC1RCUIT
`
`-
`
`DQ-n[1] (DQ-n:DQ)
`
`17-1,17
`
`DO SIGNAL CONTROL UNIT
`FIRST VAR IABLEDECAYcIRcUlT
`- -------------------------- -
`SECOND VARIABLE DELAY CIRCUIT
`
`
`
`DQ-n[k] (DQ-n:DQ)
`
`17-k,17.
`
`DQ SIGNAL CONTROL UNIT
`FIRST VARIABLE DELAY CIRCUIT
`SECOND VARIABLE DELAY CIRCUIT ; "
`
`DR
`
`DW
`
`DQ-1 [k] (DQ-1:DQ)
`
`DR
`
`DQS-n (DOS)
`
`DW
`DW
`DQ-n[1] (DQ-n:DQ)
`
`-DR
`
`DW
`DQ-n[k] (DQ-n:DQ)
`
`DR
`
`SDRAM-n
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 1
`
`(cid:9)
`(cid:9)
`(cid:9)
`

`

`FIG. 1
`RELATED ART
`
`- -. (cid:9)
`
`90
`
`-.
`.........
`
`91
`________
`DIMM
`
`
`DQ/DQS
`---------------------------------------
`I
`
`D O/DOS (cid:9)
`
`CONTROLLER
`
`DO/DOS
`
`SDRAM
`
`_
`
`_____
`
`ci)
`
`92-1
`
`92-2
`
`92-3
`
`:L1
`
`ci)
`
`- {M 92-n
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 2
`
`(cid:9)
`

`

`FIG. 2
`RELATED ART
`
`CK/Add/CMD
`
`^ -------------- -X51----------------
`
`f
`
`I9li►T1i►'I
`
`^.---- SDRAM
`
`."
`
`MEMORY
`CONTROLLER
`
`93-1 (cid:9)
`
`93-n
`
`92-n
`
`00
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 3
`
`

`

`an
`
`FIG. 3
`RELATED ART (cid:9)
`
`91
`
`92-1
`
`92-n
`
`00
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 4
`
`

`

`FIG. 4 (cid:9)
`CPU (cid:9)
`
`13
`
`10
`
`CLK
`
`15-1,15
`
`d1, d2
`------------ --------17-1,17---
`
`DQ-1 [1] (DQ-1:DQ)
`
`14 (cid:9)
`
`MEMORY CONTROLLER
`FIRST CLOCK SIGNAL
`GENERA TOR
`CONTROL CIRCUIT UNIT
`DOS SIGNAL GENERATOR
`DQS-1 (DOS)
`--FIRST VARIABLE DELAYCIRCUIT - _Y -- -, - DW
`DQ SIGNAL CONTROL UNIT
`-" DW
`DO-1[1] (DQ-1:DQ)
`FIRSTVARIABLEDELAYCIRCUIT
`----- -- ---- -- -- -- -- -- -- -- --
`---------------------------,
`;SECONDVARIABLEDELAYCIRCUIT,
`
`11-
`12 (cid:9)
`CK1/Add/CMD
`
` -
`
`1 ;
`
`--
`
`
`
`- DR
`
`DIMM
`
`SDRAM-1
`
`ft
`
`23
`
`22
`
`DELAY TIME
`CONTROL UNIT
`FIRST DELAYTIME
`CONTROL UNIT
`
`SECOND DELAY TIME
`CONTROL UNIT
`
`17-k,17
`DQ-1 [k] (DQ-1:DQ)
`
`DO SIGNAL CONTROL UNIT
`FIRSTVARIABLEDELAYCIRCUIT_ ;
`SECOND-VARIABLE DELAYCIRCUIT r
`--
`
`-" DW
`DQ-1[k] (DQ-1:DQ)
`
`- DR
`
`-----------
`
`-------
`
`15-n,15
`
`d- 'd------ (cid:9)
`
`-
`16 ; (cid:9)
`
`24 (cid:9)
`
`DQ-n[1] (DQ-n:DQ)
`17-1,17
`
`CONTROL CIRCUIT UNIT
`DOS SIGNAL GENERATOR
`FIRST VARIABLE DELAY CIRCUIT (cid:9)
`DQ SIGNAL CONTROL UNIT
`FIRST VARIABLE DELAY CIRCUIT
`SECOND VARIABLE DELAY CIRCUIT
`
`r
`
`DOS-n (DOS)
`
`DW
`DW
`DQ-n[1] (DQ-n:DQ)
`
`DR
`
`DW
`DQ-n[k] (DQ-n:DQ)
`
`SDRAM-n
`
`00
`
`DQ-n[k] (DQ-n:DQ)
`
`17-k,17--
`
`DO SIGNAL CONTROL UNIT
`I
`FIRST VARIABLE DELAY CIRCUIT
`SECOND VARIABLE DELAY CIRCUIT ,
`
`-
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 5
`
`(cid:9)
`

`

`FIG. 5
`CPU
`
`23
`FIRST DELAY TIME
`CONTROL UNIT
`SECOND DELAY
`TIME CONTROL UNIT
`rJ
`24
`
`13 10
`
`CLK
`
`dl
`
`17-1,17-
`I_DQe-1 [1] (I_DQe)
`(DQ-1[1] DQ-1 DQ)
`I_DQo-1 [1] (I_DQo)
`(DQ-1[1] DQ-1 DQ)
`
`0_DQe-1[1](0 DQe)
`(DQ -i [1] ; DQ-1; DQ)
`0_DQo-1[1](0 DQo)
`(DQ -i [i] . DQ-1; DQ)
`15-1,15
`17-1,17 --_
`I_DQe-1 [kJ (I_DQe)
`(DQ -1 [k.: DQ-1; DQ)
`I DQo-1 [kl (I_DQo)
`(DQ -1 [k:: DQ-1: DQ)
`
`0 DQe-1 [kJ (0 DQe)
`(DQ-1[k.: DQ-1; DQ)
`0 DQo-1[kl(0 DQo)
`(DQ-1[k.: DQ-1; DQ)
`
`14 (cid:9)
`
`ice
`
`MEMORY CONTROLLER
`DWO (cid:9)
`
`16
`
`- (cid:9)
`
`- (cid:9)
`
`--------------------
`
`11
`
`CK1
`
`DIMM
` 12
`
`'
`
`18
`
`CK2
`
`19-1,19
`
`FF1 ' (cid:9)
`
`DW1
`
`DW2
`
`^ (cid:9)
`
`'
`
`DQS-1
`(DOS)
`
`FF2
`
`21
`
`(DQ-1;DQ)
`
`------- ------- (cid:9) ----- (cid:9) ---- (cid:9)
`
`-------- -------- -- ------- (cid:9) ------i
`
`FF6 (cid:9)
`
`FF8 (cid:9)
`- (cid:9)
`---- (cid:9)
`
`- (cid:9)
`
`'
`
`DR1
`
`FF5
`
`DR2
`-t
`----------
`
`FF7
`19-k,19
`_
`201 20
`
`--
`
`DW1 (cid:9)
`
`(cid:127) (cid:9)
`
`FF1 €
`
`(cid:9) DW2
`
`------- - (cid:9) ----------- (cid:9)
`
`--
`
`-
`
`FF6 (cid:9)
`
`DTtFF8 (cid:9)
`
`DR1
`
`DR2
`
`FF5
`
`FF7 rLI _f
`
`i'
`
`.
`
`DQ-1[k]
`
`(DQ-1:DQ)
`FF4
`
`i)
`21:
`
`,j
`
`
`
`JI
`
`00
`
`OR
`
`20 -k,20
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 6
`
`(cid:9)
`(cid:9)
`

`

`FIG. 6
`CPU
`
`-x.13 10
`
`13 14 (cid:9)
`
`23
`
`FIRST DELAY TIME
`CONTROL UNIT
`SECOND DELAY
`TIME CONTROL UNIT
`
`24
`
`dl (cid:9)
`
`17-1,17— - (cid:9)
`IDQe-n[1I (IDQe) (cid:9)
`
`
`
`I_DQo-n[11(1-DQo) (cid:9)
`
`O DQen[11(0_DQe) (cid:9)
`
`0 DQo-n 1 0 DQo (cid:9)
`DQ-n 1 DQ-n: DQ
`l (cid:9)
`[ 1 (cid:9)
`)
`
`MEMORY CONTROLLER (cid:9)
`DW0 (cid:9)
`– (cid:9)
`
`16
`
`=-- (cid:9) --------------
`
`12 11.E
`
`DIMM
`14
`[ CK1
`
`18 (cid:9)
`
`CK2 (cid:9)
`
`DW1 (cid:9)
`
`19-1,19
`
`FFO (cid:9)
`
`------- ----- (cid:9)
`!,
`
`- (cid:9)
`
`-- -1 --------- -- ------ -- --
`
`'
`
`
`
`FF1 (cid:9)
`
`DW2 (cid:9)
`
`J
`
`FF2 (cid:9)
`
`DQS n
`(DQS)
`
`; i ; (cid:9)
`
`DQ-n[1]
`(DQ -n:DO)
`
`i ----- ---- - ----- ---------- ---------- --- ------- ------
`FF5
`DR1 (cid:9)
`
`FF6
`
`;
`
`----
`
`
`
`
`
`
`
`U)
`
`17-k, 17 —
`
`:DWI 1 20-1 20 9 k,19(cid:127)
`
`FF2
`DQ-n[k]
`(DO-n[k] DQ-n: DO)
`DQ-n:DQ
`FF1 (cid:9)
`DW2 (cid:9)
`21
`( (cid:9)
`)
`I-DQo-n[k](I DQo) (cid:9)
`(DQ n[k] DQ DQ) (cid:9) vFF4
`FF3 (cid:9)
`-- ------
`--------------- (cid:9)
`------- -------
`- --- ---------,
`----- -- -- ---- -- (cid:9)
`---------------------- (cid:9)
`0-DQe-n[kl (0-DQe)
`
`(DQ-n[k] DQ-n:DQ) (cid:9)
`0 DQo-n[kI (0-DQo)
`(DQ-n[k] DQ-n:DQ) (cid:9)
`
`- - - - (cid:9)
`
`-
`
`; (cid:9)
`
`FF6 (cid:9)
`
`DR1 (cid:9)
`
`FF5
`
`FF8 (cid:9)
`i ; (cid:9)
`----------- F8 ------ (cid:9)
`
`DR2 (cid:9)
`----------- (cid:9)
`
`!
`FF7 (cid:9)
`------------- ---------- . ,
`
`'
`
`O-DQX-n
`
`OR (cid:9)
`
`20-k,20
`
`00
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 7
`
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`

`

`FIG. 7
`MEMORY CONTROLLER
`
`-
`
`_ (cid:9)
`
`DIMM
`
`, 11
`
`T2 T3
`
`SDRAM-1
`
`CK1
`
`DOS-1
`
`J
`
`-x-12
`
`CK11Add1CMD
`
`DQS-1 (DQS)
`DQ-1 J1J_!kUDO) --
`
`- --
`
`DW-1
`
`T1
`
`CK1
`
`DQS
`
`;
`DQS-n ' ;
`
`ft
`
`00
`
`DQS-n (DQS)
`* ------------- DQ-n i1J-1kUPQj-------------
`
`------
`
`SDRAM-n
`
`-.
`
`DW-n
`
`CK1 (cid:9)
`
`J
`
`DQS-n :r--
`
`.H.
`A (cid:9) Dtl-n
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 8
`
`(cid:9)
`

`

`FIG. 8
`CPU
`
`10
`
`x-13 (cid:9)
`
`23
`
`FIRST DELAY TIME
`CONTROL UNIT
`SECOND DELAY
`TIME CONTROL UNIT
`
`24
`
`CLK (cid:9)
`
`dl
`
`d2 (cid:9)
`
`IDQe-1[1] (cid:9)
`
`IDQo-1 [1 ] (cid:9)
`
`0_DQe-1[1] (cid:9)
`
`0 DQo-1 1 (cid:9)
`[ ] (cid:9)
`
`15-1,15
`
`I_DQe-1 [k] (cid:9)
`_
`I_DQo 1 [k] (cid:9)
`17-k 17 _ — (cid:9)
`0DQe 1[k] (cid:9)
`
`0_DQo 1 [k] (cid:9)
`
`MEMORY CONTROLLER (cid:9)
`DWO dCKO 16
`'
`
`14 (cid:9)
`
`r (cid:9)
`
`18 (cid:9)
`-- -- -----DWI
`
`: ------- (cid:9)
`
`-- - (cid:9)
`
`dDQSWO FFO
`19-1,19 (cid:9)
`-J ---- (cid:9)
`
`- (cid:9)
`
`DW2 (cid:9)
`----- -------:------ --------------------- (cid:9)
`----------
`----- ------ (cid:9)
`DR1 (cid:9)
`
`FF1 (cid:9)
`
`FF6 (cid:9)
`
`FF2 (cid:9)
`
`------ ------
`FF5 - --------
`
`= r
`
`0 U)
`
`12 (cid:9)
`
`^'
`dCK1
`
`DIMM
`CK2
`
`,
`
`DQS-1
`
`
`dDQS WI ,
`
`DQ-1[1]
`
`^ i ; (cid:9)
`21 ;
`
`r : (cid:9)
`
`i
`i (cid:9)
`
`; ! , (cid:9)
`
`' (cid:9)
`^i' (cid:9)
`- -- - (cid:9)
`
`FF8 (cid:9)
`(cid:127) (cid:9)
`= (cid:9)
`
`(cid:127) (cid:9)
`
`-- (cid:9)
`
`DR2 (cid:9)
`
`FF7
`; ^ (cid:9)
`19-,19(cid:127)
`20-1,20 (cid:9)
`-- - (cid:9)
`
`-,m (cid:9)
`-- -- --- - - --- ;: (cid:9)
`
`DW2 (cid:9)
`
`FF ' 1 (cid:9)
`
`21;' (cid:9)
`FIF
`-----------:--------------------- -- ---- ---------
`- -- (cid:9)
`-- ---------------------- --
`- -- --------- -
`DR1 (cid:9)
`FF5
`
`FF6 (cid:9)
`
`' (cid:9)
`FF7
`DR2 (cid:9)
`FF8 (cid:9)
`i ; (cid:9)
`------------------------------ ----- ------ ------- - ---------
`
`ORrLH 20-k,20
`
`-FF2
`DQ-1 [k]
`
`FF4
`
`co
`
`00
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 9
`
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`

`

`MEMORY CONTROLLER (cid:9)
`dCKO (cid:9)
`1 6 (cid:9)
`14 (cid:9)
`JJLbW0
`
`
`
`1
`
`12dCK1
`CK1
`
`DIMM
`dCK2x,
`dCK2y,
`
`---- --------------1------------------------ - (cid:9)
`
`'
`
`FIG. 9
`CPU
`
`x-13 (cid:9)
`
`23
`
`FIRST DELAY TIME
`CONTROL UNIT
`SECOND DELAY
`TIME CONTROL UNIT
`
`24
`
`10
`
`CLK
`
`d1
`
`d2
`
`DO-x, DQ-y (DQ)
`
`DO x, DO -y (DO)
`
`--- -- --- (cid:9)
`ir FF1
`
`- (cid:9)
`
`--' (cid:9)
`
`18
`
`FFO (cid:9)
`
`----------------------------------------
`
`DW1 (cid:9)
`- - - (cid:9)
`
`191,19
`--- --- — - — —
`
`_
`
`DW2 dDQSROx F2
`
`DQS-x, DQS-^
`^(DDQQSy
`dDQSR1x,
`dDQSR1y
`DQ x, DQ y
` (DO)
`21, ^
`
`'
`
`OD
`
`FF6
`FF8
`
`(cid:127)
`
`,
`j
`
`DR2 (cid:9)
`
`FF7
`-= (cid:9)
`19-k,19;
`
`: DW1 (cid:9) 20-1,20(cid:127) _
`-- (cid:9) - - (cid:9)
`-
`
`- (cid:9) (cid:127)
`--
`
`L (cid:9) DW2
`
`- (cid:9)
`
`-
`
`-
`
`15-x,15,
`
`DQ-x, DQ-y (DO)
`
`DO-x, DQ-y (DQ)
`17 k,17
`DQ x, DQ-y (DO)
`
`DQ-x, DQ-y (DO)
`
` : (cid:9)
`FF1 (cid:9)
`i (cid:9)
`; (cid:9)
`-- --- FF3 r (cid:9) ^;' -----
`
`;----- - ------------------------------ ------ -- --- (cid:9) ---- ----- - = (cid:9)
`DR1 (cid:9)
`FF5
`FF6
`
`
`i ; --------------------- FF8 ------ (cid:9)
`
`DR2
`
`
`---- (cid:9)
`
`---
`
`pR
`
`20-k,20
`
`: =
`
`i
`211=
`
`FF2
`DQ x, DQ-y
`DQ
`F (cid:9)
`)
`FF4
`
`;
`
`00
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 10
`
`

`

`FIG. 10
`
`MEMORY CONTROLLER
`
`12
`
`T4
`
`CK1 _/
`
`DQS-1[ - - _ (cid:9)
`(cid:9) kDW-1
`DQ 1 [l]-[fl/
`--- --
`
`- (cid:9)
`
`DOS
`
`DQ-k [1]-[ ; (cid:9)
`
`DW n
`------- ------ (cid:9)
`
`___ _.
`
`fl
`H
`FF-la
`
`
`
`----
`
`FF-na
`
`CK1/Add/CMD
`
`DQS-1 (DOS)
`
`DO-1 [1]-[k] (DO)
`
`DIMM
`
`T5 T6
`
`CKI J/
`
`DQS-1
`
`Q-1 [1]-[k
`
`DQS-n (DQS)
`
`DO-n [1]-[k] (DO)
`
`SDRAM-n
`
`CK1
`
`DQS-n ,
`
`0-1 [1]-,'fl
`
`
`Dt1-n
`
`00
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 11
`
`(cid:9)
`

`

`FIG. 11
`MEMORY CONTROLLER
`
`12
`
`T9 T10
`
`DQ-1 [1]_[k]
`
`CK11Add/CMD
`
`DQS-1 (DQS)
`------- --- --- - (cid:9)
`DQ1 [1][k] (DQ) (cid:9)
`
`
`
`----nSDRAM-1
`j
`J (cid:9)
`
`DR-1 (cid:9)
`
`FF-lb
`
`DIMM
`
`T7 T8
`
`CK1
`
`DQS-1
`
`DQS-n (DQS)
`
`DQ-n [1]-[k] (DQ)
`
`---------
`
`DR-n (cid:9)
`
`FF-nb
`
`; .-
`Dt2-n
`
`L _________
`
`SDRAM-n
`
`CK14I
`
`DQS-n
`
`Dt2-n
`
`ft
`
`00
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 12
`
`(cid:9)
`(cid:9)
`

`

`FIG. 12
`CPU
`
`23
`
`FIRST DELAY TIME
`CONTROL UNIT
`SECOND DELAY
`TIME CONTROL UNIT
`
`24
`
`lOa (cid:9)
` 14 (cid:9)
`
`MEMORY CONTROLLER
`
`11
`
`DIMM
`
`FL
`
`:
`
`CLK
`
`dl (cid:9)
`
`17-1 , 17
`IDQe-1 III (IDQe) (cid:9)
`IDQo-1 III (lDOo)
`(DQ1[1]:DQ1 DQ) (cid:9)
`O_DQe-1[1](O_DQe) (cid:9)
`(DQ-l[1]:DQLDQ) (cid:9)
`ODQO1[1] (ODQO)
`(DQ-l[1]:DQ.LDQ) (cid:9)
`
`18 (cid:9)
`
`CK2
`
`FFO (cid:9)
`
`1. DWIa (cid:9)
`
`19a-1,19a
`
`F1 (cid:9)
`
`FF6 (cid:9)
`
`FF8
`
`F2a
`
`J -
`
`FF5
`
`FF7 _rL,_I
`--- --- --- --
`
`-DR1 (cid:9)
`DR2 (cid:9)
`
`(DOS)
`
`
`
`U)
`
`ci)
`
`ci)
`
`I5-1,I5---
`17-k,17 --.. (cid:9)
`
`: (cid:9)
`
`: (cid:9)
`
`20-1,20
`19a-k,19a (cid:9)
`DW1a (cid:9)
`
`
`
`i
`
`::4:: 4:
`1
`
`DQ-1 [k]
`(DQ-1 DQ)
`---FF2a
`
`) (cid:9)
`
`FF1 (cid:9)
`
`IDQe-1[k](IDQe) (cid:9)
`IDQo-1[k](IDQ0) (cid:9)
`(DQ-1[k]: DQ-1 DQI (cid:9)
`ODQe-1[k](ODQe)
`(DQ-1]:DQ1:DQ) (cid:9)
`FF6 (cid:9)
`0DQo-1 [k] (ODQO)
`
`(DQl[k]:DQ.1:DQ) -ES ---- -DR2 (cid:9)
`
`DR1
`
`FF5—
`
`-FF7 -U (cid:9)
`
`
`----
`
`ODQX1 .R 2O,2O
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 13
`
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`

`

`MEMORY CONTROLLER
`
`DWO (cid:9)
`
`16
`
`13 (cid:9)
`
`14 (cid:9)
`
`L
`
` 1: >
` 18
`FFO-1_ij (cid:9)
`
`I
`
`DQS-n
`(DOS)
`
`
`
`_________
`DIMM
`
`12 (cid:9)
`
`"
`
`FIG. 13
`CPU
`
`10a
`
`-13
`
`23
`li
`FIRST DELAY TIME
`CONTROL UNIT
`
`SECOND DELAY
`TIME CONT
` UNIT
`1J
`24
`
`dl
`
`d2
`17-1,17
`1_DQe.n[1](1_DQe)
`1_DQo-n[1] (1_DOo)
`(DQ.n[1]:DQ.n (cid:9) DO)
`
`-
`
`O_DQe.n[1](O_DQe)
`(DQ.n[1]:DQ.rDQ)
`ODQO-n[1](ODQO)
`(DO .n[1]:DQ.rDQ)
`
`—
`
`19a-1,19a
`DW1a (cid:9)
`._.._.._._._.._._.._._.'-..-(cid:127)(cid:127)(cid:127)(cid:127)--(cid:127)--(cid:127)(cid:127)(cid:127)(cid:127)-(cid:127)-(cid:127)-(cid:127)--(cid:127)----(cid:127)
`¶
`L ------------ 1'
`__________ _______
`
`FFIa (cid:9)
`FF2a -
`
`DO-n[1]
`
`DQ- DO'
`fl (cid:9)
`j
`
`!
`
`' 1 (cid:9)
`
`I (cid:9)
`
`I
`
`FF6
`
`DR1 (cid:9)
`
`FF1-3
`
`FF1-4
`DR2 (cid:9)
`FF8 (cid:9)
`:-----------------------------------------
`-----
`
`: (cid:9)
`
`20-1,20
`19a-k,19a
`DW1 a (cid:9)
`
`F/ (cid:9)
`----------------- (cid:9)
`tDR1 (cid:9)
`FF6 (cid:9)
`
`FF8 (cid:9)
`
`- -DR- (cid:9)
`
`1
`
`iii- iii (cid:9)
`t_i j
`_________
`
`FF5 (cid:9)
`_______ (cid:9)
`
`(DOnDO)
`
`- "
`
`FF2a
`
`
`
`
`
`---- - - -- - -:
`
`
`
`(D (cid:9)
`
`U-U
`I.,
`
`15n,15
`
`17-k,17 (cid:9)
`
`---
`
`(D]E
`
`ODQe(cid:127)n[kI(ODQe)
`(DO .ii[k]:DQ.n:DQ)
`O_DQQ(cid:127)n[kI(O_DQo)
`(DQ[k]:DQ-n:DQ)
`
`O_DQX-n
`
`14
`
`L
`
`-
`
`
`
`Go
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 14
`
`(cid:9)
`(cid:9)
`

`

`FIG. 14
`CPU
`
`lOb
`
`,13
`
`14
`
`MEMORY CONTROLLER
`18 (cid:9)
`
`16
`
`DIMM
`
`12
`
`CK1
`
`(DQS)
`
`NOT USED
`
`23
`ri
`FIRST DELAY TIME
`CONTROL UNIT
`SECOND DELAY
`TIME CONTROL UNIT
`1J
`24
`
`d2
`
`IDQe1[lj(IDQe)
`(DQ1[1]:DO1:DQ)
`
`--------------------
`
`-FF1
`
`L_j
`
`)DQ 1[1]:DQtDQ) - L
`[1](O DOe) -
`
`0DQe -
`
`
`- -------------
`DQ-1[1]
`DWR1
` FF2 rrT{ (DQ-1:DQ)
`21
`F
`
`(DO 1[1]:DQ-1 (cid:9) DQ)
`15-1,15
`17-k17----
`IDQe .1[k])IDQe)
`(DQl[k]DO1:DQ)
`
`(DQ 1IkI:DQ.1 :DQ)
`ODQe. l[I(O DOe)
`
`(DQ (cid:9) 1[k]: DI (cid:9) DO)
`
`-
`
`FF6
`
`FF8
`
`---
`
`FF7
`
`-
`
`FF5
`
`------I
`
`:
`
`:
`
`: (cid:9)
`:
`: (cid:9)
`: (cid:9)
`20-1,20 (cid:9)
`FF2
`I --------- DQ-1 [k]
`i
`(DQ-1:D0
`FF1
`21
`-
`-
`--
`-
`I------ - --
`FF4
`FF6
`
`
`DWR1 1 1
`
`-
`
`DWR2FF711
`
`OR
`
`,
`20-k20
`
`ci)
`
`ci)
`
`0
`oft
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 15
`
`

`

`FIG. 15
`
`CPU
`
`10b
`
`13 (cid:9)
`
`14 (cid:9)
`
`MEMORY CONTROLLER
`18 (cid:9)
`
`16
`
`12 11 I DIMM
`14 14
`ICK1
`
`DQS-n
`
`NOT USED
`DWRO
`
` ________
`FF2 (cid:9)
`1DWR1
`---
`
`DQn[1 I
`(DQ-n:DQ)
`
`H
`
`DWR2
`
` FF5
`
`D
`(I)
`
`ci)
`
`ci)
`
`JI
`
`23
`ri
`FIRST DELAY TIME
`CONTROL UNIT
`SECOND DELAY
`OL UNIT TIME CONTR
`
`rJ
`24
`
`17-1,17-- .
`
`1_DQe n[1] (1_DQe)
`
`1DQn[l11DOo
`(DO r[1]:DQ:DO)
`O_DQe-ri[l](O_DQe)
`
`CDQo.11[(CDQo)
`(DO -rH:DQ-:DQ)
`15 n,15
`17-k,17-
`IDQe.r[k](IDQe)
`(DQnDQn:DO)
`
`(DQ(cid:127)r[k]:DQn:DQ)
`
`O_DQe-[k](O_DQe)
`
`ODQo.r[(ODOo)
`(DQr[k]:DQn:DQ)
`
`ODQX-n
`
`-
`
`L_
`FF1 (cid:9)
`. :FF3L
`
`
`FF6
`
`
`
`L--
`
`--
`
`------—
`
`FF1
`
`20-1,20
`
` 19-k,19 .
`
`.
`
`DWRl
`
`- DO-n[k]
`(DO-n:DQ
`
`21
`FE- -
`
`-
`
`
`
`FF6
`
`FF8 (cid:9)
`
`LDWR2FF7rL
`
`- -
`
`- FF4
`
`
`
`20-k,20
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 16
`
`(cid:9)
`(cid:9)
`(cid:9)
`

`

`FIG. 16
`
`DWR
`
`IN (cid:9)
`
`OUT (cid:9)
`
`--------------- (cid:9)
`Dt1
`----------------- (cid:9)
`
`- ------------- (cid:9)
`Dt2
`------------ (cid:9)
`
`DOUT
`
`DIN
`
`FIG. 17
`DWR
`
`31-1,31 (cid:9)
`
`31-2,31 (cid:9)
`
`31-3,31 (cid:9)
`
`31-4,31 (cid:9)
`
`31-5,31 (cid:9)
`
`31-6,31 (cid:9)
`
`31-7,31 (cid:9)
`
`31-8,31 (cid:9)
`
`31-9,31 (cid:9)
`
`31-10,31
`
`IN-1 (IN)
`
`OUT-2(OUT)
`
`ft
`
`00
`
`OUT-1 (DOUT)
`
`I N-2(DI N)
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 17
`
`(cid:9)
`

`

`U.S. Patent (cid:9)
`
`Sep. 13, 2011
`
`Sheet 17 of 20 (cid:9)
`
`US 8,020,022 B2
`
`FIG. 18A
`
`33-1 (cid:9)
`
`32-2 (cid:9)
`
`31
`
`N-1
`
`OUT-1
`
`OUT-2
`
`IN-2
`
`33-2
`
`FIG. 18B
`
`FIG. 18C
`
`33-1 (cid:9)
`
`32-2 (cid:9)
`
`31
`
`33-1 (cid:9)
`
`32 -2 (cid:9)
`
`31
`
`N-1
`
`BOUT-1 (cid:9)
`
`IN-1_
`
`.OUT-1
`
`OUT-2
`
`_IN-2
`
`OUT-2 Ar
`
`— IN-2
`
`33-2
`
`CONT
`
`33-2
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 18
`
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`

`

`FIG. 19
`
`CPU
`
`23
`rJ
`FIRST DELAY TIME
`CONTROL UNIT
`SECOND DELAY
`TIME CONTROL UNIT
`1J
`24
`
`I 0c
`
`13
`
`CLK
`
`dl
`d2
`IDQe.1[l](IDQe)
`
`(DQ1[1]DQ-1:DQ)
`
`15-1,15
`
`IDo.1[kiDQo)
`
`ODo.1N(OJQo)
`(DQ{kJ:DQ-l:DO)
`
`0DQX-1
`
`-
`
`
`
`DIMM
`
`11
`-.-12
`CK1
`
`DQS-1
`(DOS)
`
`D
`(I)
`
`DQ-1 [k]
`
`ci)
`
`ci)
`
`14
`
`MEMORY CONTROLLER
`1 16
`
`CK2 C ^Q ^F F O^
`
`FFO
`
`18 (cid:9)
` 19a-119a
`
`1TT
`
`r1 (cid:9) :::
`
`!
`
`FF6 - (cid:9)
`' 'i[:
`
`::
`
`DWR2a
`
`20- 1 , 20
`
`(cid:127) (cid:9)
`
`i
`i9-r (cid:9) 9a
`
`::::
`
`FF5 FF5
`
`
`
`FFla
`
`tl
`NOTUSEDIII FF5— (cid:9) LfJ
`
`I FF8 (cid:9)
`
`DWR2a FF7
`
`
`OR 7Gf 20-k,20
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 19
`
`(cid:9)
`

`

`FIG. 20
`CPU
`
`10c ^
`
`x.13
`
`13 (cid:9)
`
`14
`
`MEMORY CONTROLLER
`16
`-='-----------------
`
`12
`
`11r
`
`DIMM
`14
`I CK1
`
`23
`FIRST DELAY TIME
`CONTROL UNIT
`SECOND DELAY
`TIME CONTROL UNIT
`
`24
`
`dl
`d2
`IDQe-u[l]([_DQe)
`I_DQo-n[i]
`(DQ(cid:127)n[1]:DQ(cid:127)n:D Q)
`
`(DQ-n[i]; DQ-n; DQ)
`0 DQo-n[1] (o_DQo)
`(DQ-n[l]:DQ-n:DQ)
`
`15-n,15
`I DQe-n[k] (I DQe)
`_
`_
`I_
`DQon[k](I_
`DQo)
`(DQ n[k] (cid:9) DQ n:CQ)
`17-k17 _
`0DQe-n[k](0DCe)
`(DQ n[k];DQn;DQ)
`
`(DQ-n[k]: DQ-n: DQ)
`0_DQX-n
`
`18 (cid:9)
`
`CK2
`
`19a-1,19a
`
`FFO (cid:9)
`
`-
`
`! (cid:9)
`
`------ (cid:9) -- (cid:9) -- (cid:9)
`
`- (cid:9)
`
`--------- (cid:9) -----1---------- (cid:9) --- (cid:9) ------
`
`-- - (cid:9)
`
`- (cid:9)
`
`- (cid:9) ---------- }----- (cid:9)
`
`- (cid:9)
`
`-- (cid:9)
`
`- (cid:9)
`
`DWR1a (cid:9)
`
`FF2a (cid:9)
`- (cid:9) ----- (cid:9)
`
`- (cid:9)
`
`i
`
`Ir
`
`; ; ; (cid:9)
`
`;
`i
`r ; (cid:9)
`
`FF6
`
`FF8 (cid:9)
`
`------- (cid:9) --------------; (cid:9)
`
`DWR2a
`
`FF7
`
`DQS-n
`(DQS)
`
`
`
`
`
`0
`co
`
`
`
`19a-k,19a : (cid:9)
`(cid:127) 20-1 20 ,
`
`
`--------- --- (cid:9) -------- (cid:9) 1- (cid:9)
`r (cid:9)
`-- (cid:9)
`-
`-- (cid:9)
`DWR1a
`tF
`F1a
`------ (cid:9)
`- (cid:9)
`^; ------
`' I
`
`
`
`------
`
`- (cid:9) -- (cid:9)
`
`- (cid:9)
`
`--
`
`: (cid:9)
`
`:
`
`- (cid:9)
`
`- (cid:9)
`
`----- (cid:9)
`
`,: (cid:9)
`
`
`
` - -- (cid:9)
`
`--- (cid:9) --- (cid:9)
`
`- (cid:9)
`
`! (cid:9)
`
`--
`
`I
`
`'
`
`DQ-n [k]
`(DQ-n:DQ)
`FF2a
`
`;FF6
`'
`
`NOT USED
`
`FF5
`
`i (cid:9)
`
`;
`
`F8
`
`DWR2a FF7 (cid:9)
`
`---------------------------------------------- ------ (cid:9)
`
`H
`
`----- T ---I ;
`
`00
`
`OR (cid:9)
`
`20-k,20
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 20
`
`

`

`FIG. 21
`
`DWR
`
`31-1,31 (cid:9)
`
`31-2,31 (cid:9)
`
`31-3,31 (cid:9)
`
`31-4,31 31-5,31 (cid:9)
`
`31-6,31 (cid:9)
`
`31-7,31
`
`31-8,31 (cid:9)
`
`31-9,31 (cid:9)
`
`31-10,31
`
`N-1 (IN)
`
`OUT-2(OUT)
`
`^^^ (cid:9)
`
`[,! (cid:9)
`
`I! (cid:9)
`
`^'
`
`" (cid:9)
`
`L
`
`" H " (cid:9)
`
`"L"
`
`"H" (cid:9)
`
`[I! (cid:9)
`
`[I!
`
`OUT-1(DOUT)
`
`IN-2 (DIN)
`
`CD
`
`ft
`
`00
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 21
`
`(cid:9)
`

`

`US 8,020,022 B2
`
`1
`DELAY TIME CONTROL OF MEMORY
`CONTROLLER
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This application is related to and claims priority to Japa-
`nese patent application no. 2007-241610 filed on Sep. 18,
`2007, in the Japan Patent Office, and incorporated by refer-
`ence herein.
`
`BACKGROUND
`
`1. Field
`The memory control circuit, delay time control device, and
`delay time control method relate to a technique for control-
`ling read/write operations for a plurality of memories to
`which a clock signal line is wired through the daisy chain
`connection, as in, e.g., a DDR3 memory interface, by supply-
`ing a clock signal through the clock signal line.
`2. Description of the Related Art
`Recently, the DDR3 (Double Data Rate 3) memory inter-
`face has been standardized as standards of a DRAM (Dy-
`namic Random Access Memory) by JEDEC (Joint Electron
`Device Engineering Council) (see, e.g., JDEC STANDARD
`(JESD79-3; DDR3 SDRAM Standard). Unlike the hitherto
`practiced DDR (Double Data Rate) memory interface and
`DDR2 (Double Data Rate 2) memory interface (see, e.g.,
`Japanese Laid-open Patent Publication No. 2003-99321, No.
`2005-78547, and No. 2005-209168), the DDR3 memory
`interface employs fly-by topology for connection between a
`memory controller and a DIMM (Dual Inline Memory Mod-
`ule).
`FIG. 1 is a block diagram showing a configuration example
`of the recently proposed DDR3 memory interface, and FIG. 2
`is a block diagram for explaining a write leveling operation in
`the DDR3 memory interface.
`As shown in FIG. 1, for example, the fly-by topology is
`configured such that a signal line for each of a clock signal
`CK, an address signal Add and a command signal CMD is
`wired from a memory controller 90 to a plurality (number n)
`of SDRAMs (Synchronous Dynamic Random Access
`Memories) 92-1 to 92-n (n is a natural number of 2 or more)
`on a DIMM module 91 through the daisy chain connection.
`On the other hand, data signal lines for data signals DQ and
`data strobe signals DQS are wired from the memory control-
`ler 90 to the plurality of SDRAMs 92-1 to 92-n on the DIMM
`module 91, respectively.
`In the following description, regarding characters denoting
`the SDRAMs, when one among the plurality of SDRAMs
`needs to be specified, any of characters 92-1 to 92-n is used,
`while a character 92 is used when an arbitrary SDRAM is to
`be indicated.
`Also, regarding characters denoting the data signals, when
`one among the plurality of data signals needs to be specified,
`any of characters DQ-1 to DQ-n is used, while a character DQ
`is used when an arbitrary data signal is to be indicated.
`Further, regarding characters denoting the data strobe sig-
`nals, when one among the plurality of data strobe signals
`needs to be specified, any of characters DQS-1 to DQS-n is
`used, while a character DQS is used when an arbitrary data
`strobe signal is to be indicated.
`Thus, in the DDR3 memory interface, because the clock
`signal line for the clock signal CK is wired to the plurality of
`SDRAMs 92-1 to 92-n through the daisy chain connection
`and a propagation delay is generated, the clock signal CK
`output from the memory controller 90 cannot reach all the
`
`10 (cid:9)
`
`SDRAMs 92-1 to 92-n at the same time. According to the
`JEDEC standards, for example, a length Li of outer dimen-
`sion of the DIMM module 91 is determined to be 133 mm.
`Assuming a data transmission speed to be 7 ps/mm, therefore,
`5 a difference of about 1 ns is generated in arrival time of the
`clock signal CK between the SDRAM 92-1 disposed at one
`end and the SDRAM 92 -n disposed at the other end of the
`DIMM module 91 in the lengthwise direction thereof
`(namely, 7 ps/mmx133 mm=931 ps).
`For that reason, according to the JEDEC standards, it is
`specified to employ the write leveling function in the DDR3
`memory interface.
`The term "write leveling function" refers to the function of
`sampling the clock signal CK by using the data strobe signal
`15 DQS output from the memory controller 90, detecting the
`phase relationship between the data strobe signal DQS and
`the clock signal CK, and adjusting (compensating) a delay
`time of the data strobe signal DQS. The write leveling func-
`tion is realized, as shown in FIG. 2, by incorporating variable
`20 delay circuits 93-1 to 93-n, which can change respective delay
`times of the data strobe signals DQS-1 to DQS-n, in the
`memory controller 90 corresponding to the plurality of
`SDRAMs 92-1 to 92-n, respectively.
`In the following description, regarding characters denoting
`25 the delay circuits, when one among the plurality of delay
`circuits needs to be specified, any of characters 93-1 to 93-n
`is used, while a character 93 is used when an arbitrary delay
`circuit is to be indicated.
`More specifically, for the data strobe signals DQS-1 to
`3o DQS-n output respectively to the plurality of SDRAMs 92-1
`to 92-n to which the clock signal line is wired through the
`daisy chain connection, a CPU (Central Processing Unit, not
`shown) sets respective delay times t1-1 to t1 -n based on the
`data signals DQ-1 to DQ-n output from the plurality of
`35 SDRAMs 92-1 to 92-n so that the data strobe signals DQS-1
`to DQS-n are adjusted to be input respectively to the plurality
`of SDRAMs 92-1 to 92-n substantially at the same time as the
`clock signal CK for each SDRAM.
`In other words, for example, at the time of completion of
`40 the write leveling, the data strobe signals DQS are delayed
`through the respective delay times t1-1 to t1 -n in the delay
`circuits 93-1 to 93-n which correspond to the SDRAMs 92-1
`to 92-n on the DIMM module 91, respectively, whereby the
`data strobe signal DQS and the clock signal CK are input in
`45 phase to each of the SDRAMs 92-1 to 92-n.
`Thus, in the DDR3 memory interface, the difference in the
`delay time caused in the write operations between the
`memory controller 90 and the plurality of SDRAMs 92 is
`adjusted by employing the write leveling function.
`Additionally, in the above-described case, the delay times
`t1-1 to t1 -n are not equal to each other because the clock
`signal CK is input to the SDRAMs 92-1 to 92-n via the clock
`signal line through the daisy chain connection.
`Although, the DDR3 memory interface compensates the
`55 arrival time when the data strobe signals DQS-1 to DQS-n
`arrive at the SDRAMs 92-1 to 92-n in the write operations
`according to the JEDEC standards as described above, com-
`pensations of the signal arrival time in read operations are not
`provided with the JEDEC standards.
`FIG. 3 is a block diagram explaining the read operation of
`the conventional DDR3 memory interface.
`The SDRAMs 92-1 though 92-n output data signals DQ-1
`though DQ-n and the data strobe signals DQS-1 through
`DQS-n to the memory controller 90 on receiving the clock
`65 signal CK output from the memory controller 90 via the data
`signal line in the daisy chain connection in the read operation
`as shown in FIG. 3.
`
`50 (cid:9)
`
`60 (cid:9)
`
`Samsung Electronics Co., Ltd.
`Ex. 1006, p. 22
`
`

`

`US 8,020,022 B2
`
`3
`Therefore, the data signal DQ-n and the data strove signal
`DQS-n output from the SDRAM 92-n to which the clock
`signal CK is input lastly arrives at the memory controller 90
`approximately 1 ns after the data signal DQ-1 and the data
`strobe signal DQS-1 output from the SDRAM 92-1 to which 5
`the clock signal CK is input firstly where the data transmis-
`sion speed is 7 ps/mm as the case described above. 7 ps/mmx
`133 mm=931 ps.
`The delay on the order of 1 ns will become greater than a
`typical data period of the DDR3 memory interface, at mini-
`mum 0.625 ns, so that the delay may affect in reading data
`from the SDRAM 92.
`
`10
`
`SUMMARY
`
`15
`
`A memory control circuit having a write leveling function
`and controlling read/write operations by supplying a clock
`signal to a plurality of memories through a clock signal line
`which is wired to the plurality of memories through daisy
`chain connection is comprising, for each of the plurality of 20
`memories, a first variable delay unit for delaying, in the write
`operation, a data strobe signal output to the memory by a first
`delay time that is set by utilizing the write leveling function
`and a second variable delay unit for delaying, in the read
`operation, a data signal input from the memory by a second 25
`delay time that is set based on the first delay time.
`Additional objects and advantages of the embodiment will
`be set forth in part in the description which follows, and in
`part will be obvious from the description, or may be learned
`by practice of the embodiment. The object and advantages of 30
`the embodiment will be realized and attained by the elements
`and combinations particularly pointed out in the appended
`claims.
`It is to be understood that both the foregoing general
`description and the following detailed description are exem- 35
`plary and explanatory only and are not restrictive of the
`embodiment, as claimed.
`These together with other aspects and advantages which
`will be subsequently apparent, reside in the details of con-
`struction and operation as more fully hereinafter described 40
`and claimed, reference being had to the accompanying draw-
`ings forming a part hereof, wherein like numerals refer to like
`parts throughout.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`45
`
`4
`FIG. 8 is a block diagram for explaining calculation for-
`mulae used to determine a first delay time in the first delay
`time control unit of the information processing apparatus
`according to the first embodiment;
`FIG. 9 is a block diagram for explaining the calculation
`formulae used to determine the first delay time in the first
`delay time control unit of the information processing appa-
`ratus according to the first embodiment;
`FIG. 10 is an explanatory diagram for explaining a write
`operation using a first variable delay circuit in the information
`processing apparatus according to the first embodiment;
`FIG. 11 is an explanatory diagram for explaining a read
`operation using a second variable delay circuit in the infor-
`mation processing apparatus according to the first embodi-
`ment;
`FIG. 12 is a circuit diagram showing a portion of the
`memory controller, which corresponds to the SDRAM-1, in
`the information processing apparatus according to a modifi-
`cation of the first embodiment;
`FIG. 13 is a circuit diagram showing a portion of the
`memory controller, which corresponds to the SDRAM-n, in
`the information processing apparatus according to the modi-
`fication of the first embodiment;
`FIG. 14 is a circuit diagram showing a portion of a memory
`controller, which corresponds to SDRAM-1, in an informa-
`tion processing apparatus according to a second embodiment;
`FIG. 15 is a circuit diagram showing a portion of the
`memory controller, which corresponds to SDRAM-n, in the
`information processing apparatus according to the second
`embodiment;
`FIG. 16 is a diagram for explaining the function of a third
`variable delay circuit of the memory controller in the infor-
`mation processing apparatus according to the second embodi-
`ment;
`FIG. 17 is a block diagram showing a configuration
`example of the third variable delay circuit in the information
`processing apparatus according to the second embodiment;
`FIGS. 18A to 18C are circuit diagrams each showing a
`configuration example of a unit circuit of the third variable
`delay circuit in the information processing apparatus accord-
`ing to the second embodiment;
`FIG. 19 is a circuit diagram showing a portion of the
`memory controller, which corresponds to the SDRAM-1, in
`the information processing apparatus according to a modifi-
`cation of the second embodiment;
`FIG. 20 is a circuit diagram showing a portion of the
`memory controller, which corresponds to the SDRAM-n, in
`the information processing apparatus according to the modi-
`fication of the second embodiment; and
`FIG. 21 is a block diagram for explaining another example
`of use of the third variable delay circuit in the information
`processing apparatus according to the second embodiment.
`
`DETAILED DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`Embodiments will be described below with reference to the
`drawings.
`
`[1] First Embodiment
`
`FIG. 1 is a block diagram showing a configuration example
`of the known DDR3 memory interface;
`FIG. 2 is a block diagram for explaining a write leveling
`operation in the known DDR3 memory interface; (cid:9)
`FIG. 3 is a block diagram for e