United States Patent (19)
`Jones et al.
`
`USOO595.9926A
`Patent Number:
`11
`(45) Date of Patent:
`
`5,959,926
`Sep. 28, 1999
`
`54 PROGRAMMABLE POWER SUPPLY
`SYSTEMS AND METHODS PROVIDING A
`WRITE PROTECTED MEMORY HAVING
`MULTIPLE INTERFACE CAPABILITY
`75 Inventors: Brian W. Jones, Richardson; Alan
`Mark Morton, Dallas, both of Tex.
`73 Assignee: Dallas Semiconductor Corp., Dallas,
`TeX.
`
`21 Appl. No.: 09/059,244
`22 Filed
`Apr. 13, 1998
`
`a
`
`lays
`
`CC
`
`4,874.965 10/1989 Campardo et al. .................. 307/272.3
`4.885,476 12/1989 Mahabadi.......
`... 307/272.3
`4,886,984 12/1989 Nakaoka .............................. 307/272.3
`(List continued on next page.)
`OTHER PUBLICATIONS
`Dallas Semiconductor Data Book, DS 1215 and DS 1217
`data sheets, 1987-88.
`The TTL Data Book, Texas Instruments, Inc. pp. 7-460 to
`7-464, 1980–81.
`Primary Examiner Huan Hoang
`Attorney, Agent, or Firm Jenkens & Gilchrist
`57
`ABSTRACT
`A programmable power controller controls power between a
`primary power Source and a Secondary power Source and
`powering first circuitry. The primary power Source has a first
`Voltage and the Secondary power Source has a Second
`Voltage. A control register has a first field, which is field used
`to activate circuitry used to direct power from the primary
`power Source to the Secondary power Source. First logic
`circuitry compares the first Voltage and the Second Voltage tO
`determine which is greater and then couples the primary
`power Source or the Secondary power Source, depending
`upon which is greater, to power the first logic circuitry,
`References Cited
`Second logic circuitry, and memory. The memory is coupled
`U.S. PATENT DOCUMENTS
`to the first logic circuitry and is read and written to via an
`input/output buffer. The Second logic circuitry is coupled to
`2.
`is: 10/1967 Arai i al. ...............................
`the memory and to Said first logic circuitry and activates
`3. 94.2 Ronaldson, Jr. ..................... 3.2 write protection circuitry to prevent writing to the memory
`4.013,902 3/1977 SE m.
`... 307f268
`if the Secondary power source is powering the first logic
`4,034,348 7/1977 Rathbun .......
`... 364/200
`circuitry, the second logic circuitry, and the memory. A
`4,365,291 12/1982 Zanchi et al. ...
`... 364/200
`multiple Voltage interface System comprises a first voltage
`4,500,953 2/1985 Takezoe et al. .................
`... 364/200
`interface able to be electrically coupled to first power Supply
`4,571,602 2/1986 De Schamphelaere et al. ....... 346/160
`having a first Voltage level, a Second Voltage interface able
`4,571,603 2/1986 Hornbeck et al. ...............
`... 346/160
`to be electrically coupled to a Second power Supply having
`4,591,745 5/1986 Shen .....................
`... 307/592
`a Second Voltage level and Switching circuitry to Switch Said
`4,612,632 9/1986 Olson rthy".
`... 365/o
`Second Voltage interface on to receive and adjust Said Second
`2.3% 121: Nort y .
`- - - - 3. Voltage level to power an application System or to Switch
`4.670,676 6/1987 Nishitani.
`... 307/592
`Said first voltage interface on to receive and adjust Said first
`4797.584 1/1989 Aguti et al.".
`... 307564
`Voltage level to power Said application System.
`4,812,679 3/1989 Mahabadi.........
`307/272.1
`4,818,904 4/1989 Kobayshi et al. ...................... 307/594
`
`Related U.S. Application Data
`63 Continuation of application No. 08/660,131, Jun. 7, 1996,
`abandoned.
`6
`
`52)
`
`O X
`
`O
`
`- - - - - - - - - - - - - - - - - - - - - - - - - - -365,226, 36522 I.2.
`-- O - - - - - - - - - - - - - - - - - - - - - - - - - -
`3 65/189 1: 326so
`• ----
`58 Field of Search ..................................... 365,226, 22,
`365/229, 195, 196, 206, 189.11; 307/43;
`326/80
`
`56)
`
`5 Claims, 13 Drawing Sheets
`
`
`
`
`
`
`
`WCCF
`
`PRE IN
`LVLSHIFT
`
`- - - - - - - - - - - - - - - - - - -
`
`
`
`Petitioner Intel Corp., Ex. 1045
`IPR2023-00783
`
`

`

`5,959,926
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`4,900,950 2/1990 Dubujet ................................ 307/272.3
`4,902,907 2/1990 Haga et al. .
`... 307/272.3
`4,931,985
`6/1990 Glaise et al.......
`... 364/900
`4,953,077 8/1990 Alvarez, II et al.
`. 364/200
`4,970,418 11/1990 Masterson .....
`... 307/480
`4,975,883 12/1990 Baker et al.
`365/226
`5,019,966 5/1991 Saito et al. .............................. 364/200
`
`
`
`1/1992 Silver ...................................... 395/325
`5,081,701
`5,307,318 4/1994 Nemoto ................................... 365/226
`5,357,458 10/1994 Yu et al. ................................. 365/226
`5,490,117
`2/1996 Oda et all
`365/226
`2 : - - 2
`to r
`5,530,672 6/1996 Konishi et al. ......................... 365/226
`5,537,360 7/1996 Jones et al. ............................. 365/226
`5,663,918 9/1997 Javanifard et al. ..................... 365/226
`5,781,780 7/1998 Walsh et al. ....................... 395/750.01
`
`Petitioner Intel Corp., Ex. 1045
`IPR2023-00783
`
`

`

`U.S. Patent
`
`Sep. 28, 1999
`
`Sheet 1 of 13
`
`5,959,926
`
`110
`
`- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
`BIT 0
`BIT 6 BIT 5 BIT 4.
`BIT 3 BT 2 BT 1
`BIT 7
`TRICKLE
`CHARGE
`RECISTER
`
`OF 16 SELECT
`
`1 OF 2
`SELECT
`
`OF 3
`SELECT
`
`
`
`
`
`Petitioner Intel Corp., Ex. 1045
`IPR2023-00783
`
`

`

`Sep. 28, 1999
`Sep. 28, 1999
`
`Sheet 2 of 13
`Sheet 2 of 13
`
`5,959,926
`5,959,926
`
`U.S. Patent
`U.S. Patent
`
`
`
`
`
`DATA
`
`/
`
`RD_UZ
`BUS2L
`
`PWwRUPD—[>0—d
`
`cb
`
`BIT
`
`BITZ
`
`t
`
`FIG. 2C
`
`Petitioner Intel Corp., Ex. 1045
`IPR2023-00783
`
`Petitioner Intel Corp., Ex. 1045
`IPR2023-00783
`
`

`

`5,959,926
`5,959,926
`2NO“UL<
`
`
`
`2880SHvd300030{|
`
`|S19773S
`
`peefpPeee0Baoe‘eamt<<vivvivavivavivGvivaviv
`2118laiajaaafeulayo-a
`20cd+0sa90£0GeDidSSee
`annafrofraandfeeanid
`anocuaiunO4gudHOIV]Soe‘9P|231£9}
`()09()()0()0()0)0.
`C<1pNaay
` —_91v
`
`
`
`
`
`ZWS0SHivd400030‘Gia
`
`U.S. Patent
`U.S. Patent
`
`Sep. 28, 1999
`Sep. 28, 1999
`
`Sheet 3 of 13
`Sheet 3 of 13
`
`ry
`
`mod—i—
`
`
`
`JIdIIAWSLOFTIS
`
`ugLig
`gif
`
`
`
`
`
`
`
`VY
`
`VVY
`
`cONady
`
`oLYddy
`
`ZYOGY
`
`oryady
`
`Petitioner Intel Corp., Ex. 1045
`IPR2023-00783
`
`Petitioner Intel Corp., Ex. 1045
`IPR2023-00783
`
`
`

`

`DATA
`
`U.S. Patent
`U.S. Patent
`
`RD_LZ
`BUS2L
`
`Sep. 28, 1999
`Sep. 28, 1999
`
`Sheet 4 of 13
`Sheet 4 of 13
`
`5,959,926
`5,959,926
`
`PwRUP >>>0—d
`
`
`
`PWRON
`
`PWRON
`
`
`
`vec
`
`POS
`
`NEG
`VREF >——|
`
`J
`
`OUTU
`
`FIG. 3B
`
`Petitioner Intel Corp., Ex. 1045
`IPR2023-00783
`
`Petitioner Intel Corp., Ex. 1045
`IPR2023-00783
`
`

`

`Sep. 28, 1999
`Sep. 28, 1999
`
`Sheet S of 13
`Sheet 5 of 13
`
`5,959,926
`5,959,926
`
`U.S. Patent
`
`U.S. Patent
`
`
`
`8
`
`Petitioner Intel Corp., Ex. 1045
`IPR2023-00783
`
`Petitioner Intel Corp., Ex. 1045
`IPR2023-00783
`
`

`

`U.S. Patent
`
`Sep. 28, 1999
`
`Sheet 6 of 13
`
`5,959,926
`
`R54
`
`R
`
`R41
`
`R
`
`strict,
`FIC. 3C
`
`R
`
`R40
`
`70
`
`R36
`
`R42
`
`i.e. RREFOUT
`
`RDIVIN
`
`8
`
`R21
`
`R2O
`
`FIC. 3D
`
`RDIVOUT
`
`20TTOVCC
`VcC2CTL
`19
`NC
`VBATOLT2
`X13 8PF
`NC
`4
`17
`VCCF
`X25 16D SDO
`FIC. 4A NC
`6
`15 OSD
`INTOLL 7
`14SCLK
`NC
`8
`13 ONC
`INT1
`9
`12
`CE
`GND
`10
`11
`SERMODE
`
`FIC. 4B
`
`
`
`VcC2
`VBAT2
`X1 O3
`X24
`NC 5
`INT06
`INT1 O7
`
`16Vcci
`15DPF
`4 VCCF
`13 SDO
`2DSD
`11SCLK
`1 OCE
`9 SERMODE
`
`Petitioner Intel Corp., Ex. 1045
`IPR2023-00783
`
`

`

`U.S. Patent
`
`Sep. 28, 1999
`
`VS‘Old
`
` JIGONNSS
`
`419A
`
`OWYIS
`
`UTS
`
`Sheet 7 of 13
`
`5,959,926
`
`Petitioner Intel Corp., Ex. 1045
`IPR2023-00783
`
`Petitioner Intel Corp., Ex. 1045
`IPR2023-00783
`
`
`

`

`U.S. Patent
`
`Sep. 28, 1999
`
`SC
`S.
`BAT
`VCCIF
`PF
`GND
`
`SCLK
`SD
`SDO
`CE
`SERMODE
`
`POWER
`CONTROL
`AND TRICKLE
`CHARGER
`
`V
`CC
`
`SERIAL
`INTERFACE
`
`INPUT
`SHIFT
`REGISTER
`
`5,959,926
`
`Sheet 8 of 13
`275 KHZ
`X1
`X2
`CLOCK/CALENDAR
`LOGIC
`
`CLOCK, CALENDAR,
`AND ALARM
`REGISTERS
`CONTROL
`REGISTERS
`
`
`
`
`
`USER
`RAM
`
`INTO
`NT
`
`FIG. 6B
`
`
`
`SYSTEM
`VCC
`
`A
`
`
`
`
`
`PRIMARY POWER SUPPLY
`
`SECONDARY POWER SUPPLY
`
`Petitioner Intel Corp., Ex. 1045
`IPR2023-00783
`
`

`

`U.S. Patent
`U.S. Patent
`
`Sep. 28, 1999
`Sep. 28, 1999
`
`Sheet 9 of 13
`Sheet 9 of 13
`
`5,959,926
`5,959,926
`
`
`
`
`
`
`3
`
`131
`
`(PARRALLEL)
`
`g
`cs
`U
`1.
`m
`
`SHIFTREGARRAY
`
`M)
`
` SERMODE>
`SHIFT_OUT&
`SELI0&
`
`Petitioner Intel Corp., Ex. 1045
`IPR2023-00783
`
`Petitioner Intel Corp., Ex. 1045
`IPR2023-00783
`
`

`

`U.S. Patent
`
`Sep. 28, 1999
`
`Sheet 10 of 13
`
`5,959,926
`
`
`
`VCCF
`
`PRE IN
`
`FIC. 1 O
`
`OUTZ
`
`Petitioner Intel Corp., Ex. 1045
`IPR2023-00783
`
`

`

`U.S. Patent
`
`Sep. 28, 1999
`
`Sheet 11 of 13
`
`5,959,926
`
`FIC.
`
`1 1
`
`OOH
`
`CLOCK/CALENDAR
`READ ADDRESSES ONLY
`
`
`
`96 BYTES USER RAM
`READ ADDRESSES ONLY
`CLOCK/CALENDAR
`READ ADDRESSES ONLY
`
`96 BYTES USER RAM
`READ ADDRESSES ONLY
`
`FFH
`
`BIT 7
`O
`O
`0
`O
`O
`O
`M
`M
`M
`M
`M
`M
`M
`M
`
`06H
`
`86H
`
`HEX ADDRESS
`READ
`WRITE
`OOH
`8OH
`01H
`81H
`O2H
`82H
`O3H
`83H
`O4H
`84H
`OSH
`85H
`07H
`87H
`08H
`88H
`O9H
`89H
`OAH
`8AH
`OBH
`8BH
`OCH
`8CH
`ODH
`8DH
`OEH
`8EH
`OFH
`8FH
`
`OH
`
`1H
`
`90H
`
`91H
`
`
`
`
`
`H R
`
`10 DATE
`
`10 MONTH
`
`10 YEAR
`
`10 SEC ALARM
`
`10 MN ALARM
`
`O MN ALARM
`
`%O S E C
`s
`
`BIT O
`
`
`
`SEC
`
`MIN
`
`HOURS
`
`DAY
`
`DATE
`
`MONTH
`
`YEAR
`
`SEC ALARM
`
`MIN ALARM
`
`HOUR ALARM
`
`DAY ALARM
`
`SEC ALARM
`
`MIN ALARM
`
`HOUR ALARM
`
`DAY ALARM
`
`ALARM
`O
`
`ALARM
`
`CONTROL REGISTER
`
`STATUS REGISTER
`
`TRICKLE CHARGER REGISTER
`
`RESERVED
`
`FIC. 12
`
`% 10 SEC ALARM
`% %
`
`Petitioner Intel Corp., Ex. 1045
`IPR2023-00783
`
`

`

`U.S. Patent
`
`Sep. 28, 1999
`
`Sheet 12 of 13
`
`5,959,926
`
`-
`SHIFT
`INTERNAL
`STROBE
`
`SCLK
`
`CPOL = 1
`
`-
`
`CPOL=0
`
`SCLK
`
`SHIFT
`
`INTERNAL
`STROBE
`
`FIC. 13
`
`CE /
`
`N
`
`SDI 2A7 A6 A5 A4A3 A2 IAAOD7 D6D5 D4D3D2 D1 D02.
`HGH Z
`
`
`
`SDO
`
`FIC. 14
`
`c -
`
`SDIZA7 A6A5 A4A3 A2AAOZ
`SDO
`HIGH Z
`D7 D6D5 D4 D3D2 D1 DO
`FIC. 16
`
`Petitioner Intel Corp., Ex. 1045
`IPR2023-00783
`
`

`

`U.S. Patent
`
`Sep. 28, 1999
`
`Sheet 13 of 13
`
`5,959,926
`
`/
`SCLK IIIII -
`
`SDWSW2
`
`READ
`
`SDO
`
`DATA
`BYTE O/NBYTE
`FIC. 16
`
`DATA
`BYTE N
`
`CE /
`
`SCLK
`
`\
`
`I/O -(AOAAAAAAGADooD2DD4D50607)
`FIC. 1 7
`
`CE
`
`/
`
`N
`
`SCLK
`
`I I | |
`
`BYTE
`
`BYTE O
`BYTE
`FIC. 18
`
`BYTE N
`
`Petitioner Intel Corp., Ex. 1045
`IPR2023-00783
`
`

`

`1
`PROGRAMMABLE POWER SUPPLY
`SYSTEMS AND METHODS PROVIDING A
`WRITE PROTECTED MEMORY HAVING
`MULTIPLE INTERFACE CAPABILITY
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`This application is a continuation of application Ser. No.
`08/660,131, filed Jun. 7, 1996, now abandoned.
`This application hereby incorporates by reference: U.S.
`Pat. No. 5,148,051 (inventors: Kevin Deierling and Louis
`Rodriguez), issued Sep. 15, 1992; and U.S. Pat. No. 5,567,
`993 (inventors: Brian Jones and Alan Morton), issued Oct.
`22, 1996.
`
`PARTIAL WAIVER OF COPYRIGHT
`PURSUANT TO 1077 O.G. 22(Mar. 10, 1987)
`(C) Copyright, Dallas Semiconductor Corporation 1994.
`All of the material in this patent application is Subject to
`copyright protection under the copyright laws of the United
`States and of other countries. As of the first effective filing
`date of the present application, this material is protected as
`unpublished material.
`Portions of the material in the Specification and drawings
`of this patent application are also Subject to protection under
`the maskwork registration laws of the United States and of
`other countries.
`However, permission to copy this material is hereby
`granted to the extent that the owner of the copyright and
`maskwork rightS has no objection to the facsimile reproduc
`tion by anyone of the patent document or patent disclosure,
`as it appears in the United States Patent and Trademark
`Office patent file or records, but otherwise reserves all
`copyright and maskwork rights whatsoever.
`BACKGROUND
`Primary and Secondary power Supplies are often used in
`tandem to power various forms of application circuitry (e.g.,
`timekeeping). Inputs for primary power Supplies have typi
`cally been electrically coupled to System power Sources and
`inputs for Secondary power Supplies have been electrically
`coupled to back-up power Supplies (e.g., batteries), neither
`of which were rechargeable (e.g., rechargeable batteries).
`The power management circuitry used to control power
`Supplies have not allowed convenient mechanisms or meth
`ods that allow users to access and/or recharge batteries that
`are used as a power Supply. As a result, a user's choice has
`been rather limited. The user could use only the system
`power Supply (e.g., for the first power Source) and non
`rechargeable batteries for the primary and Secondary power
`Supplies. Alternatively, if the user insisted on rechargeable
`batteries, external charging circuitry was required, because
`necessary circuitry (if it existed at all) could not be easily
`integrated into an integrated circuit. AS referenced above, a
`reliable power Supply is an especially important consider
`ation in time-keeping applications, because users generally
`want to perpetually Save, back-up, and otherwise preserve
`timekeeping information (e.g., what time is it?). However, it
`is important in other applications as well.
`The use of multiple power Supplies in Systems can intro
`duce other complications to integrated circuits, especially
`CMOS integrated circuits. CMOS circuits powered by two
`different Supply levels cannot be directly connected together
`because of the diodes that typically exist in CMOS circuits
`for processing reasons and for ESD protection. In addition,
`
`15
`
`25
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`5,959,926
`
`2
`power consumption may increase when connecting circuits
`that are powered by power Supplies having differing power
`Supply levels.
`More Specifically, two situations generally apply: a circuit
`being Supplied by a higher Supply driving a circuit being
`powered by a lower Supply and a circuit being Supplied by
`a lower Supply level driving a circuit being powered by a
`higher Supply. In the first Situation, the circuit powered by a
`Voltage Supply having the lower Supply level generally has
`an input that transitions above the Voltage level correspond
`ing to the power Supply powering it, because it is being
`driven by the circuit with the higher supply. Since a diode
`typically exists between the input of the lower Supply level
`circuit and its Supply Voltage, any transition more than a
`diode drop above its supply will forward bias this diode and
`must not be allowed. Not only could this cause a latch-up
`problem within the circuit but the input pin would actually
`begin to Supply the current for the operation of the lower
`Supply level circuit.
`The Second situation addresses a power issue which has
`become very important over the last Several years. Input
`Signals from circuits that have lower Supply levels than those
`of the circuits being driven may not transition high enough
`to stop the flow of current through input buffers of the higher
`Supply level circuits. This will increase the power used by
`the higher Supply circuit.
`In addition, adding features to existing product lines
`introduces additional factors, Such as compatibility issues.
`New generations of parts are preferably compatible with
`previous generations of parts. In addition, combing addi
`tional features, Such as write protection, introduces addi
`tional requirements. This provides functionality to a broader
`application base with a single part. As a result, new features,
`Such as those discussed above, need to be able to be added
`to or integrated with existing Systems without altering the
`basic functionality or operation of previous generations of
`electrical devices (e.g., integrated circuits). For instance,
`when there are a limited number of pins, one cannot simply
`add an extra pin to invoke or activate the newly added
`feature. Thus, it complicates the addition of new features
`without affecting the basic functionality.
`
`SUMMARY OF THE INVENTIONS
`A programmable power controller controls power
`between a first power Source (e.g., a primary power Source
`or System power Source, which is typically non
`rechargeable) and a second power Source (e.g., a secondary
`power Source or a back-up power Supply, Such as a battery
`or capacitor that can be charged up). First and Second power
`Sources have a first voltage and Second Voltage respectively.
`The first and Second power Sources are preferably used to
`independently power first circuitry. Circuitry is used to
`compare the first voltage and the Second Voltage to deter
`mine which is greater and then to couple the greater of the
`first power Source or the Second power Source to the first
`circuitry to power the first circuitry. Preferred embodiments
`also provide the additional feature of providing write pro
`tection for data in memory, which is coupled to the first logic
`circuitry and is read and written to via an input/output buffer.
`This write protection capability is typically activated when
`a non-rechargeable backup Supply is being used. The Second
`logic circuitry is coupled to the memory and to Said first
`logic circuitry and activates write protection circuitry to
`prevent writing to the memory if the Secondary power
`Source is powering the first logic circuitry, the Second logic
`circuitry, and/or the memory. Write protection not only
`
`Petitioner Intel Corp., Ex. 1045
`IPR2023-00783
`
`

`

`3
`keeps the data from being corrupted during a main power
`failure, but also lowers the power requirements of the circuit
`in order to conserve the backup Supply. In particular, this
`additional write protect capability is performed by disabling
`the interface when the main Supply Voltage is less than the
`back-up Supply Voltage. And, as a result, the active power
`requirements are reduced by not allowing the user to acceSS
`the memory.
`While varying numbers of pins could be used, preferred
`embodiments use only three pins to provide this function
`ality. Preferred embodiments of the three pin programmable
`power Supply generally have three operating configurations:
`backup Supply is a non-rechargeable Supply (with need to
`protect memory data); backup Supply is either rechargeable
`or non-rechargeable (without need to protect data); and low
`power Single Supply.
`In addition, a control register has a first field that is used
`to activate circuitry that directs power from first power
`Source to the Second power Source. The control register also
`has a Second field used to Select an electrical path having a
`first voltage drop that ensures first power Source will have a
`higher Voltage than the Second power Source when first
`power Source is active under normal operating conditions.
`Diodes are preferably used to provide the necessary Voltage
`drops. The control register also has a third field used to Select
`an electrical path from a plurality of electrical paths, each
`electrical path having an unique Series resistance. The elec
`trical path governed by the Second field preferably incorpo
`rates at least one diode. The electrical paths governed by the
`third field have different resistances. The second power
`Source may be chargeable. The circuitry used to implement
`the conductive paths constitutes a trickle charger. However,
`if the Second power Source is not rechargeable, the trickle
`charger can be bypassed, So that preferred embodiments are
`compatible with previous generations of products that lack
`a trickle charger and/or do not use a chargeable power Source
`for the second power source. Preferred embodiments have
`three electrical paths governed by the third field with the
`following resistances: 2KS2, 4KS2, and 8KS2. In addition,
`preferred System embodiments allow the user to activate the
`programmable power Supply System and to Select the type of
`first and/or Second power Supply which is connected to the
`circuit via a first and Second pin. This circuit adds the
`additional capability for Second power Sources that are
`rechargeable, Such as rechargeable batteries or large capaci
`tors known as "Super caps'.
`More Specifically, preferred embodiments of the program
`mable power controller comprise first Switching circuitry,
`Second Switching circuitry, third Switching circuitry, control
`register, and a comparator. The first Switching circuitry is
`electrically coupled to a primary power Source and the
`Second Switching circuitry is electrically coupled to the
`Second Switching circuitry and to a first plurality of conduc
`tive paths, each of which has a Voltage drop that is not equal
`to any other, and the third Switching circuitry is electrically
`coupled to the first plurality of conductive paths and to a
`Second plurality of conductive paths, each of which has a
`resistance that is not equal to any other. The Second plurality
`of conductive paths are electrically coupled to a Secondary
`power Source. The control register has a first field, a Second
`field, and a third field. The first field is electrically coupled
`to first Switching circuitry and the Second field is electrically
`coupled to the Second Switching circuitry and the third field
`is electrically coupled to the third Switching circuitry. The
`comparator compares first Voltage of the primary power
`Source with the Second Voltage of the Second power Source
`to determine which is greater and then to couple the primary
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`power Source or the Secondary power Source depending
`upon which is greater to power first logic circuitry, Second
`logic circuitry, and memory. The Second logic circuitry
`determines whether the primary power Source or the Sec
`ondary power Source is powering the first logic circuitry and
`if the Secondary power Source is powering the first logic
`circuitry, the Second logic circuitry, and the memory, the
`Second logic circuitry activates write protection circuitry to
`prevent the memory from being written to, the Second logic
`circuitry coupled to the memory and to the Second logic
`circuitry.
`Preferred embodiments of the multiple voltage interface
`System comprise a first voltage interface able to be electri
`cally coupled to first power Supply having a first voltage
`level, a Second Voltage interface able to be electrically
`coupled to a Second power Supply having a Second Voltage
`level and Switching circuitry to Switch Said Second Voltage
`interface on to receive and adjust Said Second Voltage level
`to power an application System or to Switch Said first voltage
`interface on to receive and adjust Said first voltage level to
`power Said application System.
`All preferred embodiments are preferably integrated onto
`a single Silicon Substrate.
`The Switching circuitry is preferably a level translator
`(“lvlshift”) coupled to a first power input. The Switching
`circuitry Switches the first power input to a first power output
`or a Second power output depending upon Said first power
`input. The first power output coupled to the application
`System via a first conductive path and the Second power
`output coupled to the application System via a Second
`conductive path. Moreover, preferred embodiments also
`comprise at least one transistor having a Source, a gate, and
`a drain, wherein the first conductive path is electrically
`coupled to the Source of the transistor(s) and the Second
`conductive path is electrically coupled to the gate of the
`transistor(s), the drain of the transistor(s) coupled to said
`application System.
`There are numerous advantages of the preferred embodi
`ment discussed below. The System discussed above is com
`patible with and easily incorporates the functionality and
`purpose of the two pin programming mode that is discussed
`in the patent application (DSC-414) having U.S. application
`Ser. No. 08/264,389, which is incorporated by reference
`hereinabove. In particular, regarding the advantages associ
`ated with that circuitry, the disclosed charging Scheme is
`Simple enough that it provides continuous charging of
`back-up Supply while the primary power Source remains
`connected and is at an adequate Voltage. Similarly, the
`charging Scheme allows user flexibility in Setting both
`charging current and Voltage. The diode drop(S) also ensure
`that the charged Supply will always have a Smaller Voltage
`than the charging Supply So that the comparator that deter
`mines which Supply is connected to the circuit makes the
`proper decision when the charging Supply has Sufficient
`Voltage. Preferred embodiments also allow users to connect
`either rechargeable batteries or large capacitors, which are
`known as "Super caps', to Supply power to the integrated
`circuit (e.g., the Serial timekeeping chip). In addition, pre
`ferred embodiments also provide a protection against the
`charging of non-rechargeable power Supplies by defaulting
`to the dual power supply mode which disables the trickle
`charger. No external circuits are required.
`In addition to the above advantages, preferred embodi
`ments provide user with all the features of the previous two
`pin power Supply System plus a method of protecting the
`memory data and also conserving backup Supply energy.
`
`Petitioner Intel Corp., Ex. 1045
`IPR2023-00783
`
`

`

`S
`Preferred embodiments also provides protection against
`non-rechargeable battery back-charging. Preferred embodi
`ments provide for an easy Selection of power Supply con
`figuration by Simply grounding the unused power connec
`tion. Power Supply pins are used as the mode Select.
`Moreover, preferred embodiments only require three pins to
`operate.
`The advantages recited above are important, because they
`can be extended to other parts and other applications.
`Preferred embodiments are easily adaptable to using power
`pins for enabling test mode conditions that the user is not
`allowed access (e.g., disabling a 32 kHz output, etc.).
`Preferred embodiments also provide a three pin power
`Supply System that does not have to use the trickle charger,
`because it is connected to only one of the backup Supply
`pins. Preferred embodiments provide a means for the user to
`Select whether or not write protection during backup is
`enabled. In addition, preferred embodiments could also be
`configured to allow user to Select which backup Supply is
`connected to the trickle charger So that write protection is
`provided for the rechargeable Supply.
`Regarding the trickle charger, depending on the normal
`operating Voltage, any number of diode drops could be
`available to the user by adding more register bits and the
`appropriate decode. Similarly, depending on the current
`requirements, any number of different value resistors could
`be made available to the user by adding more register bits
`and the appropriate decode. In addition, the level of Security
`against accidental enabling of the charger could be improved
`by adding more bits in the control register that allows this
`operation. Since only one code would enable the charger, the
`probability would be reduced as the number of bits gets
`larger. Likewise, the control bits could be of EEPROM type
`that get initialized at power-up So as to configure the power
`Supply function of the integrated circuit that the user desires.
`A capacitor could also be integrated onto the integrated
`circuit to be a redundant back-up Supply So that the user
`could disconnect the rechargeable power Supply from the
`integrated circuit pin and Still have enough back-up power to
`Save memory registers. This is useful in replacing worn-out
`rechargeable batteries.
`Preferred embodiments of the multiple voltage interface
`capability also address problems associated with the two
`Situations described above. In particular, the multiple Volt
`age interface allows the interfacing of integrated circuits that
`are powered by different supply levels, which allows the
`driving circuit to have either a higher Supply level or a lower
`supply level than the driven circuit. If the driver circuit's
`Supply Voltage is used to provide the interface Supply
`voltage, the driver circuit will automatically disable itself
`when the driven circuit's supply voltage fails. If the driven
`circuit's Supply Voltage is used to provide the interface
`Supply Voltage, the output will disable to the interface
`Voltage level if the driver circuit's main Supply Voltage fails.
`No unnecessary current is used because of improper biasing
`of the driven circuit's input stages. Preferred embodiments
`of the multiple interface system also provide full active drive
`CMOS output levels. Output Swings “rail-to-rail” (e.g.,
`extreme to extreme), which eliminates the need for open
`drain output driver circuits with resistive pull-ups. Preferred
`embodiments also provide a separate output power Supply to
`reduce the current on the circuit's main power Supply. This
`is particularly important in battery backed applications
`which require outputs to be driven off the back-up battery
`(i.e., 32 kHz. Square wave output, etc.). Finally, preferred
`embodiments also reduce Switching noise on the main power
`Supply.
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`BRIEF DESCRIPTION OF THE DRAWINGS
`Further features and advantages will become apparent
`from the following and more particular description of the
`various embodiments of the invention, as illustrated in the
`accompanying drawings, wherein:
`FIG. 1 is a block diagram of the combined programmable
`power Supply System (e.g., trickle charger) and write pro
`tection system 110;
`FIG. 2A is a Schematic implementing multiple power
`control block 20 (e.g., trickle charger) of the overall block
`diagram of the combined programmable power Supply (e.g.,
`trickle charger) and write protection system 110 that is
`shown in FIG. 1;
`FIG. 2B is a Schematic implementing power Supply
`control register block 30 (e.g., trickle charge register) of the
`overall block diagram of the combined programmable power
`supply and write protection system 110 that is shown in FIG.
`1;
`FIGS. 2C and 2D are schematics implementing latchprefo
`blocks 50 and latchpref1 blocks 60 respectively of the
`schematic of power supply control register block 30 shown
`in FIG. 2B;
`FIG. 2E is a schematic of power-on reset circuitry 331,
`which initializes power supply control register block 30 in
`FIG. 1;
`FIG. 3A is a Schematic implementing power Switch and
`write protect block 43 of the overall block diagram of the
`combined programmable power Supply and write protection
`system 110 that is shown in FIG. 1 and a block diagram of
`newpf or powerfail module 140 (in FIG. 5A), which
`Switches the internal Voltage Supply between the primary
`and back-up Supply Voltage levels;
`FIG. 3B is a schematic implementing comparator 42 of
`power Switch and write protect block 43 shown in FIG. 3A;
`FIG. 3C is a schematic implementing RRef block 70 of
`power Switch and write protect block 43 shown in FIG. 3A;
`FIG. 3D is a schematic implementing RDiv block 80 of
`power Switch and write protect block 43 shown in FIG. 3A;
`FIGS. 4A and 4B are examples of preferred embodiments
`of the preferred System application of the above circuitry
`showing the preferred pin assignments,
`FIG. 5A is a block diagram of the preferred system
`application referenced in FIGS. 4A and 4B;
`FIG. 5B is a conceptual block diagram of the preferred
`system application referenced in FIGS. 4A and 4B;
`FIGS. 6A, 6B, and 6C show different configurations of
`preferred architecture shown in FIGS. 5A and 5B and
`packaged in packages shown in FIGS. 4A and 4B, which are
`backup Supply and is a non-rechargeable Supply (with need
`to protect memory data); backup Supply is either recharge
`able or non-rechargeable (without need to protect data); and
`low power Single Supply;
`FIG. 7 is a block diagram of shiftblock module 150 (in
`FIG. 5A), which shifts in serial I/O data for internal circuit
`uSe,
`FIG. 8 is a block diagram of outbuf module 100 (in FIG.
`7), which drives the external serial data pin;
`FIG. 9 is a block diagram of pf-outbuf module 200 (in
`FIG. 3A), which drives the external pf pin;
`FIG. 10 is a block diagram of lvlshift module 300 (in
`FIGS. 8 & 9), which translates between two different voltage
`Supply levels;
`FIG. 11 is an address map of memory found in a preferred
`implementation of the circuitry described above in reference
`to the general architecture shown in FIG. 5A;
`
`Petitioner Intel Corp., Ex. 1045
`IPR2023-00783
`
`

`

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`7
`FIG. 12 is map of rtc registers found in a preferred
`implementation of the circuitry described above in reference
`to the general architecture shown in FIG. 5A;
`FIG. 13 is a timing diagram highlighting the operation of
`a Serial clock as a function of microcontroller clock polarity
`(CPOL) of the preferred implementation of the circuitry
`described above in reference to the general architecture
`shown in FIG. 5A;
`FIG. 14 is timing diagram highlighting the operation of a
`SPI Single Byte Write of the preferred implementation of the
`circuitry described above in reference to the general archi
`tecture shown in FIG. 5A;
`FIG