DIGITAL ELECTRONICS
`538 Chapter 8
`
`inputs
`
`inputs
`
`outputs
`
`outputs
`
`Figure 8.83
`
`PLD
`
`discrete logic (usual case)
`
`standard-function MSI logic types. In
`fact, just two of the newer GALS (generic
`array logic) mimic a whole set of PALS, by
`making their internal architecture (as well
`as the logic connections) programmable.
`In particular, the 20-pin GAL16V8 and 24-
`pin GAL20V8 can each mimic 21 standard
`PALS. What's more, they can be pro-
`grammed as mongrel in-between PALs
`(e.g., an odd number of registers).
`
`PAL loose ends
`
`I/O pins. Three-state output pins that
`are internally wired as inputs to the AND
`array can be used as inputs. For exam-
`ple, the 16L8 shown in Figure 8.45 has
`16 inputs (each true and complemented)
`to the AND array; 10 of these are ded-
`icated as input pins, and 6 are fed back
`from three-state outputs. The latter can
`be converted to "permanent" inputs by
`disabling the corresponding output (con-
`nect a true/complement pair to its AND
`control); alternatively, those outputs can
`operate bidirectionally, by enabling the
`three-state driver according to some logic
`variables.
`
`"Super-PALs." As we remarked earlier,
`more flexible programmable logic has fol-
`lowed the original PALs. Notable among
`
`these are erasable CMOS variants from
`Lattice, VTI, Altera, and others.
`For example, the "generic array logic"
`(UAL) from Lattice uses electrically eras-
`able programmable logic, so you can
`reprogram the chip. Even better, the out-
`put structure (called a "macrocell") is itself
`programmable —each output can be either
`registered or combinational, true or com-
`plemented; there's similar programmable
`flexibility for the three-state enable line
`and the feedback line (the latter can come
`before or after the three-state buffer, or
`from the adjacent output); see Figure 8.84.
`The result is that you can mimic any of
`the common 20-pin PALs with the single
`GAL16V8 (and any of the common 24-pin
`PALs with the GAL20V8). This kind of
`flexibility helps keep your inventory within
`manageable bounds.
`Altera has a line of programmable
`CMOS logic that can be erased with UV
`light, just like EPROMs (the IC has a
`quartz window over the chip). They call
`their devices EPLDs, for "erasable pro-
`grammable logic devices." Their smallest
`chip (the EP320) has output macrocells,
`and it mimics all 20-pin PALs, just like
`the GAL16V8. Furthermore, it runs at
`very low power, unlike the original power-
`hungry PALS (see below). Finally, Altera
`makes a number of larger EPLDs, as well
`
`Petitioner Intel Corp., Ex. 1037
`IPR2023-00783
`
`

`

`SEQUENTIAL FUNCTIONS AVAILABLE AS ICs
`8.27 Sequential PALS 539
`
`as programmable microsequencers, etc.
`Cypress and VTI also make erasable
`CMOS programmable logic, complete with
`macrocells.
`Another approach to programmable
`logic is typified by the Xilinx RAM-config-
`urable gate arrays. These impressive chips
`contain huge blocks of configurable logic,
`holding the connection configuration in
`on-chip RAM (volatile memory). This
`memory gets loaded from external mem-
`ory after power has been applied, either by
`downloading from a microprocessor or by
`loading itself from nonvolatile ROM-type
`memory.
`
`Speed and power. The original bipo-
`lar transistor PALS introduced by Mono-
`lithic Memories (and quickly copied by
`National and AMD) consumed consider-
`able current —about 200mA for the 16L8/
`
`16R8 —and had propagation delays of 40ns.
`The subsequent "half-power" bipolar PALs
`were more reasonable, running 90mA with
`speeds of 35ns. However, the fastest PALS
`still burn plenty of power; for example,
`AMD's 16R8D and 16R8-7 have propa-
`gation times of 10 and 7.Sns, respectively,
`but require 180mA (max). The CMOS
`devices are significantly better: Lattice's
`"quarter-power" GALS (GAL20V8-15Q)
`draw 45mA, with a delay time of 15ns, and
`Altera's EP320-1 delivers 25ns delays with
`SmA of current. More important for low-
`powerdesign, the Altera chips (and AMD's
`Z-series PALs) can be put into a "zero-
`power" (10µA typical) standby mode. The
`designers of future programmable logic will
`surely continue this healthy trend toward
`high speed and low power; the days of
`watt-guzzler programmable logic are be-
`hind us!
`
`CLK
`
`OE
`
`Figure 8.84. GAL programmable-output macrocell.
`
`from adjacent
`stage output
`
`Petitioner Intel Corp., Ex. 1037
`IPR2023-00783
`
`

`

`DIGITAL ELECTRONICS
`540 Chapter 8
`
`Glitches. Programmable logic devices
`are wonderful things. But you can occa-
`sionaiiy get into trouble if you forget about
`the possibility of logic races. Figure 8.85
`shows a 2-input multiplexer implemented
`in the obvious way; both the PAL diagram
`and the equivalent circuit are shown. It
`looks fine, the logic is fine, but the circuit
`has a flaw: If both data inputs (A and B)
`are HIGH, and the SELECT line changes
`state, the output may produce a glitch, as
`shown. That is because the internal gate
`delays in S and S' can be unequal, causing
`a transient state in which both AND gates
`have one LOW input. The solution in this
`case (Fig. 8.85B) is to add a redundant
`term, A * B, which you can easily prove to
`yourself will guarantee no output glitches.
`
`EXERCISE 8.33
`Prove that the additional term eliminates all
`possibility of glitches.
`
`AES+BxS'
`
`s
`
`A —
`
`e
`
`EXERCISE 8.34
`What logic terms need to be added to the 4-
`input m ultiplexerexample (Fig. 8.75) to eliminate
`glitches?
`
`s
`
`A
`
`ASS+B•S'
`B +AwB
`
`00 01 11
`
`10
`
`1 j 1 , 0
`
`i~
`
` ~
`o~~ i ;
`
`redundant
`term
`
`Figure 8.85. PAL glitch elimination.
`A. 2-input MUX.
`B. Added product term to eliminate glitch.
`C. Karnaugh map showing necessary redundant
`term.
`
`You can visualize this so-called logic
`hazard in terms of Karnaugh maps: Dia-
`gram the 2-input multiplexer of Fig-
`ure 8.85A as a Karnaugh map (Fig. 8.85C).
`Each group in the map is one product term
`that forms an input to the common OR
`gate. The OR output is true if any of the
`product terms is true; but a transition be-
`tween product groups can produce a glitch
`if the variables of the starting group are
`disasserted before the variables of the final
`group are asserted. The cure (which we
`used earlier) consists of adding redundant
`terms to ensure that any possible transition
`between 1's is included in a single product
`term; in other words, any 1's that lie in ad-
`jacent rows or columns must be enclosed
`by a product group. This prescription can
`be cast into a generalized form that applies
`
`Petitioner Intel Corp., Ex. 1037
`IPR2023-00783
`
`

`

`SEQUENTIAL FUNCTIONS AVAILABLE AS ICs
`8.28 Miscellaneous sequential functions
`
`541
`
`to the Boolean logic expression directly,
`rather than the Karnaugh map. That's use-
`ful for logic with more than four variables,
`for which Karnaugh maps become awk-
`ward.
`The foregoing example is called a static
`glitch, because the output should have
`remained static. There are also dynamic
`glitches, in which an output that should
`make a single transition makes multiple
`transitions instead. It is important to be
`aware of these internal race conditions
`when you use programmable logic. In
`general, design aids like PALASM, ABEL,
`and CUPL do not attempt to identify
`such problems. If anything, they usually
`make things worse, because their logic
`optimizers work zealously to eliminate just
`such redundant terms needed to prevent
`glitches!
`
`8.28 Miscellaneous sequential functions
`
`With the widespread availability of large-
`scale integration (LSI, equivalent to 1000
`gates or more on a chip) and very large
`scale integration (VLSI), you can get weird
`and wonderful gadgets all on one chip.
`This brief section will present just a sam-
`pling.
`
`q First-in/first-out memory
`A first-in/first-out (FIFO) memory is some-
`what akin to a shift register in that data
`entered at the input appear at the output
`in the same order. The important differ-
`ence is that with a shift register the data
`get "pushed along" as additional data are
`entered and clocked, but with a FIFO the
`data "fall through" to the output queue
`with only a small delay. Input and output
`are controlled by separate clocks, and the
`FIFO keeps track of what data have been
`entered and what data have been removed.
`A helpful analogy might be a bowling al-
`ley, in which black and white bowling balls
`
`(bits) are returned to the bowling station:
`The bits are input by the pin-setting ma-
`chine, and the time it takes for a ball to
`roll the length of the alley is the "ripple-
`through delay time" of the FIFO (typically
`1µs-25µs), whereupon the bits are avail-
`able at the output to be removed at the
`whim (asynchronously) of the user.
`FIFOs are useful for buffering asynchro-
`nous data. The classic application is buf-
`fering akeyboard (or other input device,
`such as magnetic tape) to a computer or
`sluggish instrument. By this method, no
`data are lost if the computer isn't ready
`for each word as it is generated, provided
`the FIFO isn't allowed to fill up completely.
`Some typical FIFOs are the 74F433 (TTL,
`64 words of 4 bits each, IOMHz, 4µs
`fall-through) and the IDT7202 (CMOs,
`4096 x 9, 15MHz, zero fall-through).
`A FIFO is unnecessary if the device to
`which you are sending data can always
`get it before the next data arrive. In
`computer language, you must ensure that
`the maximum latency is less than the
`minimum time between data words. Note
`that a FIFO will not help if the data
`recipient is not able, on the average, to
`keep up with the incoming data.
`
`q Rate multiplier
`Rate multipliers are used to generate out-
`put pulses at a frequency that is related
`to the clock frequency by a rational frac-
`tion. For instance, a 3-decade BCD rate
`multiplier allows you to generate output
`frequencies of nnn/ 1000 of the input fre-
`quency, where nnn is a 3-digit number
`specified as three BCD input characters.
`This isn't the same as a modulo-n counter,
`since, for instance, you cannot generate
`an output frequency of 3~ 10 of the input
`frequency with amodulo-n divider. One
`important note: The output pulses gener-
`ated by a rate multiplier are not, in general,
`equally spaced. They coincide with input
`pulses, and therefore they come in funny
`
`Petitioner Intel Corp., Ex. 1037
`IPR2023-00783
`
`

`

`DIGITAL ELECTRONICS
`542 Chapter 8
`
`patterns whose average rate is as above.
`Examples are the '97 (6-bit binary) and
`the ' i 67 (isi;D j rate muitipiiers.
`
`Frequency counters
`
`Intersil has a good selection of integrated
`frequency counters. These include provi-
`sion to gate the input signal for accurately
`known intervals, up to 8 digits of BCD
`counter, display drivers, auto-decimal-
`point and leading-zero blanking, etc. These
`chips generally require very little external
`circuitry.
`
`calculators, smoke detectors, telephone di-
`alers, music synthesizers, rhythm and ac-
`companiment generators, etc. The guts of
`radios, TVs, and compact discs are nearly
`empty these days, thanks to large-scale in-
`tegration. Speech synthesis (and ultimately
`speech recognition) has seen a lot of work
`recently; that's why elevators, Coke ma-
`chines, automobiles, and even kitchen ap-
`pliances now speak to us in those sci-fi
`voices we've all come to love. The de-
`velopment of effective automobile circuits
`(for engine functions, collision-avoidance
`systems, etc.) seems to be the next big
`frontier.
`
`Digital voltmeters
`
`You can get complete digital voltmeters
`(DVMs) on a single chip. They include
`analog digital conversion circuitry and the
`necessary timing, counting, and display
`circuitry. Examples are the low-power 3 2 -
`digit ICL7136 and the 42-digit ICL7129;
`both use LCD 7-segment displays and run
`from a single 9-volt battery.
`
`q Special-purpose circuits
`
`There are nice collections of LSI chips
`for arcane jobs like radio communications
`(e.g., frequency synthesizers), digital signal
`processing (multiplier/accumulators, digi-
`tal filters, correlators, arithmetic units),
`data communications (UARTs, modems,
`network interfaces, data encryption/de-
`cryption ICs, serial format converters), and
`the like. Often these chips are used in
`conjunction with microprocessor-based
`devices, and many of them cannot stand
`alone.
`
`q Consumer chips
`
`The semiconductor industry loves to de-
`velop ICs for use in large-market consumer
`products. You can get single chips to make
`digital (or "analog") watches, clocks, locks,
`
`Microprocessors
`
`The most stunning example of the won-
`ders of LSI is the microprocessor, a com-
`puter on a chip. At one extreme there
`are powerful number crunchers like the
`68020/30 and 80386/486 (32-bit fast pro-
`cessors with prefetch and cache, large ad-
`dress space, virtual memory, and power-
`ful numeric coprocessors) and chips like
`the MicroVAX that emulate existing main-
`frame computers. At the other extreme are
`single-chip processors with various input,
`output, and memory functions included on
`the same chip, for stand-alone use. An ex-
`ample of the latter is the Toshiba TLCS-90
`(Fig. 8.86), a CMOS low-power microcon-
`troller with 6 channels of 8-bit A/D con-
`verter, internal timers, RAM and ROM, 20
`bidirectional digital I/O lines, a serial port,
`and two stepping-motor ports. This latter
`type is intended as a dedicated controller
`in an instrument, rather than as a versatile
`computation device.
`The microprocessor revolution hasn't
`begun to slow, and we have seen a doubling
`of computer power and memory size (now
`1 Mbit per chip, compared with 16kbit/chip
`at the time the previous edition of this
`book was written) each year; at the same
`time, prices have dropped dramatically
`(Fig. 8.87). Along with bigger and better
`
`Petitioner Intel Corp., Ex. 1037
`IPR2023-00783
`
`

`

`w
`
`Inc.)
`Figure 8.86. Single-chip microprocessor with lots of on-chip I/0. (Courtesy of Toshiba America,
`
`TMP90C840P
`
`A 16-A19
`P40 - P43
`
`P37 WAIT
`P36 WR
`P35 RD
`
`AS-A15
`P20 - P27
`
`AO-A7
`PIO-PI7
`
`DO-D7
`?00 - P07
`
`.A
`
`ELK
`
`BESET
`
`t2
`Ci
`
`/SS(GNDI
`/CC
`
`Q
`
`PORT
`
`3
`
`PORT
`
`2
`
`PORT
`
`PORT
`
`~
`
`PORT
`
`OSC
`
`(S KB)
`
`ROM
`
`(256 B)
`
`RAM
`
`CONTROLLER
`
`SYSTEM
`
`INTERNAL ADDRESS BUS
`
`INTERNAL DATA BUS
`
`LATCH
`
`DECODER
`
`INSTRUCTION
`
`~
`
`~
`
`q
`
`R
`
`~
`
`X
`
`Y
`
`CPU
`
`LATCH
`PC
`SP
`IV
`IX
`
`BY
`BX
`
`H C
`D
`E'
`B' C
`A F
`H L
`~ E
`B C
`F
`A
`
`BUFFER
`
`(TIMER 4)
`i681T iCH
`
`EVENT GAUNTER
`
`TIMER
`
`(TIMER 2 3)
`
`8817 2CH
`
`TIMER
`
`IMER 0 I)
`BRIT 2CH
`TIMER
`
`(T
`
`CONTROL PORT I
`STEPPING MOTOR
`
`CONTROL PoRT 0
`STEPPING MOTOR
`
`A D CONVERTER
`
`8817 6CH
`
`ICH
`
`SERIAL I 0
`
`TIMER
`
`WATCH DOG
`
`CONTROLLER
`INTERRUPT
`
`P83 703 704
`P82 INT2 TIS
`P81 INTI 714
`
`P73 M13
`P72 M12
`P71 M
`
`P70 703 M 10
`
`P63 H03
`P62 H02
`P61 H01
`P60 TAI H00
`
`AGND
`VREF
`
`ANO-ANS
`P50-P55
`
`P34 CTS
`P33 TXD
`P32 RTS SCLK TXD
`P31 RXD
`P30 RXD
`
`P80 INTO
`IVMI
`
`Petitioner Intel Corp., Ex. 1037
`IPR2023-00783
`
`

`

`0
`
`OO
`
`0 0
`
`0 m
`U
`p n
`
`E0sc0 NOm NmN NJN
`
`DIGITAL ELECTRONICS
`544 Chapter 8
`
`~~
`
`i
`
`~.
`
`C U a
`
`~
`
`U a OE
`
` 0.0
`
`mE
`
`0.00
`
`Q.~~Q
`
`1970
`
`1975
`1980
`Figure 8.87. The law of Silicon Valley: learning curve.
`
`1985
`
`processors and memory, recent activity in
`very high speed devices and large parallel
`architectures promises more excitement in
`coming years.
`
`SOME TYPICAL DIGITAL CIRCUITS
`
`Thanks to the efforts of the semiconduc-
`tor industry, digital design is wonderfully
`easy and pleasant. It's almost never neces-
`sary to "breadboard" a digital circuit, as so
`often is the case with linear design. Gen-
`erally speaking, the only serious pitfalls in-
`volve timing and noise. We'll have more
`the say about the latter in the next chap-
`ter. This is a good place to illustrate tim-
`ing with some sequential design examples.
`Some of these functions can be performed
`with LSI circuits, but the implementations
`shown are reasonably ef~'icient and illus-
`trate the kind of circuit design being done
`with what's now available.
`
`8.29 Modulo-n counter: a timing
`example
`
`The circuit in Figure 8.88 produces one
`output pulse for every n+l input clock
`
`pulses, where n is the 8-bit number you've
`set on the pair of hexadecimal thumbwheel
`switches. The ' 163s are 4-bit synchronous
`up-counters, with synchronous load (when
`LD' is LOW) via the D inputs. The
`idea is to load the counters with the
`complement of the desired count, then
`count up to FFH, reloading at the next
`clock pulse. Since we've generated the
`preload levels with pullups to +5 (with
`the switch common grounded), those levels
`are negative-true for the displayed switch
`settings; that makes the preload values,
`interpreted as positive-true, equal to the
`1's complement of the switch settings.
`
`EXERCISE 8.35
`Show that the last statement is true, by figuring
`out the positive-true value that will be loaded for
`the switch settings in Figure 8.88.
`
`Circuit operation is entirely straightfor-
`ward. To cascade synchronous counter,
`you tie all clocks together, then tie a "maxi-
`mum-count" output of each counter to an
`enable of the successive counter. For an
`enabled ' 163, the RCO (ripple-clock out-
`put) goes HIGH at maximum count,
`
`Petitioner Intel Corp., Ex. 1037
`IPR2023-00783
`
`

`

`SOME TYPICAL DIGITAL CIRCUITS
`8.29 Modulo-n counter: a timing example
`
`545
`
`hexadecimal thumbwheel switches EECO 1776-...
`
`clock width HIGH
`—► ~-
`f~n
`output /o~~n+ 1)
`
`Figure 8.88. Modulo-n counter.
`are additional time delays associated with
`the cascading connection (IC2 has to know
`that IC1 has reached maximum count in
`time for the next clock pulse), and also the
`load-on-overflow connection. To figure the
`maximum frequency at which the circuit
`is guaranteed to work, we have to add up
`the worst-case delays and make sure there
`is enough setup time remaining. Look at
`Figure 8.89, where we've drawn a timing
`diagram showing the load sequence that
`occurs at maximum count.
`A LOW-to-HIGH change on any Q
`output follows the positive edge of CLK
`by 34ns max. That's interesting, but not
`relevant, because the load sequence uses
`the RCO output; ICl's RCO follows the
`rising edge of the CLK pulse that brings it
`to maximum count by 35ns max, and ICZ's
`RCO follows its input enable (assuming,
`of course, that it is at maximum count)
`by 32ns max. The 74HC04 adds a delay
`of 19ns max to generate LD', which must
`precede CLK (tset„P) by 30ns min. That
`brings us to the next CLK; therefore,
`l~fmaX = (35 -f- 32 -{- 19 + 30)ns, or
`fmaX = 8.6MHz. This is considerably less
`than the maximum guaranteed counting
`frequency of a single 74HC163.
`
`Mc
`
`lock in
`fo
`enabling the second counter via the en-
`abling inputs ENT and ENP. Thus IC1 ad-
`vances at each clock, and IC2 advances at
`the clock after ICl reaches FH. The pair
`thus counts in binary until the state FFH,
`at which point the LD' input is asserted.
`This causes synchronous preload at
`the next clock. In this example we've cho-
`sen counters with synchronous load in
`order to avoid the logic race (and runt
`pulse RCO) that you would get with a
`jam-loaded counter. Unfortunately, this
`makes the counter divide by n+l, rather
`than n.
`
`EXERCISE 8.36
`Explain what would happen ifjam-load counters
`(e.g. ' 191 s) were substituted for the synchronous-
`load '163s. In particular, show how a runt pulse
`would be created. Demonstrate also that the
`foregoing circuit divides by n+1, whereas the
`asynchronous-load would divide byn (if itworked
`at all!).
`
`Timing
`How fast can our modulo-n counter count?
`The 74HC163 specifies a guaranteed fmax
`of 27MHz. However, in our circuit there
`
`Petitioner Intel Corp., Ex. 1037
`IPR2023-00783
`
`

`

`DIGITAL ELECTRONICS
`546 Chapter 8
`
`CLK
`
`MSD
`
`LSD
`
`RCOILSD)
`
`RCOIMSD)
`
`LD'
`
`~1 CLK to Q
`Q2 CLK to RCO
`Q3 ENT to RCO
`Q4 A to Y 1'041
`Q5 LD' setup to CLK
`
`ns, max
`34
`35
`32
`19
`301min)
`
`EXERCISE 8.37
`Show by a similar calculation that a pair of
`synchronously cascaded 74HC163s (without
`load on overflow) have a maximum guaranteed
`counting rate of 15.4MHz.
`
`Of course, if greater speed is needed, you
`can always use faster logic. Doing the same
`calculation for 74F logic (for which the
`maximum count rate of a single 74F163
`is 100MHz), we find fm~ = 29MHz.
`Modulo-n counter devotees should take
`note of the 'HC40103, an 8-bit synchro-
`nous down-counter with parallel load (syn-
`chronous or jam load!), decoded zero-state
`output, and reset-to-maximum input. It
`has a close cousin, the'HC40102, identical
`except organized as 2-digit BCD.
`
`8.30 Multiplexed LED digital display
`This example illustrates the technique of
`display multiplexing: displaying an n-digit
`number by displaying successive digits ra-
`pidly on successive 7-segment LED dis-
`plays (of course, the characters need not
`
`Figure 8.89. Timing diagram and calculation for
`modulo-n counter.
`
`be numbers, and the displays can have a
`different organization than the popular 7-
`segment arrangement). Display multiplex-
`ing is done for reasons of economy and
`simplicity: Displaying each digit continu-
`ously requires separate decoders, drivers,
`and current-limiting resistors for each digit,
`as well as separate connections from each
`register to its corresponding decoder (4
`lines) and from each driver to its corre-
`sponding display (7 wires); it's a mess!
`With multiplexing, there's only one de-
`coder/driver and one set ofcurrent-limiting
`resistors. Furthermore, since LED dis-
`plays come in n-character "sticks" with the
`corresponding segments of all characters
`tied together, the number of interconnec-
`tions is enormously reduced. An 8-digit
`display requires 15 connections when mul-
`tiplexed (7 segment inputs, common to
`all digits, plus one cathode or anode re-
`turn for each digit), rather than the 57
`required for continuous display. An in-
`teresting bonus of multiplexing is that the
`subjective brightness perceived by the eye
`is greater than if all digits were illuminated
`
`Petitioner Intel Corp., Ex. 1037
`IPR2023-00783
`
`

`

`SOME TYPICAL DIGITAL CIRCUITS
`8.30 Multiplexed LED digital display
`
`547
`
`three-state buffers) and decode and dis-
`continuously with the same average bright-
`play it while on the bus (4511 BCD-to-7-
`ness.
`segment decoder/driver).
`Figure 8.90 shows the schematic dia-
`In this circuit a pair of inverters is used
`gram. The digits to be displayed are res-
`to form a classic CMOS oscillator oper-
`ident in register ICl—IC4; they could be
`ating at about 1kHz, driving a 4022 oc-
`counters, if the device happened to be
`a frequency counter, or perhaps a set of tal counter/decoder. As each successive
`output of the counter goes HIGH, it en-
`latches receiving data from a computer, or
`ables one digit onto the bus and simultane-
`possibly the output of an A/D converter,
`ously pulls the corresponding digit's cath-
`etc. In any case, the technique is to assert
`ode LOW via the high-current open-drain
`each digit successively onto an internal 4-
`bit "bus" (in this case with 4503 CMOS 40107 buffers. The 4022 is rigged up to
`
`4-digit LED display "stick"
`
`all 33051
`(5mA avg)
`
`5082-7404
`
`13 a BCD/7-segment
`12 b decoder
`
`7 2
`
`3
`
`4
`
`CATH CATH CATH CATH
`4
`1 2
`3
`
`LT 3 +
`8~ 4 +
`
`~~ d
`
`4511
`1 5 e
`f 5
`14 LE
`g A 8 C D
`
`3
`
`4069
`—~
`
`p 1
`
`40107
`
`40107
`
`..
`
`7 1
`
`2 6
`
`13
`
`12
`
`6
`4069
`
`9
`
`11
`
`6 4069
`
`~—' 4069
`
`6 4069
`
`~2
`
` 3
`3 ~
`4022 4 71
`4
`13
`CE 6 5 5
`0.01µF _
`R 7 ~~
`
`t00k
`
`220k
`
`~ 2 3 4 14
`
`15
`
`6
`
`8 ~~
`
`~~~
`
`'i~i~i~i~~~
`
`~~,~\
`iiii~~~
`
`~~~~~
`iiii~ ~
`~~m
`
`~ i
`
`71 s
`
`~ MSB
`
`ICS
`
`R
`
`~
`
`R
`
`IC z
`
`MSB
`
`MSB
`> >
`
`MSB
`
`R I~3 R
`
`ICQ
`
`I
`I
`I
`MSD I
`I
`I
`I
`Figure 8.90. Four-digit multiplexed display. Numbers outside symbols are IC pin numbers.
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I LSD
`
`Petitioner Intel Corp., Ex. 1037
`IPR2023-00783
`
`

`

`DIGITAL ELECTRONICS
`548 Chapter 8
`
`cycle through the states 0-3 by resetting
`when the count reaches 4. Display multi-
`plexing will work with greater numbers of
`digits, and it is universally used in instru-
`ments with multidigit LED displays. Try
`waving a calculator around in front of your
`eyes —you get numeric alphabet soup!
`Many LSI display-oriented chips, such
`as counters, timers, and watches, include
`on-chip display multiplexing (and even
`driver) circuitry. In addition, you can
`get LSI display controller chips (e.g., the
`74C911 and 74C912) for handling the kind
`of job done earlier with MSI circuits.
`
`q 8.31 Sidereal telescope drive
`
`The circuit in Figure 8.91 was designed to
`drive Harvard's 61-inch optical telescope.
`We needed a 60Hz power source for the
`equatorial drive motor (1 revolution/day),
`accurately settable to any frequency near
`60Hz (SSHz to 65Hz, say). You wouldn't
`want exactly 60Hz, for several reasons:
`(a) stars move at the sidereal rate, not the
`solar rate, so you would want 60.1643Hz,
`approximately; (b) starlight gets bent, trav-
`eling obliquely through the atmosphere;
`this "refraction" depends on zenith angle,
`so the apparent motion is at a slightly dif-
`ferent rate; (c) sometimes you want to look
`at the moon, planets, or comets, which
`have different rates. The solution here was
`to use a 5-digit rate multiplier to generate
`output pulses at a rate f;nn/ 105, where n
`is a 5-digit number set by front-panel BCD
`thumbwheel switches.
`The output is then near 600kHz, since
`f;n is an accurate 1 MHz generated by a
`stable crystal oscillator. The output of
`the rate multiplier is divided by 104 by
`four decade counters, with the last counter
`arranged as a divide-by-5 followed by a
`divide-by-2 for symmetrical square waves
`at 60Hz. The output is clamped by a zener
`for stable square-wave amplitude and fil-
`tered by a 6-pole Butterworth low-pass
`
`filter (fo = 90Hz) to generate a good sine
`wave (you can think of the filter as strip-
`ping away the higher Fourier components,
`or "overtones," of the square wave). Then
`1 15 volts ac is generated by the "over-
`compensated" amplifier illustrated in Sec-
`tion 4.35. The output of the Butterworth
`looks "perfect" on a scope, as it should,
`since in this case a 6-pole Butterworth re-
`duces the largest overtone to 1.5% of its
`unfiltered amplitude; this means that the
`distortion is more than 35dB down. Note
`that this technique of sine-wave generation
`is convenient only if the input frequency is
`confined to a narrow range.
`The f 10% guiding inputs alter the
`synthesized output frequency 10% by
`changing the third divider to divide-by-9
`or divide-by-11. That stage is a modulo-n
`divider constructed along the lines of Fig-
`ure 8.88.
`
`q 8.32 An n-pulse generator
`
`The n-pulse generator is a useful little test
`instrument. It generates a burst of n out-
`put pulses following an input trigger sig-
`nal (or you can push a button), with a set
`of selectable pulse repetition rates. Fig-
`ure 8.92 shows the circuit. The'HC40102s
`are high-speed CMOS 2-decade down-
`counters, clocked continuously by a se-
`lected power-of-10 subdivision of the fixed
`IOMHz crystal oscillator, but disabled by
`having both APE (asynchronous preset en-
`able) asserted and CI (carry in) disasserted.
`When a trigger pulse comes along (note
`the use of 'HCT logic at this input, for
`compatibility with bipolar TTL), flip-flop
`1 enables the counter, and flip-flop 2 syn-
`chronizes counting following the next ris-
`ing edge of the clock. Pulses are passed
`by NAND gate 3 until the counter reaches
`zero, at which time both flip-flops are re-
`set; this parallel-loads the counter to n
`from the BCD switches, disables count-
`ing, and readies the circuit for another
`trigger. Note that the use of pulldown
`
`Petitioner Intel Corp., Ex. 1037
`IPR2023-00783
`
`

`

`—
`
`~SD)
`
`BCD
`
`—
`
`switch
`BCD
`
`—
`
`switch
`BCD
`
`+5
`
`+5
`
`+5
`
`NC
`
`+5
`
`C~ A B C DSs
`
`Ea
`
`STR '167
`
`E;,, ~K ZU/C
`
`+5
`
`A 8 C DS9
`
`CL
`
`STR '167
`Eo
`E~~ CK ZU/C
`
`A 8 C DS9
`
`CL
`
`Eo
`
`STR '167
`
`+5
`
`E;,, ~K zU/C
`
`+5
`
`5
`
`Ci
`
`CZ .
`
`A
`
`Ro
`
`390
`
`2
`
`D
`
`C~
`Cz
`
`A
`
`Ro
`
`2'390
`
`D
`
`2V rms
`
`10051
`
`sine out
`60 ± 5Hz
`
`10%
`0.01
`
`~0°~ ~
`0.01
`
`10%
`0.01
`
`10% =
`0.01
`
`LF422
`
`~
`
`z
`+
`
`180k 5% 7gOk 5%
`
`LF422
`
`~
`
`2
`
`+
`
`180k 5% 180k 5%
`
`LF442
`
`~
`
`15k
`
`10k
`
`5.6k
`
`10 k
`
`6.8k
`
`~c
`~ Figure 8.91. Precision 60Hz ac signal source.Output frequency =x~.xxx; e.g., to generate sidereal
`
`rate, set switches to 60165.
`
`—
`
`y~itch
`gCD
`
`are 3.3k
`resistors
`all pull-up
`
`/
`
`—
`
`(MSD)
`switch*
`BCD
`
`is permissible
`only "5" or "6"
`
`et detent so
`
`'S
`
`input
`1 MHz
`
`1k
`
`1N914 —
`
`A 8 C D S9
`
`CL
`
`'167 Eo
`E;,,~K Z U/C
`
`STR
`
`9
`
`+5
`
`+5
`
`A 8 C D S9
`
`CL
`
`Eo
`
`STR '167
`
`2N3563
`
`+5
`
`E.,, CK z U/C
`
`4'00
`
`+5
`
`68052
`
`nnti +
`3.3k
`
`H I
`
`LO
`
`±10% guiding:
`
`3.3k
`
`DA DB D~ Do
`
`~
`
`'191
`
`Rg Ra C~
`
`CZ
`
`"9~
`
`M/M L Diu EN RC
`
`D A
`
`+
`
`J L
`
`4'00
`
`4"00
`
`= 10%
`0.07
`
`10%
`0.01
`
`l 00k
`
`~ k
`
`LM3296
`
`6
`
`~ ~ ~ g
`
`2
`
`+
`
`180k 5% 180k 5%
`
`1µF
`
`2.2k
`
`100k
`
`1 k
`
`+15
`
`Petitioner Intel Corp., Ex. 1037
`IPR2023-00783
`
`

`

`1kHz
`
`o w
`> n
`N r
`t p
`
`O J
`
`• +
`o
`aM ~
`
`+ p
`
`DIGITAL ELECTRONICS
`550 Chapter 8
`
`manna
`trigger
`(mOmi
`contac
`C&KF
`
`Figure 8.92. n-pulse generator.
`
`;aeon
`LTC1045
`
`Petitioner Intel Corp., Ex. 1037
`IPR2023-00783
`
`

`

`LOGIC PATHOLOGY
`8.33 do problems
`
`551
`
`resistors in this circuit means that true
`(rather than complemented) BCD switches
`must be used. Note also that the manual
`trigger input must be debounced, since it
`clocks aflip-flop. That is not necessary for
`the free-run/n-pulse switch, which simply
`enables a continuous stream of output
`pulses.
`The output stage delivers two pairs of
`true/complement signals. The paralleled
`'HC04 inverters give normal +5 volt logic
`swings, saturating cleanly at the rails be-
`cause we're using CMOS. We paralleled
`them to increase drive capability; the cir-
`cuit as drawn can drive at least f l OmA
`with logic levels within 0.3 volt of the rails.
`If you need more output current, you can
`replace them with 'AC04s, a paralleled pair
`of which will give you f50mA with logic
`levels within 0.3 volt of the rails. We
`added the boxed driver pair so that you
`can drive logic that runs on voltages other
`than +5 volts. For example, low-power de-
`sign often uses 4000B or 74C series CMOS
`running directly from 9 volt batteries (it's
`rated for 3V to 15V operation); 'HC logic
`accepts 2 to 6 volt supply voltage; and
`there have been suggestions recently that
`'AC-style CMOS be operated at +3.3 volts
`(JEDEC Standard No. 8). The 40109,
`14504, and LTC1045 are all level shifters,
`chips with active pullups to a second sup-
`ply terminal connected (in this case) to the
`driven circuit's VDD line, which can be
`higher or lower than the pulse generator's
`-F-S volt supply. In that way you get clean
`CMOS output levels at the right voltage for
`the circuit under test.
`
`LOGIC PATHOLOGY
`
`There are interesting, and sometimes
`amusing, pitfalls awaiting the unsuspect-
`ing digital logician. Some of these, such
`as logic races and lockup conditions, can
`occur regardless of the logic family in use.
`Others (e.g., "SCR latchup" in CMOS
`chips) are "genetic abnormalities" of one
`
`logic family or another. In the following
`sections we have collected our bad experi-
`ences in the hope that such anecdotes can
`help others avoid such problems.
`
`8.33 do problems
`
`Lockup
`It is easy to fall into the trap of designing
`a circuit with a lockup state. Suppose you
`have some gadget with a number of flip-
`flops, all going through their proper states.
`Everything seems to work fine. Then one
`day it just stops dead. The only way you
`can get it to work is to turn the power off
`and back on again. The problem is that
`there is a lockup state (an excluded state
`of the system that you can't escape from),
`and you got into it because of some power-
`line transient that sent the system into the
`forbidden state. It is very important to
`look for such states when you design the
`circuit and rig up logic so that the circuit
`recovers automatically. At a minimum,
`things should be arranged so that a RE-
`SET signal (generated manually, at start-
`up, etc.) brings the system to a good state.
`This may not require any additional com-
`ponents (e.g., Exercise 8.24).
`
`Start-up clear
`A related issue is the state of the system at
`start-up. It is always a good idea to provide
`some sort of RESET signal at start-up.
`Otherwise the system may do weird things
`when first turned on. Figure 8.93 shows
`a suitable circuit. The series resistor is
`necessary with CMOS to prevent damage
`when power is removed from the circuit,
`since otherwise the electrolytic capacitor
`will try to power the system via the CMOS
`input-gate protection diode. A Schmitt
`trigger (4093, '14) may be a good idea, to
`make the RESET signal switch off cleanly.
`The hysteresis symbol shown in the figure
`indicates an inverter with Schmitt trigger
`input, e.g., the TTL 74LS 14 (hex inverter)
`or CMOS 40106 or 74HC 14.
`
`Petitioner Intel Corp., Ex. 1037
`IPR2023-00783
`
`

`

`DIGITAL ELECTRONICS
`552 Chapter 8
`
`+ vcc
`
`33k
`
`470
`
`omit for bipolar TTL
`
`d
`
`.L 15~F
`'~` zov
`
`1
`Figure 8.93. Power-on clear circuit.
`
`RESET
`
`RESET
`
`8.34 Switching problems
`
`Logic races
`Lots of subtle traps lurk here. The classic
`race was illustrated with the pulse synchro-
`nizer in Section 8.19. Basically, in any sit-
`uation where gates are enabled by signals
`coming from flip-flops (or any clocked de-
`vice), you must be sure that a gate
`doesn't get enabled and then disabled a
`flip-flop delay time later. Likewise, make
`sure that signals appearing at flip-flop in-
`puts aren't delayed with respect to the clock
`(another plus for synchronous systems!).
`In general, delay the clock rather than the
`data. It is surprisingly easy to overlook a
`race condition.
`
`for m