United States Patent (19)
`Patel et al.
`
`11)
`45)
`
`4,327,410
`Apr. 27, 1982
`
`54
`(75)
`
`(73)
`21
`(22)
`51
`(52)
`(58)
`
`56
`
`PROCESSOR AUTO-RECOVERY SYSTEM
`Inventors: Rameshchandra S. Patel, Kettering,
`Ohio; Mark R. Easley, Cupertino,
`Calif.
`Assignee: NCR Corporation, Dayton, Ohio
`Appl. No.: 134,246
`Fed:
`Mar. 26, 1980
`Int. Cl. ........................ G06F 11/00; G06F 9/46;
`G06F 3/OO
`U.S. C. ..................................... 364/200; 365/228
`Field of Search ... 364/200 MS File, 900 MS File;
`371/10, 66; 36.5/226, 228, 229
`References Cited
`U.S. PATENT DOCUMENTS
`3,286,239 11/1966 Thompson et al. ................. 364/200
`3,321,747 5/967 Adamson ..........
`... 364/2OO
`3,801,963 4/974 Chen .........
`... 364/200
`3,810, 16 5/1974 Prohofsky ........................... 36.5/229
`3,859,638 1/1975 Hume, Jr. .....
`... 340/73 R
`3,916,390 10/1975 Chang et al. .
`... 340/173 R
`3,959,778 5/1976 Brette ........
`....... 364/200
`3,980,935 9/1976 Worst .....
`... 340/173 R
`4,075,693 2/1978 Fox et al. ............................ 364/200
`4,096,560 6/1978 Footh ............
`... 365A228
`4,145,761 3/1979 Gunter et al. ....................... 365A227
`
`OTHER PUBLICATIONS
`Rayside et al., "A Minicomputer Power Fail Detection
`System', Chemical Instrumentation, vol. 7, No. 3, pp.
`211-218, 1976.
`Hicks et al., “Instruction Retry Mechanism For a Com
`puter', IBM Tech. Discl. Bull., vol. 17, No. 8, Jan.
`1975, pp. 2239-2242.
`Primary Examiner-Gareth D. Shaw
`Assistant Examiner-Eddie P. Chan
`Attorney, Agent, or Firm-J. T. Cavender; Albert L.
`Sessler, Jr.; Elmer Wargo
`(57)
`ABSTRACT
`A system for preserving data associated with a memory.
`unit having a volatile section and a non-volatile section.
`The system controls the transfer of data between the
`volatile and non-volatile sections of the memory unit
`and also handles successive impending power fail sig
`nals so as to preserve data such as transaction totals, for
`example, and also includes a control means to enable the
`system to return to a processing point at which the first
`of the impending power fail signals occurred, thereby
`avoiding reconstruction of an aborted transaction, for
`example.
`
`3 Claims, 12 Drawing Figures
`
`
`
`MedPORT:
`
`ABAA9
`
`SYNCMOSCA
`
`RESET NA
`
`PFA a
`
`
`
`
`
`
`
`STORE / ERASE
`CONTROL OGC AND
`DISABLE CONTRO CKT
`
`SABE
`CONTRO
`
`98
`
`Petitioner Intel Corp., Ex. 1035
`IPR2023-00783
`
`

`

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`U.S. Patent
`U.S. Patent
`
`Apr. 27, 1982
`
`Sheet 1 of 11
`
`4,327,410
`4,327,410
`
`||
`
`J1
`
`Petitioner Intel Corp., Ex. 1035
`IPR2023-00783
`
`Petitioner Intel Corp., Ex. 1035
`IPR2023-00783
`
`
`
`
`

`

`U.S. Patent Apr. 27, 1982
`
`Sheet 2 of 11
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`4,327,410
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`Petitioner Intel Corp., Ex. 1035
`IPR2023-00783
`
`

`

`U.S. Patent Apr. 27, 1982
`
`Sheet 3 of 11
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`4,327,410
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`Petitioner Intel Corp., Ex. 1035
`IPR2023-00783
`
`

`

`U.S. Patent
`
`Apr. 27, 1982
`
`Sheet 4 of 1]
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`4,327,410
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`Petitioner Intel Corp., Ex. 1035
`IPR2023-00783
`
`Petitioner Intel Corp., Ex. 1035
`IPR2023-00783
`
`
`

`

`U.S. Patent
`
`Apr. 27, 1982 ee ||BHOLS|
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`Petitioner Intel Corp., Ex. 1035
`IPR2023-00783
`
`Petitioner Intel Corp., Ex. 1035
`IPR2023-00783
`
`

`

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`
`
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`
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`U.S. Patent
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`Apr. 27, 1982
`
`Sheet 6 of 11
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`Petitioner Intel Corp., Ex. 1035
`IPR2023-00783
`
`Petitioner Intel Corp., Ex. 1035
`IPR2023-00783
`
`
`

`

`U.S. Patent Apr. 27, 1982
`
`Sheet 7 of 11
`
`4,327,410
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`Petitioner Intel Corp., Ex. 1035
`IPR2023-00783
`
`

`

`U.S. Patent Apr. 27, 1982
`
`Sheet 8 of 11
`
`4,327,410
`
`FG. 7
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`
`Petitioner Intel Corp., Ex. 1035
`IPR2023-00783
`
`

`

`U.S. Patent
`Apr. 27, 1982
`U.S. Patent Apr. 27, 1982
`
`Sheet 9 of 11
`Sheet 9 of 11
`
`4,327,410
`4,327,410
`
`
`
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`
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`
`Petitioner Intel Corp., Ex. 1035
`IPR2023-00783
`
`Petitioner Intel Corp., Ex. 1035
`IPR2023-00783
`
`

`

`U.S. Patent Apr. 27, 1982
`
`Sheet 10 of 11
`
`4,327,410
`
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`Petitioner Intel Corp., Ex. 1035
`IPR2023-00783
`
`

`

`U.S. Patent Apr. 27, 1982
`
`Sheet 11 of 11
`
`4,327,410
`
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`Petitioner Intel Corp., Ex. 1035
`IPR2023-00783
`
`

`

`5
`
`O
`
`30
`
`1
`
`PROCESSOR AUTO-RECOVERY SYSTEM
`
`BACKGROUND OF THE INVENTION
`This invention relates to a system or means for han
`dling the sequencing of data between the volatile and
`non-volatile portions of a memory unit during momen
`tary power fluctuations including successive momen
`tary power fluctuations so as to avoid the loss of trans
`action processing data such as totals and the like.
`In certain financial terminals, for example, transac
`tion processing (TP) data is developed for handling
`customers' accounts. This TP data is stored in memory
`units which are sometimes referred to as Non-Volatile
`15
`Random Access Memory (NVRAMS). These
`NVRAMS contain a first section which acts as a normal
`RAM when the power thereto is on; however, these
`RAMS lose the data when the power thereto is turned
`off. These NVRAMS also contain a second section
`which comprises for example, Electrically Alterable
`20
`Read Only Memory (EAROM) which section is non
`volatile in that data (which is readily written into) is not
`lost therefrom when the power thereto is turned off.
`These NVRAMS are frequently used to store TP data
`25
`such as teller totals, accumulators, transaction counters,
`supervisory codes, certain constants and terminal sign
`in information, which TP data frequently has to be
`updated.
`The financial terminal in which these NVRAMS are
`used generally has a power supply whose A.C. input is
`subjected to fluctuations in voltage, which fluctuations
`may be due to, for example, excessive demands on the
`associated A.C. source in the building in which the
`terminal is housed. The excessive demands (heavy
`loads) may be due to the operation of elevators, air
`35
`conditioning units, and the like in the building, for ex
`ample.
`One of the problems with such terminals is that such
`a momentary fluctuation in the AC source is sensed by
`the terminal as an impending power failure causing the
`terminal to be placed in a complete "reset" in order to
`insure that only valid data will be retained in the nem
`ory unit. This resetting of the terminal could result in a
`considerable down time for the reconstruction of an
`aborted transaction via an audit trail, a restart of pro
`45
`gram loading operations and/or an establishment of
`disrupted communication lines.
`SUMMARY OF THE INVENTION
`In a preferred embodiment of this invention, the sys
`50
`ten comprises a memory unit having first and second
`sections for storing data, with the first section being
`volatile and the second section being non-volatile;
`means for processing data being operatively coupled to
`the memory unit for handling data; and means for con
`55
`trolling the transfer of data between the first and second
`sections, whereby the controlling means is adapted to
`transfer the data from the second section to the first
`section upon the occurrence of a first signal, to clear the
`data from the second section upon the occurrence of a
`60
`second signal to provide a cleared second section, and
`also to transfer the data from the first section to the
`cleared second section upon the occurrence of a third
`signal which indicates at least an impending power
`failure to the memory unit; the controlling means also
`65
`includes means for handling successive third signals so
`as to enable the system to preserve data which was
`stored in the first section and to enable the processing
`
`4,327,410
`2
`means to return to a point in processing data at which
`point the first one of the successive third signals oc
`curred without losing any of the TP data referred to
`earlier herein.
`BRIEF DESCRIPTION OF THE DRAWING
`FIGS. 1A and 1B taken together show a terminal,
`such as a financial teller terminal in block form in which
`the automatic recovery system of this invention may be
`used;
`FIG. 2 is a block diagram showing more details of the
`automatic recovery system shown in FIG. 1;
`FIG. 3 is a block diagram showing additional details
`of the automatic recovery system shown in FIG. 2;
`FIG. 4 is a timing diagram showing the relationship
`among various signals associated with a normal se
`quence;
`FIG. 5 is a timing diagram showing the relationship
`among various signals associated with a momentary
`power failure mode of operation;
`FIG. 6 is a schematic diagram showing the details of
`the disable circuit shown in FIG. 3;
`FIG. 7 is a schematic diagram showing the details of
`the control circuit shown in FIG. 3;
`FIG. 8 is a schematic diagram showing a circuit for
`generating the RESETINA signal shown in FIG. 3;
`FIG. 9 is a schematic diagram of the WAROM dis
`able control circuit shown in FIG. 2;
`FIG. 10 is a timing diagram showing the relationship
`among various signals associated with one of the mem
`ory units shown in FIG. 1B; and
`FIG. 11 is a chart showing the relationship of various
`transistors (with regard to being "on" or "off") included
`in different portions of the control logic and disable
`control circuit shown in FIG, 1B.
`DETAILED DESCRIPTION OF THE
`INVENTION
`As stated earlier herein, the data recovery system of
`this invention may be used, for example in a financial
`teller terminal. FIG. 1A shows a portion of a financial
`terminal 20 (hereinafter called terminal) in which the
`data recovery system 22 (FIG. 1B) of this invention
`may be used. The data recovery system 22 (hereinafter
`called system 22) is coupled to the terminal 20 via a
`conventional port 24. Because the terminal 20 may be
`conventional, it is described only generally herein.
`The terminal 20 (FIG. 1A) includes a processor 26
`having the usual reset 28, clock 30, and read/write
`control 32 circuit associated therewith. The terminal 20
`also has a main memory 34 consisting of, for example,
`ultraviolet-light, erasable, Programmable Read Only
`Memories or EPROMS and also utilized Random Ac
`cess Memories 36 (RAMS) as a scratch pad for the
`processor 26. The main memory 34 contains all the
`programs associated with data handling for the proces
`sor 26.
`In the embodiment described, the processor 26 (FIG.
`1A) is an eight bit processor such as an 8085 processor
`which is manufactured by Intel Corp. of California,
`although the principles of this invention may be ex
`tended to other processors.
`The processor 24 (FIG. 1A) has 16 address lines
`associated therewith, with the most significant 8 bits
`(A8-A15) passing through a buffer 38 to a utilization
`system 40 and with the least significant 8 bits (Ab-A7)
`passing through a buffer 42 to the utilization system 40.
`
`Petitioner Intel Corp., Ex. 1035
`IPR2023-00783
`
`

`

`15
`
`4,327,410
`3
`4.
`The bus 44, which is an address and data bus is also
`tion 82A having the lower addresses and with section
`marked AD Bus d-7, is used to transfer either 8 bits of
`82B having the higher addresses.
`data or the least significant 8 bits of the address between
`The memory unit 84 (FIG. 1B) is comprised of the
`the processor 26 and the rest of the terminal 20. Eight
`sections 84A and 84B shown in FIG. 2. The section 84A
`bits of data leaving the terminal 20 pass through the data
`contains Volatile Random Access Memory units and
`buffer 44, and the eight bits of data or the least signifi
`non-volatile EAROM's. The memory section 84B con
`cant 8 bits of an address pass through the buffer 46 to
`tains Word Alterable Read Only Memory units (WA
`the buffered address or data lines BADBdb-BADB7
`ROMS). In the embodiment described, one half of
`which are also marked as 48. When an address is being
`memory section 84A contains volatile RAMS 94 and
`supplied to the buffer 46, a control signal such as ad
`10
`the other half contains non-volatile EAROMS 96.
`dress latch enable (ALE), coming from the processor
`Memory section 84A has the lower addresses and sec
`26, will cause the address (the least significant 8 bits) to
`tion 84B has the higher addresses. As an illustration, the
`be latched into the latch 50. The remaining 8 bits or the
`range of addresses for each of the memory sections 82A,
`most significant 8 bits (A8-A15) are supplied to a buffer
`82B, 84A, and 84B is shown in each of the sections in
`52.
`FIG. 2, with unit 82A having hex addresses of 000H to
`In the embodiment described, 5 bits of the output of
`3FFH and with unit 84B having hex addresses of 2000H
`buffer 52 (FIG. 1A) are fed to a memory decode 54
`to 8FFH. In one embodiment, the memory unit 84 con
`which is used to select the appropriate section in mem
`sists of part #006-1022026 which is manufactured by
`ory 34 to be read, and similarly, the 6 most significant
`NCR Corporation.
`20
`address bits are fed to a memory decode 56 which is
`In general, the WAROMs of memory section 84B
`used to select the appropriate section of the memory 36
`(FIG. 2) are used for storing user programs; these WA
`for reading and writing operations. When data is to be
`ROMs can be altered under program control but are
`read from memory, for example, the data therefrom
`intended primarily for the long-term storage of data.
`passes through a buffer 58 prior to being placed on the
`The RAMs 94 of section 84A are used to store Terminal
`25
`bus 44. The buffers 38, 42, 46, 52, and 58 are conven
`Processor (TP) data which is frequently updated, such
`tional tri-state buffers which are used for effecting data
`data as teller totals, accumulators, transaction counters,
`transfer; three sequentially occurring time frames T1,
`supervisory codes, and terminal sign-in information.
`T2, and T3 (not shown) from the processor 26 are uti
`The RAMs 94 in section 84A have the advantage of
`lized to conventionally transfer data through these buff
`acting as a normal RAM while the operating power
`ers in either direction.
`from power supply 99 (FIG. 1A) is on, and when there
`The bus 48 (FIG. 1A) communicates with a plurality
`is an impending power failure (indicated by a PFAIL/
`of input/output devices such as a display or a cathode
`signal from the power supply 99), the data which is in
`ray tube (CRT) 60 and a printer 62 via conventional
`the volatile RAMs 94 is transferred to the non-volatile
`ports such as 64 and 66, respectively. The CRT 60 has
`EAROMS 96. The non-volatile EAROMs 96 in section
`the usual CRT control 68 and character generator and
`84A are used for storing data from the RAMs 94 while
`RAM 70 associated therewith as shown in FIG. 1A.
`the operating power is off. A series of operations (to be
`Data from bus 44 or the RAM 36 is supplied to the
`later described herein) allows the data to be block trans
`character generator and RAM 70 via the port 72 and
`ferred from the RAMs 94 to the EAROMs 96 and vice
`bus 74 which is also marked as MDdb-7. The terminal 20
`versa as required.
`also has a keyboard 76 (FIG. 1B) for entering data
`The normal sequence of operations for transferring
`thereon, and the keyboard 76 communicates with the
`data between the RAMs 94 and the EAROMs 96 of
`bus 44 via a conventional port 78. The read/write con
`memory section 84A (FIG. 2) will be discussed begin
`trol 32 (FIG. 1A) generates the usual control outputs
`ning with the operating power being off and with data
`80, shown only generally, for conventionally control
`being stored in the EAROMs 96. When operating
`45
`ling the flow of data in the terminal 20.
`power is turned on, a Restore operation is performed
`Earlier herein, it was stated that the terminal 20 (FIG.
`whereby data from the EAROMs 96 is transferred to
`1A) is coupled to the data recovery system 22 (FIG. 1B)
`the RAMs 94. After the data is so transferred, an Erase
`via the port 24. In general terms, the system 22 includes
`operation is performed on the EAROMs 96 so as to
`a first memory unit 82 having some input/output func
`enable them to receive data from the RAMs 94 on the
`50
`tions associated therewith, a second memory unit 84, a
`next power down. When a power fail signal (PFAIL/)
`processor 86, a control logic and disable control circuit
`is detected (indicating that valuable data in the RAMs
`88 (hereinafter referred to as control circuit 88), and a
`94 may be lost) a Store operation is performed whereby
`bus 89 intercoupling the first and second memories (82
`data from the RAMs 94 is transferred to the EAROMs
`and 84) with the processor 86.
`96. Some restrictions apply to the sequencing of the
`The system 22 (FIG. 1B) is shown in more detail in
`Restore, Erase, and Store operations. For example,
`FIG. 2. The port 24 essentially performs a handshaking
`neither the Restore nor the Store operations can be
`function, and it can be programmed to effect the type of
`interrupted before being completed, otherwise invalid
`data exchange which is desired; one such programmed
`data could result; however, before a discussion of these
`peripheral interface circuit which may be used for port
`restrictions, it appears appropriate to further discuss the
`60
`24 is the integrated circuit (IC) #8255 which is manu
`elements included in the recovery system 22.
`factured by Intel Corporation.
`The control circuit 88 (FIG. 2) is used to control the
`The memory unit 82 (FIG. 2) is comprised of the
`sequencing of the transfer of data between the RAMs 94
`sections 82A and 82B, with section 82A having an in
`and EAROMs 96 and also is used to prevent invalid
`put/output (I/O) port 90 associated therewith, and with
`situations from arising, A WAROM disable control
`65
`section 82B having an I/O port 92 associated therewith.
`circuit 98 coupled between the control circuit 88 and
`The sections 82A and 82B are comprised of Electrically
`the WAROMs 84B is used to disable the WAROMs
`Alterable Read Only Memories (EAROMs), with sec
`84B. The following List #1 contains the various control
`
`30
`
`35
`
`55
`
`Petitioner Intel Corp., Ex. 1035
`IPR2023-00783
`
`

`

`Signal
`RESETNA
`
`PFAIL
`
`NMINT
`
`GPINT
`
`MEDRESETA
`
`SYNC
`
`MDMYRST
`
`PWRUP
`
`O
`
`15
`
`25
`
`30
`
`35
`
`45
`
`50
`
`List #1
`Definition
`This is a master system reset
`which is generated on "power up'
`or is generated manually.
`This is an impending power fail
`detection signal generated by
`the associated power supply 99.
`This is a non-maskable interrupt
`request line which is triggered
`by the control circuit 88 when a
`PFAILA signal is detected; it
`initiates the Store routinese
`quence.
`This is a general purpose inter
`rupt request line which is issued
`by the processor 26 through port
`24 to alert the processor 86
`that a command sequence is being
`initiated by the processor 26.
`This is a reset line to the
`processor 86 which reset line is
`under software control of the
`processor 26.
`This is a system bus timing
`synchronization pulse which is
`generated by the processor 86.
`This is a signal which is under
`control of software associated
`with the processor 26 and it
`allows a dummy SYNC pulse to be
`generated for internally re
`setting the memory sections 82A,
`82B, 84A and 84B.
`This is an input to the port 92
`in system 22 from the terminal
`20 which signal is set only on
`"power up"; this allows the
`firmware in system 22 to distin
`guish between a power up signal
`and a manual reset.
`This is an output from the con
`trol circuit 88 which holds the
`memory section 84A. in a disabled
`state during critical power up,
`power down and reset periods.
`This is an ERASEASTOREARESTORE
`signal from the control circuit
`88 for controlling the Store,
`Restore, Erase, and Disabie
`function of the memory section
`84A.
`This is a disable line from the
`WAROM disable control circuit 98
`to disable the memory section
`84B during critical power up,
`power down, and reset periods.
`
`4,327,410
`5
`6
`signals used in the system 22 (FIG, 2) along with their
`The line 120 (FIG. 4) represents the normal power-up
`for the system 22 whereby a -5 volt line is raised from
`definitions,
`zero volts to +5 volts at time A. The signals remaining
`in FIG. 4 will now be discussed as they relate to time A.
`With regard to the signal MEDRESET/ shown on
`line 122 in FIG. 4, the main function of this signal is to
`reset the processor 86 (FIG. 2) and the ports 90 and 92
`of the EAROMs 82A and 82B, respectively. At time A,
`the MEDRESET/ signal is at zero volts, and at power
`up, all eight lines (PA-PA7) of port 92-O (FIG. 3) are
`initialized as an output port and all eight lines
`(PB-PB7) of port 90-I are initialized as an input port.
`During and after removal of the MEDRESET/ signal
`from the EAROMs 82A and 82B, the output port 92-O
`is initialized at --5 volts in the embodiment described.
`With regard to the signal PFAIL/ shown on line 124
`in FIG. 4, a function of this signal is that it provides an
`impending power failure detection before the voltages
`from the power supply 99 for the systems 20 and 22
`actually go out of tolerance or are at zero volts. In the
`embodiment described, the pre-power fail detection
`time, i.e., the time from the PFAIL/ signal switching
`from a high level to a low level to the voltages from the
`power supply 99 actually going out of tolerance is 20
`milliseconds; this is referred to as a store time. In a
`normal operating mode, the line 124 is held at a low
`level from time A through time C for 35 milliseconds as
`a minimum after the power supplies have stabilized.
`The clear up signal (CLRUP) is generated at terminal
`PAs of port 92-O (FIG. 3) of the EAROM 82B and is
`shown as being at a high level or --5 volts at time A on
`line 126 in FIG. 4. The CLRUP signal disables the
`flip-flop 110 (FIG. 3) as long as this signal is at a high
`level. When the CLRUP signal on line 126 changes to a
`low level, it causes the Q/ output of flip-flop 108 (FIG.
`3) to rise to a high level and it enables the flip-flop. 110.
`Only when the CLRUP signal to flip-flop 108 is at a low
`level and the PFAIL/ signal (line 124 in FIG. 4) to
`NAND gate 104 switches from a high level to a low
`level (as shown at point 128 on line 124) will the Q
`output offlip-flop 110 change to a high level (represent
`ing the NMINT signal) as shown at point 130 on line
`132 of FIG. 4.
`The power up signal (PWRUP) is generated at the Q
`output of flip-flop 108 (FIG. 3) and is shown as being at
`a high level at time A on line 134 of FIG. 4. When the
`PFAIL/ signal to inverter 100 (FIG. 3) is at a low level
`and the CLRUP signal to NAND gate 102 is at a high
`level, the flip flop 108 switches the PWRUP signal (at
`the Q output of flip-flop 108) to a high level. A low
`level for the CLRUP signal at the clear (CLR) input to
`flip-flop 108 resets it, causing the Q output thereof or
`the PWRUP output to fall to a low level, thereby indi
`cating to the processor 86 (FIG. 2) via the terminal PB2
`of the input port 92 of the EAROM 82B that this was a
`true power-up or a manual reset. The PWRUP signal
`falling to a low level is shown at point 136 of line 134.
`A disable memory signal (DSBLMEM) is generated
`at terminal PA6 of the output port 92-O of the EAROM
`82B as shown in FIG. 3, with the line 138 in FIG. 4
`being used for this signal which is at a high level at time
`A during the normal power-up routine. The purpose of
`the DSBLMEM signal is to disable the circuit 114
`(FIG. 3) so that the memory section 84A is not acciden
`tally erased or written into with regard to the non
`volatile portion (EAROM 96) of this section 84A.
`A non-maskable interrupt signal (NMINT) is gener
`ated at the Q output of flip-flop 10 as shown in FIG. 3,
`
`ES
`
`WARM 30
`
`The system 22 shown in FIG. 2 is shown in more
`detail in FIG. 3 and the associated timing diagrams for
`a normal operating sequence are shown in FIG. 4. The
`various letters A-M along the base of FIG. 4 represent
`55
`various times in a typical step-by-step sequence.
`A portion of the system 22 is shown in FIG. 3 and it
`includes the I/O port 92 which is part of the EAROM
`82B. The system 22 also includes the inverter 100,
`NAND gates 102 and 104, AND gate 106, and "D'-
`type, flip-flops 108 and 110. Also includes in the circuit
`22 are an inverter 112, a disable circuit 114, an AND
`gate 116, and a control circuit 118.
`The I/O port 92 associated with the EAROM 82B
`(FIG. 3) is shown as having its input and output func
`65
`tions separated as input and output ports 92-I and 92-O,
`respectively. The normal operating sequence will be
`discussed with regard to FIGS. 3 and 4.
`
`Petitioner Intel Corp., Ex. 1035
`IPR2023-00783
`
`

`

`O
`
`5
`
`5
`
`4,327,410
`8
`7
`flip-flop 108 (FIG. 3) due to the fact that the Q output
`with the line 132 (FIG. 4) being used for this signal
`of flip flop 108 is at a high level and the Q/ thereof is at
`which is initially at a low level at time A. When an
`impending power failure occurs, the signal PFAIL/ on
`a low level, indicating that the transaction program is in
`line 124 in FIG. 4 falls from a high level to a low level
`a RESTORE operation. The minimum time between
`at point 128, and this causes the Q output of flip-flop 110
`time A and C in the embodiment described is 35 milli
`to change from a low to a high as shown at point 130 on
`seconds.
`line 132. The Q output of flip-flop 110 (producing the
`At time D in FIG. 4, the RESTORE operation men
`tioned in the previous paragraph is completed and the
`NMINT signal) is connected to the highest-priority
`interrupt input pin of the processor 86 which services
`firmware, hereinafter called the transaction program,
`the interrupt to cause the STORE operation to be per
`associated with the processor 86 (FIG. 2) switches the
`formed. The STORE operation is shown occurring
`clear up (CLRUP) signal from a high to a low level via
`terminal PA5 of the output port 92-O of the memory
`between times I and J in FIG. 4, and it should be re
`called that the STORE operation transfers data from
`section 82B (FIG. 3) as shown at point 150 in FIG. 4.
`The CLRUP signal, switching to a low (as at point 150
`the volatile RAMS 94 to the non-volatile EAROMS 96
`in FIG. 4) resets the flip-flop 108 in FIG. 3 which in
`of section 84A.
`The disable memory signal (DSBTMR), shown as
`turn allows the PWRFAIL signal (in the case of a mo
`mentary power failure) to pass through the gate 104,
`line 142 in FIG. 4, follows the PFAIL/ signal and re
`setting flip flop 110. The time required for the RE
`mains high from point 144 (after time C) until the dis
`able memory (DSBLMEM) signal changes to a low
`STORE operation to be completed is between 50 and
`level at point 140 and time K. The DSBLMEM signal
`1000 microseconds (between times C and D). At the end
`of the RESTORE operation, the transaction program
`comes from the terminal PA6 of the output port 92-O of
`associated with the processor 86 (FIG. 2) enters the
`the section 82B (FIG. 3) and is fed into the circuit 114
`(FIG. 3). The output of circuit 114 is the DSBTMR
`ERASE routine during which the non-volatile (EA
`signal which is fed into the AND gate 116 whose output
`ROMs 96) portion of the memory section 84A is erased.
`(the DSBLNVRM signal) is fed into the circuit 118 to
`The ERASE operation continues between times D and
`25
`disable this circuit 118 which in turn disables the ERA
`E of FIG. 4.
`SE/STORE (E/S) signals from the circuit 118 associ
`At time E, the ERASE operation shown in FIG. 4 is
`completed, and the transaction program associated with
`ated with the memory section 84A (FIG. 3), and the
`the processor 86 enters the normal mode of operation in
`DSBNVRM signal is also fed into the WAROM disable
`control circuit 98 (FIG. 2) to disable the memory sec
`which any of the usual transactions associated with the
`financial terminal 20 may be run. The duration of the
`tion 84B.
`Having described what occurs at time A (FIG. 4)
`ERASE operation between the times D and E in FIG.
`with regard to normal sequence timing in the system 22
`4 is from 100 to 200 milliseconds,
`(FIG. 2), the discussion will now proceed to an explana
`The time between times F and G in FIG. 4 indicates
`tion of what occurs during the times B through M
`that the processors 26 and 28 are in reset. When a manu
`35
`ally-operated shunt 192 (FIG. 8) is placed in the opera
`shown in FIG. 4.
`At time B in FIG. 4, only the MEDRESET/ signal
`tive position, the MEDRESET/ signal switches to a
`(coming from the system 20 in FIGS. 1A and 1B
`low level as shown at point 152 and the CLRUP signal
`switches from a low signal to a high level as shown at
`switches to a high level as shown at point 154; this resets
`the processor 86 and causes the transaction program
`point 146 on line 122 in FIG. 4. The MEDRESET
`/signal is fed into the ports 90 and 92 of the memory
`associated with the processor 86 to return to restart
`sections 82A and 82B (FIG. 2) and is also fed into the
`execution at address zero. Notice that the time between
`processor 86. In the embodiment described, the mini
`times F and G is located in the normal mode of opera
`mum time and the maximum time between the times A
`tlOn.
`and B are 10 and 30 milliseconds, respectively. At time
`At time G in FIG. 4, the shunt 192 mentioned in the
`45
`B, the processor 86 starts its program counter (not
`previous paragraph is removed, causing the MEDRE
`shown) as is conventionally done to start the operation
`SET/ signal to return to a high level as at point 156.
`of the system 22.
`Also at time G, the processor 86, via its transaction
`program, starts at program count zero, and the proces
`At time C in FIG, 4, the PFAILAand the DSBTMR
`signals are switched to a high level as shown at points
`sor 86 reads the PFAIL/ and the PWRUP signals (via
`50
`148 and 144, respectively, and the rest of the signals
`input port 92-I in FIG. 3). Because the PFAIL/ signal is
`shown in FIG. 4 are unchanged. At time C, the memory
`at a high level and the PWRUP signal is at a low level,
`section 84B (FIG. 2), consisting of the WAROMS, is
`it indicates that the reset is due to shunt 192 and there is
`no momentary power failure; accordingly, the transac
`enabled, and the firmware or transaction program asso
`ciated with the processor 86 and located in the memory
`tion program associated with the processor 86 bypasses
`55
`sections 82A and 82B has read the PFAIL/ signal
`the RESTORE operation and switches the CLRUP
`switching from a low to a high level via terminal PB1 of
`signal (via output port 92-O) from a high to a low level
`input port 92-I of memory section 82B (FIG. 3). Be
`as at point 158 in FIG. 4 to thereby initiate the ERASE
`operation beginning at time G in FIG. 4. The elapsed
`cause the power up (PWRUP) signal to terminal PB2 of
`the input port 92-I of memory section 82B is at a high
`time for an ERASE operation between the times G and
`60
`level, the processor 86 starts the RESTORE operation
`H is from 100 to 200 milliseconds. The transaction pro
`at time C. During the RESTORE operation, the data
`gram associated with the processor 86 is now at the
`which was stored in the non-volatile portion (EAROM
`same position it was in after time E (FIG. 4) in that
`normal operations by the terminal 20 may be per
`96) of memory section 84A is transferred to the volatile
`(RAM 94) portion of memory 84A. Any momentary
`formed.
`65
`power fluctuation in the PFAIL/ signal during a RE
`At time I in FIG. 4, the PFA