United States Patent (19)
`Harari et al.
`
`US005535328A
`Patent Number:
`11)
`(45) Date of Patent:
`
`5,535,328
`* Jul. 9, 1996
`
`54) NON-VOLATILE MEMORY SYSTEM CARD
`WITH FLASH ERASABLE SECTORS OF
`EEPROM CELLS INCLUDING A
`MECHANISM FOR SUBSTITUTING
`DEFECTIVE CELLS
`
`75 Inventors: Eliyahou Harari, Los Gatos; Robert
`D. Norman, San Jose, Sanjay
`Mehrotra, Milpitas, all of Calif.
`
`73) Assignee: SanDisk Corporation, Santa Clara,
`Calif.
`
`ck
`
`*) Notice:
`
`FOREIGN PATENT DOCUMENTS
`557723 of 1987 Australia.
`0086886 of 1983 European Pat. Off. .
`2136992 of 1984 European Pat. Off. .
`0243503 of 1987 European Pat. Off..
`0220718 of 1987 European Pat. Off. .
`0300264 of 1989 European Pat. Off. .
`0.178564 of 1986 Japan.
`1054543 of 1989 Japan.
`WO84.00628 of 1984 WIPO.
`OTHER PUBLICATIONS
`Miller, "Semidisk Disk Emulator.” Interface Age, p. 102,
`Nov., 1982.
`R", tE.talt Clewitt, "Bubble Memories as a Floppy Disk Replacement,”
`ge exp
`1978 MIDCON Technical Papers, vol. 2, pp. 1-7, Dec.
`Hancock, "Architecting a CCD Replacement for the IBM
`2305 Fixed Head Disk Drive.” Digest of Papers, Eighteenth
`IEEE Computer Society International Conference, pp.
`182-184, 1979.
`
`saw- F
`
`-
`
`I saw
`
`1978.
`
`(21) Appl. No.: 393,569
`22) Filed:
`Feb. 23, 1995
`
`Related U.S. Application Data
`
`(List continued on next page.)
`Primary Examiner-Matthew M. Kim
`A.
`63 Continuation of Ser. No. 174,768, Dec. 29, 1993, which is
`Attorney, Agent, or Firm-Majestic, Parsons, Siebert &
`CONGO of S.No. 663.838.626, 1665,
`No.
`Hsue
`5,297,148, which is a division of Ser. No. 337,566, Apr. 13,
`(57)
`ABSTRACT
`1989, abandoned.
`Int. Cl.' ............................. G06F 12/00; G06F 11/16
`(51
`A system of Flash EEprommemory chips with controlling
`52 U.S. Cl. ................................ 395/182,05, 395/182,06.
`circuits serves as non-volatile memory such as that provided
`395/442: 395/833; 36.5/218; 364/DIG. 1;
`by magnetic disk drives. Improvements include selective
`364/268.5
`multiple sector erase, in which any combinations of Flash
`58) Field of Search .............................. 364/200 MS File
`sectors may be erased together. Selective sectors among the
`36,900 MS File:37,0369/8.365/85
`selected combination may also be de-selected during the
`900,218,395.425,575,442,833, 1820s
`s at a w
`' '
`' "
`80 erase operation. Another improvement is the ability to remap
`and replace defective cells with substitute cells. The remap
`o
`ping is performed automatically as soon as a defective cell
`is detected. When the number of defects in a Flash sector
`References Cited
`U.S. PATENT DOCUMENTS
`becomes large, the whole sector is remapped. Yet another
`improvement is the use of a write cache to reduce the
`1/1972 Harper .................................... 395/435
`number of writes to the Flash EEprom memory, thereby
`3,633,175
`3. 2,3. Wi. a
`a %. minimizing the stress to the device from undergoing too
`4,250,570 2/1981 Tsang et al. ............................ E; many writelerase cycling
`(List continued on next page.)
`14 Claims, 5 Drawing Sheets
`
`56)
`
`s
`
`y
`
`OZill
`
`is a soapse own as a as so an a
`
`ling.
`
`220
`SECTOR ERASE SELECTAoESLECT
`
`a
`COMMUNicito N
`LINES
`
`227
`
`-2.
`
`23
`
`Ye (ERASE solitic:) .209
`
`(MEEEO
`
`
`
`ALTERNATE
`OEFEcs iA
`
`SECTOR PARTIC
`
`Petitioner Intel Corp., Ex. 1024
`IPR2023-00783
`
`

`

`5,535,328
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`4,281,398
`4,295.205
`4,354.253
`4,355,376
`4.380,066
`4,405,952
`4,422,161
`4,450,559
`4,456,971
`4,463,450
`4,479,214
`4493,075
`4,498,146
`4,514,830
`4,525,839
`4,527,251
`4,601,031
`4,612,640
`4,617,624
`4,617,651
`4,642,759
`4,654,847
`4,672,240
`4,688,219
`4,733,394
`
`7/1981 McKenny ................................ 365/200
`10/1981 Kunstadt ................................. 395/410
`10/1982 Naden ....................................... 365/5
`10/1982 Gould ............
`... 365/200
`4/1983 Spencer et al.
`395/182.04
`9/1983 Slakmon ................................... 360/49
`12/1983 Kressel et al.
`365/185.09
`5/1984 Bond et al. ............................... 371/10
`6/1984 Fukuda et al.
`... 395/500
`7/1984 Haeusele ................................. 365/200
`10/1984 Ryan ........................................ 371/2.2
`1/1985 Anderson et al.
`... 371/0.3
`2/1985 Martinez ..........
`... 395/442
`4/1985 Hagiwara et al.
`365/185.09
`6/1985 Nozawa et al. ...
`... 371/10.2
`7/1985 Nibby, Jr. et al.
`395/82.06
`7/1986 Waker et al. ....
`... 371/10.3
`9/1986 Mehrotra et al.
`... 371/40.1
`10/1986 Goodman ................................ 395/402
`10/1986 Ip et al. .................................. 365/200
`2/1987 Foster ....
`... 395/500
`4/1987 Dutton ......
`395/182.04
`6/1987 Smith et al.
`... 326/107
`8/1987 Takemae ...
`... 371/10.3
`3/1988 Giebel .................................... 371/10.3
`
`4,746,998 5/1988
`4,757,474 7/1988
`4,768,193 8/1988
`4,774,700 9/1988
`4,794,568 12/1988
`4,796,233
`1/1989
`4,827,452 5/1989
`4,896,262
`1/1990
`4,914,529 4/1990
`4,920,518 4/1990
`4924,331 5/1990
`4.942,556 7/1990
`4.945,535 7/1990
`4949,309 8/1990
`4,953,122 8/1990
`5,043,940
`8/1991
`5,123,016 6/1992
`5,134,616 7/1992
`5,297,148 3/1994
`
`Robinson et al. ..................... 360/72.
`Fukushi et al. .....
`... 36.5/0.3
`Takemae .........
`371/10.3
`Satoh et al. ............................... 369/54
`Lim et al. ...
`365/185.09
`Awaya et al. ...
`... 371/10.2
`Toyama et al. .
`... 365/200
`Wayama et al.
`... 395/500
`Bonke .............
`... 360/48
`Nakamura et al. .
`365,228
`Robinson et al. ..
`360/721
`Sasaki et al. ........................... 365/200
`Hosotani et al.
`. 395/182.06
`Rao ................
`365/185.12
`Williams ................................. 395/404
`Harari ................................ 365/185.03
`Miller et al. .......................... 371/10.3
`Barth, Jr. et al. ...................... 371/10.3
`Harariet al. ........................... 371/10.2
`OTHER PUBLICATIONS
`Wilson, "1-Mbit flash memories seek their role in system
`design,” Computer Design, vol. 28, No. 5, pp. 30-32, (Mar.
`1989).
`Jex, "Flash Memory Bios for PC and Notebook Computers',
`1991 IEEE,
`
`
`
`Petitioner Intel Corp., Ex. 1024
`IPR2023-00783
`
`

`

`U.S. Patent
`
`Jul. 9, 1996
`
`Sheet 1 of 5
`
`5,535,328
`
`
`
`SERAL DATA
`-1
`LINES
`
`EEPROM
`ARRAY
`
`FG. A.
`
`
`
`SYSTEM
`ADA
`O
`
`
`
`SERIAL DATA - - - - - -
`- - - - - f ow- mno enre was m awa- ww an e
`INESS
`EEPROM ARRAY
`3. LINESy
`57
`0GC
`AND
`
`33
`
`E
`
`55
`40
`DATA/ADDRESS
`
`
`
`
`
`~59
`
`3
`
`
`
`SYSTEM
`CONTROL LINES
`
`49
`
`EEPROM
`CHIP
`
`CHIP
`SELECT
`
`EEPROM
`CHIP 2
`
`O
`
`TO OTHER |
`EEPROM
`ARRAYS
`
`
`
`
`
`
`
`A g
`n 3
`s
`()
`
`EEPROM
`CHIP CHP N .
`SELECT
`---------------------
`
`
`
`Petitioner Intel Corp., Ex. 1024
`IPR2023-00783
`
`

`

`U.S. Patent
`
`Jul. 9, 1996
`
`Sheet 2 of 5
`
`5.535,328
`
`3.
`
`
`
`
`
`COMMUNICATION
`| LINES FLASH MEMORY CHIPS
`209
`
`- - -
`YYYYYYYY.
`
`CONTROLER
`
`YaYaYaNyaya
`
`
`
`a SwSWSYYYaYaxisy
`
`YYYYYYSASV
`
`SECTORS TO
`
`: -
`
`FIG2.
`
`220 N
`SECTOR ERASE SELECT/DESELECT
`23
`233
`
`
`
`SERA.
`
`INTERFACE
`
`{
`209-l
`COMMUNICATION 227
`LiNES
`
`
`
`
`
`We (ERASE WOLAGE)
`
`
`
`SECTOR
`
`2
`
`SECTOR
`
`SECTOR - 23
`
`
`
`SECTOR
`
`SECTOR
`
`SECTOR
`
`O
`
`Petitioner Intel Corp., Ex. 1024
`IPR2023-00783
`
`

`

`U.S. Patent
`
`Jul. 9, 1996
`
`Sheet 3 of 5
`
`5.535,328
`
`(t)
`
`(2)
`
`(3)
`
`(4)
`
`(5)
`
`(6)
`
`(7)
`
`(8)
`
`(9)
`
`POINT TO SECTOR TO BE ERASED
`
`TAG SECTOR POINTED TOBY
`SETTING THE ASSOCATED
`ERASE ENABLE REGISTER
`
`
`
`S THERE
`MORE SECTOR TO BE
`ERASED2
`
`
`
`NO
`NITATE ERASE SEQUENCE WITH
`A GLOBAL ENABLE ERASE COMMAND
`
`APPLY A PULSE OF ERASE VOLTAGE
`ONLY TO THE TAGGED SECTORS
`
`READ AND VERIFY THAI EACH
`SECTOR IS IN ERASED STATE
`
`S THER
`ANY SECTOR
`ERIFED,
`
`POINT TO SECTOR TO
`BE REMOVED FROM ERASE
`
`UNTAG SECTOR POINTED TO
`BY CLEARING THE ASSOCATED
`ERASE ENABLE REGISTER
`
`(0)
`
`()
`
`
`
`ARE ALL
`SECTORS
`ERIFED?
`YES
`END ERASE SEQUENCE BY
`WITHORAWING ENABLE ERASE COMMAND
`
`FG.-4.
`
`Petitioner Intel Corp., Ex. 1024
`IPR2023-00783
`
`

`

`U.S. Patent
`
`Jul. 9, 1996
`
`Sheet 4 of 5
`
`5.535,328
`
`1. 40
`TYPICAL
`SECTOR
`
`DATA
`
`403
`DATA
`PORTION
`
`407
`
`ERATIVE
`DEFECTS DATA
`DEFECT MAP
`
`409
`4.
`43 - ECC OTHERS
`SECTOR PARTITION
`FIG-5.
`
`- 405
`SPARE
`PORTION
`
`70
`CACHEV
`SYSTEM
`
`
`
`
`
`
`
`703
`
`705
`
`
`
`CACHE
`BUFFER
`
`DATA
`
`f
`
`PWR /
`
`MEMORY
`
`75
`FILE TAG
`ANDTIME
`STAMP
`EOR
`
`
`
`
`
`TIMERS
`
`FIG.8.
`
`
`
`
`
`HOST
`
`INTERFACE
`
`ADDR
`
`Petitioner Intel Corp., Ex. 1024
`IPR2023-00783
`
`

`

`U.S. Patent
`
`Jul. 9, 1996
`
`Sheet 5 of S
`
`5,535,328
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`5
`COMMAND
`QUENCER
`
`ADDRESS
`GENERATOR
`
`33
`
`COMPARATOR DEC POINTER
`MEMORY FILE/
`HEADER COMPARE
`
`READ DATA PATH CONTROL
`FIG.6.
`
`5
`
`Josef POINTER
`COMPARAOR HEA);
`HEADER COMPARE
`ALTE
`RNATE
`DEFECIS (SPARES)
`S MUX s
`
`WRITE DAIA PATH CONTROL
`FIG.I.
`
`Petitioner Intel Corp., Ex. 1024
`IPR2023-00783
`
`

`

`1.
`NON-VOLATILE MEMORY SYSTEM CARD
`WTH FLASH ERASABLE SECTORS OF
`EEPROM CELLS INCLUDING A
`MECHANISM FOR SUBSTITUTING
`DEFECTIVE CELLS
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`This application is a continuation of co-pending applica
`tion Ser. No. 08/174,768, filed Dec. 29, 1993, which in turn
`is a continuation of application Ser. No. 07/963,838, filed
`Oct. 20, 1992, now U.S. Pat. No. 5,297,148, which in turn
`is a division of original application Ser. No. 071337,566,
`filed Apr. 13, 1989, now abandoned, which are all hereby
`incorporated herein by this reference.
`BACKGROUND OF THE INVENTION
`This invention relates generally to semiconductor electri
`cally erasable programmable read only memories (EEprom),
`and specifically to a system of integrated circuit Flash
`EEprom chips.
`Computer systems typically use magnetic disk drives for
`mass storage of data. However, disk drives are disadvanta
`geous in that they are bulky and in their requirement for high
`precision moving mechanical parts. Consequently they are
`not rugged and are prone to reliability problems, as well as
`consuming significant amounts of power. Solid state
`memory devices such as DRAM's and SRAM's do not
`suffer from these disadvantages. However, they are much
`more expensive, and require constant power to maintain
`their memory (volatile). Consequently, they are typically
`used as temporary storage.
`EEprom's and Flash EEprom's are also solid state
`memory devices. Moreover, they are nonvolatile, and retain
`their memory even after power is shut down. However,
`conventional Flash EEprom's have a limited lifetime in
`terms of the number of write (or program)/erase cycles they
`can endure. Typically the devices are rendered unreliable
`after 10° to 10 write/erase cycles. Traditionally, they are
`typically used in applications where semi-permanent storage
`of data or program is required but with a limited need for
`reprogramming.
`Accordingly, it is an object of the present invention to
`provide a Flash EEprom memory system with enhanced
`performance and which remains reliable after enduring a
`large number of writelerase cycles.
`It is another object of the present invention to provide an
`improved Flash EEprom system which can serve as non
`volatile memory in a computer system.
`It is another object of the present invention to provide an
`improved Flash EEprom system that can replace magnetic
`disk storage devices in computer systems.
`It is another object of the present invention to provide a
`Flash EEprom system with improved erase operation.
`It is another object of the present invention to provide a
`Flash EEprom system with improved error correction.
`It is yet another object of the present invention to provide
`a Flash EEprom with improved write operation that mini
`mizes stress to the Flash EEprom device.
`It is still another object of the present invention to provide
`a Flash EEprom system with enhanced write operation.
`SUMMARY OF THE INVENTION
`These and additional objects are accomplished by
`improvements in the architecture of a system of EEprom
`
`35.
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`5,535,328
`
`10
`
`15
`
`20
`
`25
`
`30
`
`2
`chips, and the circuits and techniques therein.
`According to one aspect of the present invention, an array
`of Flash EEprom cells on a chip is organized into sectors
`such that all cells within each sector are erasable at once. A
`Flash EEprom memory system comprises one or more Flash
`EEprom chips under the control of a controller. The inven
`tion allows any combination of sectors among the chips to
`be selected and then erased simultaneously. This is faster
`and more efficient than prior art schemes where all the
`sectors must be erased every time or only one sector at a time
`can be erased. The invention further allows any combination
`of sectors selected for erase to be deselected and prevented
`from further erasing during the erase operation. This feature
`is important for stopping those sectors that are first to be
`erased correctly to the "erased” state from over erasing,
`thereby preventing unnecessary stress to the Flash EEprom
`device. The invention also allows a global de-select of all
`sectors in the system so that no sectors are selected for erase.
`This global reset can quickly put the system back to its initial
`state ready for selecting the next combination of sectors for
`erase. Another feature of the invention is that the selection
`is independent of the chip select signal which enables a
`particular chip for read or write operation. Therefore it is
`possible to perform an erase operation on some of the Flash
`EEprom chips while read and write operations may be
`performed on other chips not involved in the erase operation.
`According to another aspect of the invention, improved
`error correction circuits and techniques are used to correct
`for errors arising from defective Flash EEprom memory
`cells. One feature of the invention allows defect mapping at
`cell level in which a defective cell is replaced by a substitute
`cell from the same sector. The defect pointer which connects
`the address of the defective cell to that of the substitute cell
`is stored in a defect map. Every time the defective cell is
`accessed, its bad data is replaced by the good data from the
`substitute cell.
`Another feature of the invention allows defect mapping at
`the sector level. When the number of defective cells in a
`sector exceeds a predetermined number, the sector contain
`ing the defective cells is replaced by a substitute sector.
`An important feature of the invention allows defective
`cells or defective sectors to be remapped as soon as they are
`detected thereby enabling error correction codes to
`adequately rectify the relatively few errors that may crop up
`in the system.
`According to yet another aspect of the present invention,
`a write cache is used to minimize the number of writes to the
`Flash EEprom memory. In this way the Flash EEprom
`memory will be subject to fewer stress inducing write/erase
`cycles, thereby retarding its aging. The most active data files
`are written to the cache memory instead of the Flash
`EEprom memory. Only when the activity levels have
`reduced to a predetermined level are the data files written
`from the cache memory to the Flash EEprom memory.
`Another advantage of the invention is the increase in write
`throughput by virtue of the faster cache memory.
`According to yet another aspect of the present invention,
`one or more printed circuit cards are provided which contain
`controller and EEprom circuit chips for use in a computer
`system memory for long term, non-volatile storage, in place
`of a hard disk system, and which incorporate various of the
`other aspects of this invention alone and in combination.
`Additional objects, features, and advantages of the present
`invention will be understood from the following description
`of its preferred embodiments, which description should be
`taken in conjunction with the accompanying drawings.
`
`Petitioner Intel Corp., Ex. 1024
`IPR2023-00783
`
`

`

`5,535,328
`
`3.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1A is a general micrprocessor system including the
`Flash EEprom memory system of the present invention;
`FIG. 1B is schematic block diagram illustrating a system
`including a number of Flash EEprom memory chips and a
`controller chip;
`FIG. 2 is a schematic illustration of a system of Flash
`EEprom chips, among which memory sectors are selected to
`be erased;
`FIG. 3A is a block circuit diagram on a flash EEprom Chip
`for implementing selective multiple sector erase according
`to the preferred embodiment;
`FIG. 3B shows details of a typical register used to select
`a sector for erase as shown in FIG. 2A;
`FIG. 4 is a flow diagram illustrating the erase sequence of
`selective multiple sector erase;
`FIG. 5 is a schematic illustration showing the partitioning
`of a Flash EEprom sector into a data area and a spare
`redundant area;
`FIG. 6 is a circuit block diagram illustrating the data path
`control during read operation using the defect mapping
`scheme of the preferred embodiment;
`FIG. 7 is a circuit block diagram illustrating the data path
`control during the write operation using the defect mapping
`scheme of the preferred embodiment;
`FIG. 8 is a block diagram illustrating the write cache
`circuit inside the controller.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`4
`Referring to FIG. 1B, the controller 31 is preferably
`formed primarily on a single integrated circuit chip. It is
`connected to the system address and data bus 39, part of the
`system bus 33, as well as being connected to system control
`lines 41, which include interrupt, read, write and other usual
`computer system control lines.
`The EEprom array 33 includes a number of EEprom
`integrated circuit chips 43, 45, 47, etc. Each includes a
`respective chip select and enable line 49, 51 and 53 from
`interface circuits 40. The interface circuits 40 also act to
`interface between the serial data lines 35, 37 and a circuit 55.
`Memory location addresses and data being written into or
`read from the EEprom chips 43, 45, 47, etc. are communi
`cated from a bus 55, through logic and register circuits 57
`and thence by another bus 59 to each of the memory chips
`43, 45, 47 etc.
`The bulk storage memory 29 of FIGS. 1A and 1B can be
`implemented on a single printed circuit card for moderate
`memory sizes. The various lines of the system buses 39 and
`41 of FIG. 1B are terminated in connecting pins of such a
`card for connection with the rest of the computer system
`through a connector. Also connected to the card and its
`components are various standard power supply voltages (not
`shown).
`For large amounts of memory, that which is conveniently
`provided by a single array 33 may not be enough. In such a
`case, additional EEprom arrays can be connected to the
`serial data lines 35 and 37 of the controller chip 31, as
`indicated in FIG. 1B. This is preferably all done on a single
`printed circuit card but if space is not sufficient to do this,
`then one or more EEprom arrays may be implemented on a
`second printed circuit card that is physically mounted onto
`the first and connected to a common controller chip 31.
`Erase of Memory Structures
`In system designs that store data in files or blocks the data
`will need to be periodically updated with revised or new
`information. It may also be desirable to overwrite some no
`longer needed information, in order to accommodate addi
`tional information. In a Flash EEprom memory, the memory
`cells must first be erased before information is placed in
`them. That is, a write (or program) operation is always
`preceded by an erase operation.
`In conventional Flash erase memory devices, the erase
`operation is done in one of several ways. For example, in
`some devices such as the Intel corporation's model 27F-256
`CMOS Flash EEprom, the entire chip is erased at one time.
`If not all the information in the chip is to be erased, the
`information must first be temporarily saved, and is usually
`written into another memory (typically RAM). The infor
`mation is then restored into the nonvolatile Flash erase
`memory by programming back into the device. This is very
`slow and requires extra memory as holding space.
`In other devices such as Seeq Technology Incorporated's
`model 48512 Flash EEprom chip, the memory is divided
`into blocks (or sectors) that are each separately erasable, but
`only one at a time. By selecting the desired sector and going
`through the erase sequence the designated area is erased.
`While, the need for temporary memory is reduced, erase in
`various areas of the memory still requires a time consuming
`sequential approach.
`In the present invention, the Flash EEprom memory is
`divided into sectors where all cells within each sector are
`erasable together. Each sector can be addressed separately
`and selected for erase. One important feature is the ability to
`select any combination of sectors for erase together. This
`will allow for a much faster system erase than by doing each
`one independently as in prior art.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`EEprom System
`A computer system in which the various aspects of the
`present invention are incorporated is illustrated generally in
`FIG. 1A. A typical computer system architecture includes a
`microprocessor 21 connected to a system bus 23, along with
`random access, main system memory 25, and at least one or
`more input-output devices 27, such as a keyboard, monitor,
`modem, and the like. Another main computer system com
`ponent that is connected to a typical computer system bus 23
`is a large amount of long-term, non-volatile memory 29.
`Typically, such a memory is a disk drive with a capacity of
`tens of megabytes of data storage. This data is retrieved into
`the system volatile memory 25 for use in current processing,
`and can be easily supplemented, changed or altered.
`One aspect of the present invention is the substitution of
`a specific type of semiconductor memory system for the disk
`drive but without having to sacrifice non-volatility, ease of
`erasing and rewriting data into the memory, speed of access,
`low cost and reliability. This is accomplished by employing
`an array of electrically erasable programmable read only
`memories (EEprom's) integrated circuit chips. This type of
`memory has additional advantages of requiring less power to
`operate, and of being lighter in weight than a hard disk drive
`magnetic media memory, thereby being especially suited for
`battery operated portable computers.
`The bulk storage memory 29 is constructed of a memory
`controller 31, connected to the computer system bus 23, and
`an array 33 of EEprom integrated circuit chips. Data and
`instructions are communicated from the controller 31 to the
`EEprom array 33 primarily over a serial data line 35.
`Similarly, data and status signals are communicated from the
`EEprom 33 to the controller 31 over serial data lines 37.
`Other control and status circuits between the controller 31
`and the EEprom array 33 are not shown in FIG. 1A.
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`Petitioner Intel Corp., Ex. 1024
`IPR2023-00783
`
`

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`5,535,328
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`S
`FIG. 2 illustrates schematically selected multiple sectors
`for erase. A Flash EEprom system includes one or more
`Flash EEprom chips such as 201, 203, 205. They are in
`communication with a controller 31 through lines 209.
`Typically, the controller 31 is itself in communication with
`a microprocessor system (not shown). The memory in each
`Flash EEprom chip is partitioned into sectors where all
`memory cells within a sector are erasable together. For
`example, each sector may have 512 byte (i.e. 512x8 cells)
`available to the user, and a chip may have 1024 sectors. Each
`sector is individually addressable, and may be selected, such
`as sectors 211, 213, 215, 217 in a multiple sector erase. As
`illustrated in FIG. 2, the selected sectors may be confined to
`one EEprom chip or be distributed among several chips in a
`system. The sectors that were selected will all be erased
`together. This capability will allow the memory and system
`of the present invention to operate much faster than the prior
`art architectures.
`FIG. 3A illustrates a block diagram circuit 220 on a Flash
`EEprom chip (such as the chip 201 of FIG. 2) with which
`one or more sectors such as 211, 213 are selected (or
`deselected) for erase. Essentially, each sector such as 211,
`213 is selected or tagged by setting the state of an erase
`enable register such as 221, 223 associated with the respec
`tive sectors. The selection and subsequent erase operations
`are performed under the control of the controller 31 (see
`FIG. 2). The circuit 220 is in communication with the
`controller 31 through lines 209. Command information from
`the controller is captured in the circuit 220 by a command
`register 225through a serial interface 227. It is then decoded
`by a command decoder 229 which outputs various control
`signals. Similarly, address information is captured by an
`address register 231 and is decoded by an address decoder
`233.
`For example, in order to select the sector 211 for erase, the
`controller sends the address of the sector 211 to the circuit
`220. The address is decoded in line 235 and is used in
`combination with a set erase enable signal in bus 237 to set
`an output 239 of the register 221 to HIGH. This enables the
`sector 211 in a subsequent erase operation. Similarly, if the
`sector 213 is also desired to be erased, its associated register
`223 may be set HIGH.
`FIG. 3B shows the structure of the register such as 221,
`223 in more detail. The erase enable register 221 is a
`SET/RESET latch. Its set input 241 is obtained from the set
`erase enable signal in bus 237 gated by the address decode
`in line 235. Similarly, the reset input 243 is obtained from
`the clear erase enable signal in bus 237 gated by the address
`decode in line 235. In this way, when the set erase enable
`signal or the clear erase enable signal is issued to all the
`sectors, the signal is effective only on the sector that is being
`addressed.
`After all sectors intended for erase have been selected, the
`controller then issues to the circuit 220, as well as all other
`chips in the system a global erase command in line 251
`along with the high voltage for erasing in line 209. The
`device will then erase all the sectors that have been selected
`(i.e. the sectors 211 and 213) at one time. In addition to
`erasing the desired sectors within a chip, the architecture of
`the present system permits selection of sectors across vari
`ous chips for simultaneous erase.
`FIGS. 4(1)–4(11) illustrate the algorithm used in conjunc
`tion with the circuit 220 of FIG. 3A. In FIG. 4(1), the
`controller will shift the address into the circuit 220 which is
`decoded in the line to the erase enable register associated
`with the sector that is to be erased. In FIG. 4(2), the
`controller shifts in a command that is decoded to a set erase
`
`6
`enable command which is used to latch the address decode
`signal onto the erase enable register for the addressed sector.
`This tags the sector for subsequent erase. In FIG. 4(3), if
`more sectors are to be tagged, the operations described
`relative to FIGS. 4(1)–4(2) are repeated until all sectors
`intended for erase have been tagged. After all sectors
`intended for erase have been tagged, the controller initiates
`an erase cycle as illustrated in FIG. 4(4).
`Optimized erase implementations have been disclosed in
`two copending U.S. patent applications. They are copending
`U.S. patent applications, Ser. No. 204,175, filed Jun. 8,
`1988, now U.S. Pat. No. 5,095,344, by Dr. Eliyahou Harari
`and one entitled "Multi-State EEprom Read and Write
`Circuits and Techniques," filed on the same day as the
`present application, by Sanjay Mehrotra and Dr. Eliyahou
`Harari. The disclosures of the two applications are hereby
`incorporate by reference. The Flash EEprom cells are erased
`by applying a pulse of erasing voltage followed by a read to
`verify if the cells are erased to the "erased' state. If not,
`further pulsing and verifying are repeated until the cells are
`verified to be erased. By erasing in this controlled manner,
`the cells are not subject to over-erasure which tends to age
`the EEprom device prematurely as well as make the cells
`harder to program.
`As the group of selected sectors is going through the erase
`cycle, some sectors will reach the "erase' state earlier than
`others. Another important feature of the present invention is
`the ability to remove those sectors that have been verified to
`be erased from the group of selected sectors, thereby pre
`venting them from over-erasing.
`Returning to FIG.4(4), after all sectors intended for erase
`have been tagged, the controller initiates an erase cycle to
`erase the group of tagged sectors. In FIG. 4(5), the controller
`shifts in a global command called Enable Erase into each
`Flash EEprom chip that is to perform an erase. This is
`followed in FIG. 4(5) by the controller raising of the erase
`voltage line (Ve) to a specified value for a specified duration.
`The controller will lower this voltage at the end of the erase
`duration time. In FIG. 4(6), the controller will then do a read
`verify sequence on the sectors selected for erase. In FIG.
`4(7), if none of the sectors are verified, the sequences
`illustrated in FIGS. 4(5)-4(7) are repeated. In FIGS. 4(8)
`and 3(9), if one or more sectors are verified to be erased, they
`are taken out of the sequence. Referring also to FIG. 3A, this
`is achieved by having the controller address each of the
`verified sectors and clear the associated erase enable regis
`ters back to a LOW with a clear enable command in bus 237.
`The sequences illustrated in FIGS. 4(5)-4(10) are repeated
`until all the sectors in the group are verified to be erased in
`FIG. 4(11). At the completion of the erase cycle, the con
`troller will shift in a No Operation (NOP) command and the
`global Enable Erase command will be withdrawn as a
`protection against a false erasure.
`The ability to select which sectors to erase and which ones
`not to, as well as which ones to stop erasing is advantageous.
`It will allow sectors that have erased before the slower
`erased sectors to be removed from the erase sequence so no
`further stress on the device will occur. This will increase the
`reliability of the system. Additional advantage is that if a
`sector is bad or is not used for some reason, that sector can
`be skipped over with no erase occurring within that sector.
`For example, if a sector is defective and have shorts in it, it
`may consume much power. A significant system advantage
`is gained by the present invention which allows it to be
`skipped on erase cycles so that it may greatly reduce the
`power required to erase the chip.
`Another consideration in having the ability to pick the
`sectors to be erased within a device is the power savings to
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`Petitioner Intel Corp., Ex. 1024
`IPR2023-00783
`
`

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`7
`the system. The flexibility in erase configuration of the
`present invention enables the adaptation of the erase needs
`to the power capability of the system. This can be done by
`configuring the systems to be erased differently by software
`on a fixed basis between different systems. It also will allow
`the controller to adaptively change the amount of erasing
`being done by monitoring the voltage level in a system, such
`as a laptop computer.
`An additional performance capability of the system in the
`present invention is the ability to issue a reset command to
`a Flash EEprom chip which will clear all erase enable
`latches and will prevent any further erase cycles from
`occurring. This is illustrated in FIGS. 2A and 2B by the reset
`signal in the line 261. By doing this in a global way to all
`the chips, less time will be taken to reset all the erase enable
`registers.
`An additional performance capability is to have the ability
`to do erase operations without regard to chip select. Once an
`erase is started in some of the memory chips, the controller
`in the system can access other memory chips and do read
`and write operations on them. In addition, the device(s)
`doing the erase can be selected and have an address loaded
`for the next command following the erase.
`Defect Mapping
`Physical defects in memory devices give rise to hard
`errors. Data becomes corrupted whenever it is stored in the
`defective cells. In conventional memory devices such as
`RAM's and Disks, any physical defects arising from the
`manufacturing process are corrected at the factory. In
`RAM's, spare redundant memory cells on chip may be
`patched on, in place of the defective cells. In the traditional
`disk drive, the