Case 6:22-cv-00335-ADA Document 47 Filed 12/28/22 Page 1 of 24
`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE WESTERN DISTRICT OF TEXAS
`WACO DIVISION
`
`BiTMICRO LLC,
`
`Plaintiff,
`
`v.
`
`KIOXIA AMERICA, INC.
`and KIOXIA CORPORATION,
`
`Defendants.
`
`BiTMICRO LLC,
`
`Plaintiff,
`
`v.
`
`INTEL CORPORATION,
`
`Defendant.
`
`Civil Action No.: 6:22-cv-00331-ADA
`
`Civil Action No.: 6:22-cv-00335-ADA
`
`PLAINTIFF BITMICRO LLC’S SUR-REPLY CLAIM CONSTRUCTION BRIEF
`
`Petitioner Intel Corp., Ex. 1019
`IPR2023-00783
`
`

`

`Case 6:22-cv-00335-ADA Document 47 Filed 12/28/22 Page 2 of 24
`
`TABLE OF CONTENTS
`
`Page
`
`C. 
`
`D. 
`
`’939 PATENT ..................................................................................................................... 1 
`A. 
`“predetermined level” ............................................................................................. 1 
`B. 
`“means for deactivating the plurality of super capacitors to cut off power
`to the computing engine based upon the plurality of super capacitors
`discharging to a predetermined level” .................................................................... 2 
`“reversing the flow of current between the computing engine and the
`plurality of super capacitors” .................................................................................. 4 
`“means for reversing the flow of current between the computing engine
`and the plurality of super-capacitors” ..................................................................... 5 
`’243 PATENT ..................................................................................................................... 5 
`A. 
`“passive port” .......................................................................................................... 5 
`B. 
`“a plurality of modules each comprising” .............................................................. 7 
`’740 PATENT ..................................................................................................................... 8 
`A. 
`“optimized memory operations” ............................................................................. 8 
`B. 
`“optimally distributed” .......................................................................................... 10 
`C. 
`“memory store” ..................................................................................................... 11 
`’190 PATENT ................................................................................................................... 13 
`A. 
`“optimal” ............................................................................................................... 13 
`’084 AND ’694 PATENTS ............................................................................................... 14 
`“Direct Memory Access (DMA) descriptors” / “DMA controller
`A. 
`descriptor” ............................................................................................................. 14 
`CONCLUSION ................................................................................................................. 15 
`
`
`
`-i-
`
`
`
`I. 
`
`II. 
`
`III. 
`
`IV. 
`
`V. 
`
`VI. 
`
`
`
`Petitioner Intel Corp., Ex. 1019
`IPR2023-00783
`
`

`

`Case 6:22-cv-00335-ADA Document 47 Filed 12/28/22 Page 3 of 24
`
`TABLE OF AUTHORITIES
`
`Page(s)
`
`
`
`CASES 
`
`Advanced Micro Devices, Inc. v. LG Elecs., Inc.,
`No. 14-cv-01012-SI, 2017 WL 1383271 (N.D. Cal. Apr. 18, 2017) .................................. 9
`
`Cacace v. Meyer Mktg. (Macau Commercial Offshore) Co.,
`812 F. Supp. 2d 547 (S.D.N.Y. 2011) ............................................................................... 13
`
`CCS Fitness, Inc. v. Brunswick Corp.,
`288 F.3d 1359 (Fed. Cir. 2002)........................................................................................... 2
`
`Cont’l Circuits LLC v. Intel Corp.,
`915 F.3d 788 (Fed. Cir. 2019)............................................................................................. 1
`
`Data Retrieval Technology, LLC v. Sybase, Inc.,
`No. C 08-5481 VRW, 2010 WL 11586656 (N.D. Cal. Nov. 8, 2010) ............................. 13
`
`Info-Hold, Inc. v. Applied Media Techs. Corp.,
`783 F.3d 1262 (Fed. Cir. 2015)........................................................................................... 1
`
`Interval Licensing LLC v. AOL, Inc.,
`766 F.3d 1364 (Fed. Cir. 2014)........................................................................................... 9
`
`Liebel-Flarsheim Co. v. Medrad, Inc.,
`358 F.3d 898 (Fed. Cir. 2004)............................................................................................. 2
`
`Moleculon Research Corp. v. CBS, Inc.,
`793 F.2d 1261 (Fed. Cir. 1986)........................................................................................... 9
`
`Nabors Drilling Techs. USA, Inc. v. Helmerich & Payne Int’l Drilling Co.,
`No. 3:20-CV-03126-M, 2022 WL 1689444 (N.D. Tex. May 26,
`2022) ................................................................................................................................. 14
`
`Nichia Corp. v. Document Sec. Sys.,
`No. 2020-2261, 2022 WL 1218036 (Fed. Cir. Apr. 26, 2022) ........................................... 7
`
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005)................................................................................. 1, 5, 15
`
`RF Delaware, Inc. v. Pacific Keystone Techs., Inc.,
`326 F.3d 1255 (Fed. Cir. 2003)......................................................................................... 12
`
`Toro Co. v. White Consol. Indus., Inc.,
`199 F.3d 1295 (Fed. Cir. 1999)........................................................................................... 2
`
`
`
`-ii-
`
`Petitioner Intel Corp., Ex. 1019
`IPR2023-00783
`
`

`

`Case 6:22-cv-00335-ADA Document 47 Filed 12/28/22 Page 4 of 24
`
`
`
`Versata Software, Inc. v. Zoho Corp.,
`213 F. Supp. 3d 829 (W.D. Tex. 2016) ............................................................................... 9
`
`Wenger Mfg., Inc. v. Coating Machinery Sys., Inc.,
`238 F.3d 1225 (Fed. Cir. 2001)......................................................................................... 12
`
`WesternGeco L.L.C. v. ION Geophysical Corp.,
`876 F. Supp. 2d. 857 (S.D. Tex. 2012) ............................................................................... 3
`
`Williamson v. Google Inc.,
`No. 15-cv-00966-BLF, 2017 WL 3232582 (N.D. Cal. July 27, 2017) ............................... 3
`
`STATUTES 
`
`35 U.S.C. § 112(6) ...................................................................................................................... 2, 5
`
`
`
`-iii-
`
`Petitioner Intel Corp., Ex. 1019
`IPR2023-00783
`
`

`

`Case 6:22-cv-00335-ADA Document 47 Filed 12/28/22 Page 5 of 24
`
`
`
`Plaintiff BiTMICRO LLC (“BiTMICRO”) submits this sur-reply brief in support of its
`claim constructions.
`I.
`’939 PATENT
`A.
`“predetermined level”
`
`Patent
`’939 Patent
`Claims 1, 10
`
`BiTMICRO’s Proposal
`Plain and ordinary meaning.
`
`Defendants’ Proposal
`“a preset minimum operating voltage
`necessary for proper operation, in which the
`super capacitors are not fully discharged”
`“In construing claims, district courts give claims their ordinary and customary meaning,
`which is ‘the meaning that the term would have to a person of ordinary skill in the art in question
`at the time of the invention.’” Cont’l Circuits LLC v. Intel Corp., 915 F.3d 788, 796-797 (Fed. Cir.
`2019) (quoting Phillips v. AWH Corp., 415 F.3d 1303, 1312-13 (Fed. Cir. 2005)). Defendants have
`provided no reason to diverge from that principle with respect to “a predetermined level.” They
`have not identified anything in the claims that compels the import of the two limitations in their
`construction. Nor have Defendants identified anything in the specification or prosecution history
`wherein the patentee “clearly set forth a definition of the disputed claim term other than its plain
`and ordinary meaning” or “expressions of manifest exclusion or restriction, representing a clear
`disavowal of claim scope.” Cont’l Circuits, 915 F.3d at 1796-797 (internal quotations and citations
`omitted). At best, they have identified a description of an embodiment or even a “best mode,” but
`that is not enough. Id.
`Defendants did not make any “salient claim arguments” in their opening brief, nor does
`BiTMICRO agree with Defendants’ mischaracterizations of the ’939 Patent therein or on reply.
`Sure, the ’939 Patent specification discloses one embodiment wherein “a pre-determined level” is
`such that “the down-converter has insufficient voltage differential to continue proper operation
`and shuts down” (‘939 Patent at 5:39-43), but Defendants have not shown that the term must be
`construed as limited to that embodiment, nor should it be. Cont’l Circuits, 915 F.3d at 797; Info-
`Hold, Inc. v. Applied Media Techs. Corp., 783 F.3d 1262, 1267 (Fed. Cir. 2015); Liebel-Flarsheim
`
`
`
`-1-
`
`Petitioner Intel Corp., Ex. 1019
`IPR2023-00783
`
`

`

`Case 6:22-cv-00335-ADA Document 47 Filed 12/28/22 Page 6 of 24
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`
`
`Co. v. Medrad, Inc., 358 F.3d 898, 906 (Fed. Cir. 2004). And Defendants oversell the cited portions
`of the specification at 5:44-48 and 6:45-49, which describe “two positive side effects” of that
`embodiment. Compare Reply at 1 with ’939 Patent at 5:44-57. Nor is it true, as Defendants
`contend, that “a threshold set below a minimum operating voltage necessary for proper operation
`would fatally undermine the ’939 Patent’s stated goals of ensuring that ‘a user is able to correctly
`store large amounts of newly written and modified data’ and ‘rapidly and irretrievably erase data.’”
`Reply at 1. Indeed, Defendants mischaracterize the relationship between those goals and the
`“minimum operating voltage necessary for proper operation.” Provided that the claimed system
`can supply enough power to the computing engine to store or erase the data in question before the
`capacitors are discharged to a predetermined level (i.e., the capacitors have sufficient capacity),
`the system operates properly. That is perhaps why those portions of the ’939 Patent that discuss
`“goals” of the claimed invention do not mention the “minimum operating voltage necessary for
`proper operation.” See e.g., ’939 Patent at 1:8-2:21, 2:25-43, 3:3-27. For these reasons,
`Defendants’ cited cases are inapposite. See CCS Fitness, Inc. v. Brunswick Corp., 288 F.3d 1359,
`1366-67 (Fed. Cir. 2002); Toro Co. v. White Consol. Indus., Inc., 199 F.3d 1295, 1301 (Fed. Cir.
`1999) (statements admitting the “important to the invention”).
`Finally, Defendants try to run away from the fact that they used “predetermined level” in
`their own patents directed to similar subject matter. But BiTMICRO is not, as in the cases cited by
`Defendants, seeking to import a definition or limitations from another patent. Rather, it is simply
`relying on Defendants’ use in its other patents to confirm what is already obvious to the Court—
`that the term “a predetermined level” has a plain and ordinary meaning to those skilled in the art.
`B.
`“means for deactivating the plurality of super capacitors to cut off power to
`the computing engine based upon the plurality of super capacitors
`discharging to a predetermined level”
`
`Patent
`’939 Patent
`Claim 10
`
`BiTMICRO’s Proposal
`Function: deactivating the plurality of super capacitors
`to cut off power to the computing engine based upon
`the plurality of super capacitors discharging to a
`predetermined level.
`
`Defendants’ Proposal
`Indefinite under 35
`U.S.C. § 112(6):
`Lacks corresponding
`structure.
`
`
`
`-2-
`
`Petitioner Intel Corp., Ex. 1019
`IPR2023-00783
`
`

`

`Case 6:22-cv-00335-ADA Document 47 Filed 12/28/22 Page 7 of 24
`
`
`
`Structure: Col. 3:3-12, 3:28-4:8, 5:35-42, 6:37-44, Figs.
`1, 3, 5, of the ’939 Patent, and equivalents thereof.
`After being called out for putting forward nonsensical arguments that rely on nonsensical
`meanings for “deactivating the plurality of supercapacitors,” Defendants seek to foist the liability
`for their arguments on BiTMICRO and the ’939 Patent. Compare e.g., Resp. at 9 (questions posed
`to Defendants) with Reply at 3 (Defendants deflecting and refusing to answer). But that is absurd.
`The claim refers to “deactivating the plurality of super capacitors to cut off power to the
`computing engine.” The plain and ordinary meaning of “deactivating the plurality of super
`capacitors” is to make inactive, e.g., by disconnecting from other elements of the system as in “the
`switch deactivates the alarm.” Hence, the plain and ordinary meaning of the claim language is to
`make the plurality of super capacitors inactive, e.g., by disconnecting them from the rest of the
`system, “to cut off power to the computing engine.” The claim language also conveys when this
`is done: i.e., “based upon the plurality of super capacitors discharging to a predetermined level.”
`This language is so straightforward that neither a POSITA nor a jury would require more
`explanation. Consistent therewith, Defendants did not challenge this same language in claim 1 for
`indefiniteness, even though it contains the exact same language save for the phrase “means for.”
`Claim 1 (not challenged)
`Claim 10 (challenged)
`(c) deactivating the plurality of super capacitors to
`means for deactivating the plurality of super
`cut off power to the computing engine based upon
`capacitors to cut off power to the computing engine
`the plurality of super capacitors discharging to a
`based upon the plurality of super capacitors
`predetermined level.
`discharging to a predetermined level.
`In other words, Defendants do not believe this limitation is indefinite, but nevertheless seek to take
`advantage of the case law built up around means-plus-function terms to try to get it rendered
`indefinite anyway. But to do so, they had to take nonsensical positions to which no expert would
`sign on. See Williamson v. Google Inc., No. 15-cv-00966-BLF, 2017 WL 3232582, at *10 (N.D.
`Cal. July 27, 2017); see also WesternGeco L.L.C. v. ION Geophysical Corp., 876 F. Supp. 2d. 857,
`875 (S.D. Tex. 2012).
`The simple fact is that the ’939 Patent specification discloses structure that deactivates the
`plurality of super capacitors to cut off power to the computing engine based on the plurality of
`
`
`
`-3-
`
`Petitioner Intel Corp., Ex. 1019
`IPR2023-00783
`
`

`

`Case 6:22-cv-00335-ADA Document 47 Filed 12/28/22 Page 8 of 24
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`
`
`super capacitors discharging to a predetermined level. As noted in BiTMICRO’s response, that
`structure consists of the “charge level sensors 30,” which informs the computer system whether
`the plurality of capacitors have discharged to a predetermined level, the “down converter DC 42,”
`which turns off or shuts down thereby disconnecting the plurality of super capacitors from the rest
`of the system and accordingly “cut[ting] off power to the computing engine,” and other related
`circuitry (like the power isolator and up converter that revert to their original states). See Resp. at
`6-9. Defendants continue to push the absurd argument that “deactivating” super capacitors requires
`a different structure than that disclosed, but have never been able to identify what such a structure
`might be. And Defendants’ argument that the structures disclosed are not “clearly linked” to the
`claim language is patently absurd, since a 1:1 mapping of structure and claim is clearly evident.
`C.
`“reversing the flow of current between the computing engine and the
`plurality of super capacitors”
`
`Defendants’ Proposal
`Indefinite.
`
`BiTMICRO’s Proposal
`Plain and ordinary meaning; not indefinite.
`
`Patent
`’939 Patent
`Claim 6
`Here, Defendants again push arguments that it could not get a single expert to support. But
`BiTMICRO’s explanation of the current flow in its response brief is exactly what the specification
`describes. For example, consider the dashed line through the center of Figure 1; the specification
`explains that “the SC 34 and associated circuitry 30, 32, 36, 38, 42 [may be] configured as a
`removable option to the system 20.” ’939 Patent at 3:63-4:2. Such an embodiment clearly
`illustrates the “shared power plane of the EPS, Power Isolator and CE” that seems to confuse the
`Defendants. See Reply at 5, Resp. at 11. Moreover, Defendants’ admission that current flows in
`one direction when external power is supplied, and another direction when power is supplied by
`the capacitors, is entirely consistent with how a POSITA and jury would understand the claim.
`Compare e.g., Reply at 5 with Resp. at 11 (“These disclosures in the specification make clear that
`‘reverse’ in the claim language is referring to the change in the flow of current in the system from
`the normal state (when power is supplied by the EPS to the computing engine and to the capacitors
`to charge them) and backup state (when power is supplied from the capacitors to the computer
`
`
`
`-4-
`
`Petitioner Intel Corp., Ex. 1019
`IPR2023-00783
`
`

`

`Case 6:22-cv-00335-ADA Document 47 Filed 12/28/22 Page 9 of 24
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`
`
`engine)”).
`Defendants’ fallback argument–that the claim language requires the “computing engine”
`to provide power to super capacitors when external power is being supplied—is technical to a
`fault. Phillips makes clear that claims are to be construed from the perspective of a POSITA, and
`that the claims “do not stand alone” but are guided by the specification. A POSITA would have
`little trouble understanding the claim language at issue in view of those sources. Resp. at 9-11.
`
`D.
`
`“means for reversing the flow of current between the computing engine and
`the plurality of super-capacitors”
`
`Patent
`’939 Patent
`Claim 15
`
`Defendants’ Proposal
`Indefinite under 35
`U.S.C. § 112(6): Lacks
`corresponding structure.
`
`BiTMICRO’s Proposal
`Function: reversing the flow of current between the
`computing engine and the plurality of super
`capacitors.
`Structure: Col. 3:3-12, 3:28-4:8, 6:22-28, Figs. 1, 3,
`5, of the ’939 Patent, and equivalents thereof.
`This term is not indefinite for the same reasons as discussed with respect to the previous
`term. And the disclosures recited with respect to that term and the “deactivating” term above also
`identify the corresponding structure, i.e., the “circuity” in the cited passages of the specification.
`II.
`’243 PATENT
`A.
`“passive port”
`
`Patent
`’243 Patent
`Claims 1, 2
`
`BiTMICRO’s Proposal
`“connection between a passive
`ball and a passive pad”
`
`Intel’s Proposal
`“connection between a passive ball on one
`surface of a SDRAM module and a passive
`pad on another surface of the same SDRAM
`module”
`Intel incorrectly argues that the ’243 applicants affirmatively stated that they were acting
`as their own lexicographers to define “passive port.” The applicants merely stated to the
`examiner the general principle that “[a]pplicants may be their own lexicographers,” along with
`the legal principle that “[d]efiniteness of claim language must be analyzed, not in a vacuum, but
`in light of Applicants written disclosure, the prior art, and the claim interpretation that would be
`given by one of ordinary skill in the art . . . .” Ta Decl., Ex. F at 23. Merely reciting the state of
`
`
`
`-5-
`
`Petitioner Intel Corp., Ex. 1019
`IPR2023-00783
`
`

`

`Case 6:22-cv-00335-ADA Document 47 Filed 12/28/22 Page 10 of 24
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`
`
`the law to the examiner is not the same as explicitly defining a term.
`The applicants did not intend to limit “passive port” to just the Figure 19 embodiment, as
`Intel contends. To the contrary, the specification repeatedly notes that Figure 19 is merely an
`“example.” Ta Decl., Ex. F at 2 (“The figure illustrates the controller and SDRAM modules as an
`example.”); id. at 3 (“The example embodiment illustrated in Figure 19 comprises . . . .”). In
`addition, as BiTMICRO previously noted (Resp. at 15-16), the applicants’ discussion with the
`examiner emphasized that the defining characteristic of “passive port” is a connection between a
`ball and pad, rather than the specific connection within a single SDRAM module proposed by
`Intel. Such a narrow construction would even be inconsistent with the Figure 19 embodiment,
`which shows that a passive port can connect a ball and pad on different modules (1905) as well
`as on the same module (1909). See id. at 15-16. Intel responds that there is no inconsistency
`because the applicants said that “[t]he above description should be read in conjunction with
`amended Figure 19,” which is nonsensical. Reply at 9. The specification’s description of Figure
`19 specifically points out an example of a passive port as a connection between a ball and pad on
`different modules: ball X1 on SDRAM Module 1 and pad X2 on SDRAM Module 0. See Ex. 5 at
`9:8; Ta Decl., Ex. F at 3 (“passive ports 1905 connecting . . . passive ball X1 to passive pad
`X2”).1 Indeed, the principle cited by Intel that a patentee may draft claims to cover different
`embodiments has little weight here, where the embodiment that would be excluded from Intel’s
`proposed construction (Figure 19) is the very embodiment that the applicants cited to the
`examiner in their discussion of “passive port.”
`Finally, Intel cannot credibly argue that claim differentiation does not apply because
`dependent claim 2 adds multiple limitations, given that it takes the exact opposite position with
`respect to the ’740 claim terms. See Reply at 14-15 (“BiTMICRO is wrong that the presumption
`of claim differentiation does not apply simply because some of the dependent claims have
`
`
`1 For the Court’s convenience, attached as Appendix A to this reply brief is a chart showing the
`language in the ’243 specification regarding Figure 19 after applying the changes in the
`Certificate of Correction.
`
`
`
`-6-
`
`Petitioner Intel Corp., Ex. 1019
`IPR2023-00783
`
`

`

`Case 6:22-cv-00335-ADA Document 47 Filed 12/28/22 Page 11 of 24
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`
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`additional limitations.”).
`B.
`“a plurality of modules each comprising”
`
`Intel’s Proposal
`BiTMICRO’s Proposal
`Patent
`“each module in the stacked module
`Part of the preamble and not a
`’243 Patent
`comprises”
`limitation of the claim.
`Claim 1
`The preamble of claim 1 recites “[a] stacked module comprising a plurality of modules
`
`each comprising: . . . .” Intel’s proposal to break off the latter part of this phrase and construe it as
`a separate claim limitation would render claim 1 nonsensical, as the actual limitations in claim 1
`recite components that are not within “each module in the stacked module,” but are rather a part
`of the stacked module as a whole. See Resp. at 18-19.
`Reliance on Nichia Corp. v. Document Sec. Sys., No. 2020-2261, 2022 WL 1218036 (Fed.
`Cir. Apr. 26, 2022), is misplaced. In that case, the claim in dispute began with the language “[a]
`display comprising a plurality of plastic leaded chip carrier LEDs, the plastic leaded chip carrier
`LEDs each comprising.” Id. at *4 (emphasis added). There, the phrase “a display comprising”
`was separated by a comma from the subsequent phrase “the plastic leaded chip carrier LEDs each
`comprising.” Thus, the natural reading was that “each comprising” referred to the immediately
`preceding phrase “the plastic leaded chip carrier LEDs,” rather than to the term “display.” In ’243
`claim 1, however, the claim language recites “[a] stacked module comprising a plurality of
`modules each comprising,” with no intervening comma. Here, “each comprising” does not
`naturally refer to “plurality of modules.” Rather, it more sensibly refers to “a stacked module”
`when read in context with the rest of the limitations in claim 1. As discussed in BiTMICRO’s
`responsive brief, claim 1 includes the limitations of “a first serial chain route” and “a second serial
`chain route,” both of which are routes that run through multiple modules in the stack as described
`in the specification. Resp. at 18-19. But under Intel’s construction where “each module in the
`stacked module” has all of the limitations of the claims, each individual module in the stack would
`have both “a first serial chain route” and “a second serial chain route,” which does not make sense.
`Tellingly, Intel does not address this argument in its reply brief. It does not do so because it cannot
`
`
`
`-7-
`
`Petitioner Intel Corp., Ex. 1019
`IPR2023-00783
`
`

`

`Case 6:22-cv-00335-ADA Document 47 Filed 12/28/22 Page 12 of 24
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`
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`reconcile this inconsistency between its proposed construction and the specification’s description
`of the “first serial chain route” and “second serial chain route.”
`Intel’s focus on the portion of the ’243 specification discussing that all modules have a
`control circuit also misses the mark. The issue is not whether each module in the stack can have a
`control circuit. Rather, the problem with Intel’s construction is that claim 1 recites a specific
`requirement for the control circuit – namely, that the control circuit must be “for enabling a routing
`path that connects the first serial chain route with the second serial chain route within an end
`module.” The plain language of claim 1 therefore requires the control circuit of the claim to be in
`the end module. Indeed, Intel offers no explanation for how a control circuit in any other module
`could connect the first serial chain route with the second serial chain route within the end module.
`Intel’s construction requiring each module in the stack to have all the limitations of claim 1
`therefore makes no sense and should be rejected.
`III.
`’740 PATENT
`A.
`“optimized memory operations”
`
`Defendants’ Proposal
`Indefinite.
`
`BiTMICRO’s Proposal
`Plain and ordinary meaning; not indefinite.
`
`Patent
`’740 Patent
`Claim 1
`Defendants cannot show by clear and convincing evidence that the term “optimized
`memory operations” is indefinite. As discussed in BiTMICRO’s responsive brief, during
`prosecution of the ’740 patent the applicants explained to the examiner how the specification
`teaches a mapping table that causes a storage device to perform “optimized memory operations,”
`thereby providing a POSITA with sufficient guidance as to what that term means. Resp. at 21.
`Defendants incorrectly suggest that that portion of the file history is irrelevant because the
`discussion involved a response to a written description rejection, not an indefiniteness rejection.
`But it does not matter what type of rejection the applicants were responding to. Rather, what
`matters is that the applicants made specific statements during prosecution regarding the meaning
`of “optimized memory operations” from which a POSITA would understand the scope of that term
`
`
`
`-8-
`
`Petitioner Intel Corp., Ex. 1019
`IPR2023-00783
`
`

`

`Case 6:22-cv-00335-ADA Document 47 Filed 12/28/22 Page 13 of 24
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`
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`with reasonable certainty. Defendants fail to present any evidence to the contrary. Having offered
`no expert testimony to support their assertions, Defendants cannot prove that “optimized memory
`operations” is indefinite. See Advanced Micro Devices, Inc. v. LG Elecs., Inc., No. 14-cv-01012-
`SI, 2017 WL 1383271, at *4 (N.D. Cal. Apr. 18, 2017) (defendant failed to prove indefiniteness
`because it “provides no expert testimony to support . . . its broader indefiniteness contentions,
`despite needing to prove its position by clear and convincing evidence.”).
`Defendants argue that expert testimony is not required prove indefiniteness, but the cases
`cited by Defendants do not support their position. In Interval Licensing LLC v. AOL, Inc., 766 F.3d
`1364, 1370 n.6 (Fed. Cir. 2014), the Federal Circuit affirmed an indefiniteness finding without
`supporting expert testimony only because in that case “there are no disputes about underlying
`questions of fact.” But in the present case, there is a factual dispute as to what a POSITA would
`understand based on the disclosures in the ’740 specification. And Moleculon Research Corp. v.
`CBS, Inc., 793 F.2d 1261, 1270 (Fed. Cir. 1986), does not even discuss indefiniteness, and is
`therefore completely inapposite.
`In addition, Defendants’ reliance on Versata Software, Inc. v. Zoho Corp., 213 F. Supp. 3d
`829 (W.D. Tex. 2016), is misplaced. In that case, the court held that the term “space-constrained
`display” was indefinite because the specification at best provided only a few examples of such
`displays, and did not define what types of displays would not be “space-constrained.” See id. at
`836-37. There is no such problem here. The ’740 Patent specifically defines “optimized memory
`operations” as “increasing the likelihood that, in response to an I/O transaction initiated by a host,
`the operational load imposed on the storage device by these memory operations will be optimally
`distributed across different storage device resources, such as by interleaving or parallel memory
`operations, reducing memory operation latency, increasing operational device efficiency, or both.”
`’740 Patent, 2:14-21. The patent also describes multiple ways of achieving this optimal distribution
`of memory operations. See id. at 6:46-7:18. The patent therefore provides sufficient disclosure for
`a POSITA to understand with reasonable certainty what falls within as well as outside the scope
`of “optimized memory operations.”
`
`
`
`-9-
`
`Petitioner Intel Corp., Ex. 1019
`IPR2023-00783
`
`

`

`Case 6:22-cv-00335-ADA Document 47 Filed 12/28/22 Page 14 of 24
`
`
`
`Defendants’ additional arguments regarding claim differentiation also lack merit.
`Defendants assert that the mapping table in Figure 2 (as well as any similar mapping table with
`more than two LBA sets) will necessarily have adjacent LBA sets, and so the scope of claim 1
`must be the same as claim 2. This makes no sense. Whether a mapping table has adjacent LBA
`sets or not is not the issue. Rather, the issue is which of the LBA sets are involved in the “optimized
`memory operations.” Claim 1 recites that the claimed mapping table causes “optimized memory
`operations on memory locations respectively associated with said first PBA and said second PBA,
`if the I/O transaction request is associated with said first and second LBA sets.” ’740 Patent, 10:19-
`24. Thus, claim 1 covers optimized memory operations where the I/O transaction request is
`associated with any two LBA sets in the mapping table, regardless of whether they are adjacent or
`non-adjacent. Claim 1 is therefore broader than claim 2, which is limited to optimized memory
`operations only if the I/O transaction request involves adjacent LBA sets. Id. at 10:25-26 (“2. The
`mapping table of claim 1, wherein: said first and second LBA sets are adjacent LBA sets . . . .”).
`Thus, there is no claim differentiation problem.
`B.
`“optimally distributed”
`
`Defendants’ Proposal
`Indefinite.
`
`BiTMICRO’s Proposal
`Plain and ordinary meaning; not indefinite.
`
`Patent
`’740 Patent
`Claim 32
`Defendants’ arguments for indefiniteness of “optimally distributed” fail for the same
`reasons that their arguments for indefiniteness of “optimized memory operations” fail. In addition,
`Defendants incorrectly argue that “claim 32 does not limit, and therefore extends, its reach to ‘I/O
`transaction request[s]’ with memory operations that use just one PBA.” Reply at 13. Not so.
`Defendants ignore the language in claim 32 stating that “said mapping table increases the
`likelihood that the operational load imposed on the storage apparatus during the processing of the
`I/O transaction request will be optimally distributed across storage device resources.” ’740 Patent,
`14:1-5 (emphasis added). The claim language here of distributing “across storage device
`resources” necessarily means that multiple PBAs are involved in “optimally distributed.” See id.
`
`
`
`-10-
`
`Petitioner Intel Corp., Ex. 1019
`IPR2023-00783
`
`

`

`Case 6:22-cv-00335-ADA Document 47 Filed 12/28/22 Page 15 of 24
`
`
`
`at 9:19-25. Claim 32 is therefore not unduly broad in scope as Defendants suggest. The scope of
`claim 32 still differs from claim 34, however, in that claim 32 does not specify which PBAs are
`used for the memory operations, whereas claim 34 specifically identifies memory operations using
`the recited “said first PBA” and “said second PBA.”
`C.
`“memory store”
`
`BiTMICRO’s Proposal
`“non-volatile, solid-state storage, e.g., flash”
`
`Defendants’ Proposal
`Patent
`Plain and ordinary
`’740 Patent
`meaning.
`Claims 1, 15, 32
`As noted in BiTMICRO’s responsive brief, the following passage in the ’740 specification
`equates “memory store” with solid-state storage:
`Memory store 6 may be configured to include a set of solid state memory devices
`that are coupled to a set of buses and that are controlled by a set of FDEs. In FIG.
`1, these memory devices, buses, and FDEs are implemented in the f