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`Petitioner Intel Corp., Ex. 1015
`IPR2023-00783, Pg. 1
`
`

`

`
`
`FILE HISTORY
`US 5,608,684
`
`5,608,684
`PATENT:
`INVENTORS: REASONER KELLY J
`WILLIAMS ERIC E
`
`TITLE:
`
`System and method for RAM power and data
`backup utilizing a capacitor and ROM
`
`APPLICATION
`NO:
`FILED:
`ISSUED:
`
`US1994322808A
`
`13 OCT 1994
`04 MAR 1997
`
`COMPILED:
`
`13 JUN 2022
`
`Petitioner Intel Corp., Ex. 1015
`IPR2023-00783, Pg. 2
`
`

`

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`NUMER/d4'U
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`PATENT DATE
`nR419
`
`PATEN
`NUMBER
`
`SERIAL NUMBER
`08:/322, 8038
`
`FILING DATE CLASS
`10/13/94
`365
`
`SUBCLASS
`
`GROUP ART UNIT
`
`EXAMINER
`
`:2511
`
`KELLY -J. REASONER, FT.. 1tOLLINS, CO; ERIC E. WILLIAMS, FT. COLLINS, CO.
`
`**CONTII\JIIN DA ******
`P).
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`
`**FORitEeIGN/PCTAPP$LI9WTIONS******
`VERIFIED
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`
`FOREIGN FILING LICENSE GR-NTED 11/20/94
`
`VerifiedandAcknowledged
`
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`
`U.S. DEPT. of COMM.-Pat. & TM Office-PTO-436L (rev. 10-78)
`
`PARTS OF APPLICATION
`/t _____________________
`FILED SEPARATELY
`NOTICE OF ALLOWANCE'MAILED
`
`ISSUEFEE
`Amount Due
`DatePaid
`~eiateac
`
`Label
`Area
`
`Form PTo-438A
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`.
`Petitioner Intel Corp., Ex. 1015
`IPR2023-00783, Pg. 3
`
`

`

`5,608,684
`SYSTEM AND METHOD FOR RAM POWER AND DATA BACKUP
`UTILIZING A CAPACITOR AND ROM
`Transaction History
`Transaction Description
`Date
`12-07-1994 Application Captured on Microfilm
`02-09-1995 Case Docketed to Examiner in GAU
`03-10-1995 Case Docketed to Examiner in GAU
`03-27-1995 Restriction/Election Requirement
`04-05-1995 Mail Restriction Requirement
`05-05-1995 Response to Election / Restriction Filed
`05-09-1995 Date Forwarded to Examiner
`05-15-1995 Non-Final Rejection
`05-24-1995 Mail Non-Final Rejection
`08-14-1995 Response after Non-Final Action
`08-22-1995 Date Forwarded to Examiner
`10-20-1995 Non-Final Rejection
`10-25-1995 Mail Non-Final Rejection
`01-16-1996 Response after Non-Final Action
`01-25-1996 Date Forwarded to Examiner
`04-01-1996 Final Rejection
`04-08-1996 Mail Final Rejection (PTOL - 326)
`05-23-1996
`Interview Summary Record
`06-07-1996 Response after Final Action
`06-13-1996 Date Forwarded to Examiner
`06-21-1996 Mail Notice of Allowance
`06-21-1996 Notice of Allowance Data Verification Completed
`09-20-1996
`Issue Fee Payment Verified
`09-20-1996 Mailroom Date of Drawing(s)
`09-30-1996 Drawing(s) Received at Publications
`10-02-1996 Drawing(s) Matched to Application
`10-07-1996 Drawing(s) Processing Completed
`01-27-1997
`Issue Notification Mailed
`03-04-1997 Recordation of Patent Grant Mailed
` 
`
`Petitioner Intel Corp., Ex. 1015
`IPR2023-00783, Pg. 4
`
`

`

`08/322808
`
`GAlvo 0Pt1 R(
`PATENT APPLICATION
`
`* Date
`Entered
`or
`Counted
`
`08322808
`
`CONTENTS
`
`S1.4Rication
`
`papers..
`
`papers.
`
`APPR&8ftifJI'
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`f 0l
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`INITIALS______
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`,
`Petitioner Intel Corp., Ex. 1015
`IPR2023-00783, Pg. 5
`
`

`

`Staple Issue Slip Here
`
`ID NO.
`
`DATE
`
`314/
`
`POSITION
`CLASSIFIER
`EXAMINER
`TYPIST
`VERIFIER
`CORPSCORR.
`SPEC.HAND
`FILE MAINT.
`DRAFTING
`
`INDEX OF CLAIMS
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`1 .
`
`52
`53
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`
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`
`-
`Petitioner Intel Corp., Ex. 1015
`IPR2023-00783, Pg. 6
`
`

`

`PATENT NUMBER
`
`CLASS
`
`ORIGINAL CLASSIFICATION
`SUBCLASS.
`
`I
`
`APPLICATION SERIAL NUMBER
`0?13 o'CLASS
`
`SUBCLASS
`_____________________________________
`
`APPLICANT'S NAME (PLEASE PRINT)
`
`CROSS REFERENCE(S)
`
`__________
`
`__________
`
`(ONE SUBCLASS PER BLOCK)
`
`_
`
`_____
`
`IF REISSUE. ORIGINAL PATENT NUMBER
`
`INTERNATIONAL CLASSIFICATION
`
`/__________ _____
`
`GROUP
`ART UNIT
`
`ASSISTANT EXAMINER (PLEASE STAMPORPRINTFULLNAME)
`MARYEXAMINER(PLW
`
`u
`
`INFULLNAME)
`
`PTO 270
`(REV. 5-91)
`
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`ISSUE CLASSIFICATION SLIP GROUP 2500
`
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`
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`
`DEARMETOCOMEC
`T. DEPARTMENT OF COMMERCE
`PATET ANe TRoADEAR OFFICE
`
`Petitioner Intel Corp., Ex. 1015
`IPR2023-00783, Pg. 7
`
`

`

`SEARCHED
`Sub.
`
`Date
`
`Class
`
`Exmr.
`
`SEARCH NOTES
`
`Date
`
`Exmr.
`
`MIn
`
`IERFERENCE SEARCHED
`4>~ss
`Sub.
`Date
`Exmr./
`
`(RIGHTOUTSIDE)
`
`Petitioner Intel Corp., Ex. 1015
`IPR2023-00783, Pg. 8
`
`

`

`PUTRI
`
`Petitioner Intel Corp., Ex. 1015
`IPR2023-00783, Pg. 9
`
`Petitioner Intel Corp., Ex. 1015
`IPR2023-00783, Pg. 9
`
`

`

`United States Patent [19]
`Reasoner et al.
`
`[54] SYSTEM AND METHOD FOR RAM POWER
`AND DATA BACKUP UTILIZING A
`CAPACITOR AND ROM
`
`[75]
`
`Inventors: Kelly J. Reasoner; Eric E. Williams,
`both of Ft. Collins, Colo.
`
`[73] Assignee: Hewlett-Packard Company, Palo Alto,
`Calif.
`
`[21] Appl. No.: 322,808
`
`[22] Filed:
`Oct. 13, 1994
`. . . . . . . . . . . . . . . . . G C7/00
`Int. Cl.6
`[51]
`[52] U.S. Cl. .......................... 365/228; 365/149; 365/154;
`365/226
`[58] Field of Search .....................................
`365/226, 102,
`365/149, 222, 228, 154
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`9/1982 Sasayama et al. .................. 365/228 X
`4,348,729
`4,399,524
`8/1983 Muguruma et al.
`................ 365/228 X
`4,874,960 10/1989 Cybela ......................................
`307/64
`5,175,842 12/1992 Totani
`.................................
`365/228 X
`5,206,938
`4/1993 Fujioka ............. 365/228 X
`5,243,577
`9/1993 Ueda et al.
`.........................
`365/228 X
`5,375,246 12/1994 Kimura et al. ...................... 365/226 X
`
`105 DA
`
`TA BUS (HI)
`
`1111111111111I111111111111111111111111111111111111111111111111111111llIll
`
`US005608684A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,608,684
`Mar. 4, 1997
`
`OTHER PUBLICATIONS
`
`NEC Document No. CEP-1004G, "Supercap" User's
`Manual, published Jun. 1992.
`
`Primary Examiner-Do Hyun Yoo
`
`ABSTRACT
`[57]
`A system and method for permanently backing up RAM
`memory devices. The present invention utilizes a capacitor
`as a primary backup device for supplying the necessary
`backup power for power fluctuations, power interruptions,
`and other short-duration power failures. The present inven-
`tion also utilizes a ROM as a secondary backup device for
`backing up and restoring valid RAM data when the duration
`of power loss is greater than that for which the capacitor can
`supply backup power. Thus, the integrity of RAM data is
`guaranteed for all types of power fluctuations, interruptions,
`and failures. The ROM includes two storage areas for
`separately storing two copies of RAM data. The processor
`first determines whether the data stored in the RAM is valid.
`If the present RAM data is valid, the processor backs up the
`present RAM data by replacing the oldest or invalid copy in
`the ROM with the present RAM data. If the present RAM
`data is not valid, the processor restores the RAM data with
`the most recent valid data previously stored in the ROM.
`
`4 Claims, 4 Drawing Sheets
`
`,--102
`
`PROCESSOR
`BACKUP
`
`8.
`
`DATA
`103
`
`16
`
`I
`
`FLASH
`ROM
`(HI)
`104
`
`|
`I
`
`114
`:116:
`
`STATIC
`RAM
`
`108
`
`ELEC!ELCRICAL POWER
`120
`
`122
`128
`124
`
`132
`132
`
`6
`
`RESTORE
`IL36J
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`4DDRSS
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`17
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`106
`
`110
`
`8"
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`107 DATA BUS (LO)
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`I
`
`130
`
`]2
`
`100
`
`Petitioner Intel Corp., Ex. 1015
`IPR2023-00783, Pg. 10
`
`

`

`U.S. Patent
`
`Mar. 4, 1997
`
`Sheet 1 of 4
`
`5,608,684
`
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`Petitioner Intel Corp., Ex. 1015
`IPR2023-00783, Pg. 11
`
`

`

`U.S. Patent
`
`Mar. 4, 1997
`
`Sheet 2 of 4
`
`5,608,684
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`Petitioner Intel Corp., Ex. 1015
`IPR2023-00783, Pg. 12
`
`

`

`U.S. Patent
`
`Mar. 4, 1997
`
`Sheet 3of 4
`
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`Petitioner Intel Corp., Ex. 1015
`IPR2023-00783, Pg. 13
`
`

`

`U.S. Patent
`
`Mar. 4, 1997
`
`Sheet 4 of 4
`
`5,608,684
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`Petitioner Intel Corp., Ex. 1015
`IPR2023-00783, Pg. 14
`
`

`

`1
`SYSTEM AND METHOD FOR RAM POWER
`AND DATA BACKUP UTILIZING A
`CAPACITOR AND ROM
`
`5,608,684
`
`20
`
`5
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates generally to maintaining a
`supply of electrical power to electronic components nor-
`mally furnished from a line supply of electrical power, and 10
`more particularly, to maintaining data stored in volatile
`memory components for which electrical power has been
`interrupted or lost.
`2. Related Art
`Volatile memory components such as a random access 15
`memory (RAM) must receive electrical power continuously
`to maintain the information stored in their memory cells.
`The bit content of the memory is typically lost whether
`electric power to the RAM is momentarily interrupted,
`fluctuates, or is lost.
`There are many situations where backup power is
`required to maintain data in RAM. For example, service
`interruptions to the line source of power by natural phenom-
`enon, operational problems in the power system, etc. These
`conditions generally result in a power interruption for a short
`period of time, perhaps one hour or less. Power backup is
`also required for momentary power fluctuations which may
`occur when, for example, heavy loads such as motors,
`buzzers, or displays are driven. Under such conditions, the
`backup power source is necessary to maintain a stable
`source of power. Other situations include providing backup
`power when the primary power source is turned off. Under
`these conditions, backup power may be required for an
`extended period of time, such as one month.
`Recently, various approaches have been taken towards
`providing power backup capability to RAMs to achieve a
`nonvolatile memory, isolated from the above power inter-
`ruptions and fluctuations. One of the more common backup
`power supply arrangements has been to combine a RAM
`with a dedicated backup battery. Some of these battery
`backup devices also include a circuit which senses power
`supply voltage. If this voltage drops below a predetermined
`battery voltage level, the circuit switches the RAM from
`receiving power from the line source of power to receiving 45
`power from the backup battery. These circuits generally
`allow current to be drawn from the battery only in the event
`of a loss of AC power.
`There are a number of problems with
`the above
`approaches. First, the circuits normally exhibit a time delay 50
`before the backup battery is connected to the RAM. This
`time delay is a result of the turn-on time of the transistors in
`the circuit. While the delay time is relatively short, the RAM
`can be exposed to a low supply voltage condition before the
`battery is connected. This exposure to low supply voltage 55
`may cause a loss of data. Some systems have incorporated
`a capacitor to supply a temporary source of power to the
`RAM during the switching of power from line voltage to
`battery.
`Another disadvantage of a battery backup power supply is 60
`that the charge remaining in nonrechargeable batteries to
`handle a power outage of unknown duration are difficult to
`determine. In addition, rechargeable batteries must have a
`controlled charge rate to limit current to the battery, and
`periodically requires replacement. This increases the main-65
`tenance cost of the system. In addition, the capacitor can
`supply the necessary voltage for only a limited period of
`
`2
`time. Thus, there may be a loss of data should the battery not
`be replaced at the proper time or is defective for a period
`longer than the discharge time of the capacitor.
`Another disadvantage of battery backup systems relates to
`the environmental concerns of used battery disposal. Battery
`backup systems require the implementation of procedures
`for removing and discharging the battery prior to disposal.
`Although the use of a capacitor alone to provide backup
`power would alleviate this environmental problem, capaci-
`tors can supply power for only a relatively short period of
`time, making them ineffective as a long term backup power
`source.
`What is needed, therefore, is a means for backing up
`volatile memory devices for long periods of time without
`incurring the problems associated with the use of batteries.
`
`SUMMARY OF THE INVENTION
`
`The present invention is system and method for indefi-
`nitely backing up RAM memory devices. The present inven-
`tion utilizes a capacitor as the primary backup device for
`supplying the necessary backup power for power fluctua-
`tions, power interruptions, and other short-duration power
`failures. The present invention utilizes a ROM as a second-
`ary backup device for backing up and replacing valid RAM
`data when the loss of line power supply is of a duration
`greater than that for which the capacitor can supply backup
`power. Thus, the present invention guarantees the integrity
`of RAM data for all types of primary power fluctuations,
`interruptions, and failures.
`More specifically, the present invention includes a RAM
`configured to store binary data, a capacitor configured to
`provide the RAM with a voltage for a first period of time
`sufficient for the RAM to maintain the data stored in its
`memory cells, a ROM configured to store multiple backup
`copies of RAM dam, and a processor for controlling the data
`transfers and copies stored in the RAM and ROM.
`The processor first determines if the data presently stored
`in the RAM is valid. Typically, the RAM data is valid unless
`the line source power supply has been unavailable for a time
`which is greater than a discharge time of the capacitor. If the
`data stored in the RAM is valid, the processor backs up
`(copies) the RAM data to ROM. The ROM includes two
`storage areas for storing copies of RAM data. In the back up
`process of the present invention, the processor determines
`which of the copies of RAM data is the most recent and valid
`copy. The processor then replaces the older or invalid copy
`with the data presently stored in the RAM. If the RAM data
`is not valid, the processor restores the RAM data with the
`most recent valid data previously stored in the ROM. This
`restoring process includes first determining which copy of
`RAM data stored in ROM is the most recent valid copy.
`Then the processor replaces the corrupted data stored in the
`RAM with the most recent valid copy of RAM data stored
`SinROM.
`One advantage of the present invention is that it com-
`pletely eliminates the use of a battery as a source of backup
`power to volatile RAM.
`Another advantage of the present invention is that it uses
`a capacitor to provide relatively short term backup power.
`This enables the present invention to respond quickly to
`power interruptions. In addition, the capacitor protects
`against power fluctuations, thereby achieving greater circuit
`stability.
`Another advantage of the present invention is that it
`utilizes an extremely high capacitance capacitor in conjunc-
`
`Petitioner Intel Corp., Ex. 1015
`IPR2023-00783, Pg. 15
`
`

`

`3
`tion with a ROM data backup system. The ROM provides
`long term data backup power for conditions in which the
`capacitor cannot maintain the necessary voltage output. The
`use of a high capacitance capacitor with a RAM enables the
`ROM to be used only in the rare circumstances wherein the 5
`power is removed from the system for long periods of time.
`This results in the ROM not being written to often, thereby
`preserving the ROM and enabling the present invention to
`guarantee RAM data indefinitely.
`Further features and advantages of the present invention10
`as well as the structure and operation of various embodi-
`ments of the present invention are described in detail below
`with reference to the accompanying drawings. In the draw-
`ings, like reference numbers indicate identical or function-
`ally similar elements. Additionally, the left-most digit of a15
`reference number identifies the drawings in which the ref-
`erence number first appears.
`
`20
`
`BRIEF DESCRIPTION OF THE FIGURES
`The invention is best understood by reference to the
`Figures wherein references with like reference numbers
`indicate identical or functionally similar elements. In addi-
`tion, the left-most digits refer to the figure in which the
`reference first appears in the accompanying drawings in25
`which:
`FIG. 1 is a circuit block diagram of a preferred embodi-
`ment of the RAM power and data backup system of the
`present invention;
`FIG. 2 is a high level flowchart of the operation of the30
`RAM data backup process of the present invention;
`FIG. 3 is a flowchart of the portion of the RAM data
`backup process which copies valid RAM data to ROM; and
`FIG. 4 is a flowchart of the portion of the RAM data
`backup process which copies previously stored RAM data
`from ROM back to RAM to replace data which has been
`found to be invalid.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`40
`
`I. Introduction
`
`The present invention is a system and method for perma-
`nently backing up RAM memory devices. The present4
`invention utilizes a capacitor as a primary backup device for
`supplying the necessary backup power for power fluctua-
`tions, power interruptions, and short-duration power fail-
`ures. The present invention utilizes a ROM as a secondary
`backup device for backing up valid RAM data and replacing50
`invalid RAM data. For instance, when the loss of line source
`power is for a time greater than that for which the capacitor
`can supply backup power, RAM data will be lost. Thus, the
`present invention guarantees the integrity of RAM data for
`all types of line source power fluctuations, interruptions, and5
`failures.
`
`H. System Architecture
`FIG. 1 illustrates a circuit block diagram of a preferred60
`embodiment of the memory backup system of the present
`invention. Referring now to FIG. 1, a memory backup
`system 100 of the present invention principally comprises a
`processor 102, a ROM 114, a RAM 116, a capacitor 112, and
`a power supply circuit 132. These components work in65
`conjunction with each other to permanently maintain and
`backup data stored in RAM 116.
`
`5,608,684
`
`4
`As will be discussed in detail below, ROM 114 consists of
`two separate ROM devices 104 and 106 to accommodate the
`multiple "flash copy" approach of the present invention. The
`two ROM devices 104 and 106 are addressed by processor
`102 via address bus 101. Address bus 101 has 17 address
`lines, all of which are used to address ROM device 104 and
`ROM device 106. Processor 102 transfers data to and from
`ROM 114 over data bus 103. Data bus 103 has 16 data lines
`as illustrated in FIG. 1. The 16 data lines of data bus 103 are
`divided into 8 high order data lines, represented by high data
`bus 105, and 8 low order data lines, represented by low data
`bus 107. The 8 high order data lines are used to transfer data
`to and from ROM device 104. The 8 low order data lines are
`used to transfer data to and from ROM 106.
`RAM 116 interfaces with processor 102 in a manner
`similar to ROM 114. RAM 116 consists of two separate
`RAM devices 108 and 110. However, as will be discussed in
`detail below, this division of RAM 116 is of little conse-
`quence in the present invention. In any event, the two RAM
`devices 108 and 110 are addressed via 16 of the 17 address
`lines of address bus 101. Processor 102 and RAM device
`108 transfer data over high data bus 105. Processor 102 and
`RAM device 110 transfer data over low data bus 107.
`RAM 116 receivespower from a line power source 120
`through power supply circuit 132. In the preferred embodi-
`ment of the present invention, RAM devices 108 and 110 are
`complimentary metal oxide silicon (CMOS) random access
`memory (RAM) components. These CMOS RAM compo-
`nents operate at 5 volts and retain stored information for
`extended periods of time at voltages down to 2 volts. Line
`power source 120 is a 12 volt source of power. Power supply
`circuit 132 receives the 12 volt line power, and converts that
`12 volt power to 5 volts. Power supply 120 provides power
`to RAM 116 through resistor 122 and diode 124. A zener
`diode 126 is coupled to the power source side of diode 124.
`Zener diode 126 is employed as a voltage reference, main-
`taining a voltage of 5.6 volts at junction 128. Since the
`voltage drop across diode 124 is 0.6 volts, the voltage at
`junction 130 is maintained at 5 volts. Resistor 122, diode
`124, and zener diode 126 are collectively and generally
`referred to as power supply circuit 132. The preferred
`embodiment of the present invention is implemented in a
`system having a 12 volt line voltage. Thus, power supply
`circuit 132 is directed towards reducing the 12 volt line
`voltage to the 5 volts required by CMOS RAM devices 108
`and 110. However, as one skilled in the relevant art would
`find apparent, the configuration of power supply circuit 132
`depends upon supply 120 and the power requirements of
`RAM 116, and may accordingly take on different configu-
`rations.
`Coupled to power supply circuit 132 and RAM 116 at
`junction 130 is a capacitor 112. Capacitor 112 is charged by
`voltage source 120 through resistor 122 and diode 124.
`Capacitor 112 discharges when the voltage at junction 130
`drops below 5 volts. Diode 124 prevents the charge stored in
`capacitor 112 from flowing to voltage source 120 when
`discharging to drive the remaining portions of the system
`(not shown). Thus, capacitor 112 supplies power only to
`RAM 116.
`Further details regarding
`the system architecture and
`components are discussed with respect to the operation of
`the present invention. As introduced above, the present
`invention provides both power backup as well as data
`backup for RAM 116. Each of these processes and associ-
`ated components are discussed below.
`A. Power Backup Components
`The components associated with the power backup fea-
`ture of the present invention are now described in further
`
`Petitioner Intel Corp., Ex. 1015
`IPR2023-00783, Pg. 16
`
`

`

`5
`detail. These components include power supply circuit 132
`and capacitor 112.
`As described above, normal line power is supplied by line
`source power supply 120 through power supply circuit 132.
`In addition, power supply 120 simultaneously charges 5
`capacitor 112 while providing power to RAM 116. In the
`event of a loss or interruption of normal line power at line
`source 120, capacitor 112 will discharge to supply the
`necessary voltage to enable RAM 116 to maintain data
`stored in its memory cells.
`As introduced above and discussed in detail below, the
`power backup feature of the present invention is utilized in
`conjunction with a ROM. However, the ROM components
`cannot be written too often (also discussed below). Thus, it
`is desired for capacitor 112 to have the capability to maintain15
`the necessary voltage at junction 130 for RAM 116 to
`maintain the stored data for as long as possible.
`In the preferred embodiment of the present invention,
`capacitor 112 is a 0.22F SUPERCAP, available from NEC
`Electronics, Inc., Mountain View, Calif., U.S.A. Due to its20
`large capacity of 0.22F, capacitor 112 has a discharge time
`of a minimum of 10 days when supplying power to CMOS
`RAM 116. Thus, when there is a power interruption or
`failure for 10 or more days, capacitor 112 will supply the
`necessary power to preserve data in RAM 116, and ROM25
`114 will not have to utilized. Further details regarding the
`NEC SUPERCAP capacitor 112 may be found in SUPER-
`CAP User Manual, Document No. DEP-10046 (also avail-
`able from NEC Electronics, Inc., Mountain View, Calif.,
`U.S.A.), herein incorporated by reference in its entirety.
`As introduced above, in the preferred embodiment of the
`present invention, capacitor 112 is a 0.22F SUPERCAP
`available from NEC. However, as one skilled in the relevant
`art would find apparent, any high capacitance capacitor may
`be used which is compatible with the anticipated duration of35
`power interruptions which may occur. If the capacitance of
`capacitor 112 is too low, then ROM 114 will be utilized more
`often. Thus, if there are few long-term power interruptions,
`ROM 116 will still not be utilized often.
`B. Data Backup Components
`The system components directed to the backup and res-
`toration of valid RAM data are now discussed. In particular,
`ROM 114 with ROM device 104 and ROM device 106 are
`provided to store copies of valid RAM data in the event that
`power is removed for a time greater than that for which45
`capacitor 112 can supply backup power. The copying of
`RAM data and the transferring of data between processor
`102 and RAM 116 and ROM 114 is performed by processor
`102. More specifically, there are two functional components
`of processor 102 associated with the present invention: a50
`backup subprocessor 134 and a restoration subprocessor
`136. Backup subprocessor 134 backs up valid RAM data by
`copying it to ROM. A restoration subprocessor 136 restores
`RAM data which was previously backed up by backup
`subprocessor 134 to replace corrupted data stored in RAM55
`116.
`As introduced above, ROM 114 is comprised of two ROM
`devices 104 and 106. Each of these are configured to store
`a copy of RAM data, referred to as a "flash copy." Thus, in
`the preferred embodiment, two copies of RAM data are60
`maintained in ROM 114.
`ROM 114, like all read-only memory components, is
`limited in the number of write cycles that it can support. This
`is typically on the order of a hundred thousand times. Thus,
`to extend the life of ROM 114, the present invention writes65
`RAM data to ROM only at particular times and under certain
`conditions. Specifically, RAM data is copied to ROM 114 at
`
`30
`
`40
`
`5,608,684
`
`10
`
`6
`power up when the validity of the RAM data has been
`verified. One copy is the latest copy of RAM data as of the
`time that the system receives line power from line source
`power supply 120. The other copy is an older version of
`RAM data which is held for the unlikely event of a power
`interruption during the copying of data into ROM 114.
`Under such conditions, the more recent backup copy which
`was in the process of being copied to ROM 114 may have
`become corrupted or may be incomplete. The flash copy
`which is the older version of RAM data may then be used as
`a backup copy.
`In the preferred embodiment of the present invention,
`flash ROM devices 104 and 106 are Intel 28F01BX-T/-B
`CMOS Flash Memory, available from Intel Corp., Santa
`Clara, Calif., U.S.A. CMOS flash ROM device 104 and
`CMOS flash ROM device 106 are nonvolatile flash memory
`comprised of four separately erasable blocks. In addition,
`each block is capable of being reprogrammed separately to
`ensure data integrity. The blocking scheme allows logical
`segmentation of the embedded software, with an 8 Kbyte
`block for boot code, a 112 Kbyte block and a 4 Kbyte block,
`combined to store the code associated with backup subpro-
`cess 134 and restore subprocess 136, and another 4 Kbyte
`block for storing critical data. In the preferred embodiment
`of the present invention, the critical data is parametric data,
`such as odometers, configurations, and identify bits. Thus,
`ROM 114 is capable of separately storing two copies of
`RAM data, one in CMOS flash ROM device 104 and one in
`CMOS flash ROM device 106. However, as one skilled in
`the relevant art would find apparent, other types ofread only
`memory may be used which have the capability of sepa-
`rately storing multiple copies of RAM data.
`ROM devices 104 and 106 also comprise a powerdown
`mode to lock out erase or write operations during system
`power up or power loss to provide absolute data protection.
`Thus, after an initial powerup or after return from a long-
`term powerdown situation, ROM devices 104 and 106
`function as standard read only memories. In addition, the
`blocking scheme of ROM devices 104 and 106 allows
`updates in the main and parameter blocks while providing
`recovery code in a boot block in the unlikely event of a
`power failure during update. Further features of ROM 114
`may be found in Intel product literature for Pat. No.
`28F001BX-T/28F001BX-B IM (128K X 8) CMOS FLASH
`MEMORY, order no. 290406-002, available from Intel Cor-
`poration, Santa Clara, Calif., U.S.A.
`In the preferred embodiment of the present invention,
`processor 102 is 68000 series Motorolla processor. How-
`ever, as one skilled in the relevant art would find apparent,
`any other processor may be used which is configured to
`interface with ROM 114 and RAM 116 and which can
`perform the processing described below.
`
`I. Data Backup Operation
`FIGS. 2 through 4 are a flowchart of the RAM data
`backup and restoration process of the present invention.
`Referring to FIGS. 2-4, a preferred embodiment of the
`RAM data backup and restoration process is now discussed.
`The RAM data backup and restoration process 200 is
`invoked at start 202 when the system in which the present
`invention is implemented initially receives power.
`First, in step 204, RAM 116 is verified to determine if it
`is corrupted. In the preferred embodiment of the present
`invention, this verification of the RAM data is accomplished
`by invoking a well known checksum operation. However, as
`one skilled in the relevant art would find apparent, other
`
`Petitioner Intel Corp., Ex. 1015
`IPR2023-00783, Pg. 17
`
`

`

`5,608,684
`
`5
`
`7
`memory verification procedures may be used, depending on
`the particular application. Typically, in the present invention,
`RAM 116 would only be corrupted when backup capacitor
`112 has discharged to a point beyond which it can no longer
`supply the minimum voltage of +2 volts to RAM 116.
`IfRAM 116 is not corrupt, then the RAM data backup and
`restoration process 200 continues at block 206 wherein a
`RAM backup subprocess 206 is performed. RAM backup
`subprocess 206 copies the contents of RAM 116 into ROM
`114. This process is illustrated in FIG. 3 and discussed in to
`detail below. If RAM 116 is found to be corrupted in step
`204, then processing continues at block 208 with a RAM
`restoration subprocess 208. RAM restoration subprocess
`208 replaces this invalid data by restoring RAM 116 with
`valid data which has been previously stored in ROM 114. 15
`This process is illustrated in FIG. 4 and dis