`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`__________________________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`__________________________
`
`
`INTEL CORPORATION,
`Petitioner
`v.
`BiTMICRO LLC,
`Patent Owner.
`
`
`___________________
`
`IPR2023-00783
`U.S. Patent No. 6,496,939
`_____________________
`
`
`DECLARATION OF DR. CARL SECHEN, PH.D.
`IN SUPPORT OF INTER PARTES REVIEW OF U.S. 6,496,939
`
`Petitioner Intel Corp., Ex. 1003
`IPR2023-00783
`
`

`

`TABLE OF CONTENTS
`Introduction ...................................................................................................... 1
`
`I.
`
`A. Qualifications and Expertise ........................................................................ 3
`B. Compensation .............................................................................................. 6
`C. Materials Considered and Basis of Opinions .............................................. 6
`D. Understanding of Relevant Legal Principles ............................................... 8
`The ’939 Patent .............................................................................................. 10
`
`II.
`
`A. Technical Background ............................................................................... 11
`1. Computer Memory System Overview ............................................. 11
`2. Types of Semiconductor Memory ................................................... 15
`3. Protecting Data During a Power Outage ......................................... 18
`4. Backup Power Supplies ................................................................... 21
`5. Capacitors as Backup Power Supplies ............................................ 22
`6. Power Monitoring and Management Circuitry ............................... 37
`B. ’939 Patent Summary................................................................................. 39
`1. Overview of the Specification ......................................................... 39
`2. The ’939 Patent’s Modes of Operation ........................................... 41
`3. The ’939 Patent’s Backup Power Supply Structure ........................ 43
`C. Prosecution History .................................................................................... 46
`D. Level of Ordinary Skill in the Art ............................................................. 48
`E. Claim Construction .................................................................................... 49
`1.
`“means for activating” (claim 10) ................................................... 50
`2.
`“means for reconfiguring” (claim 10) ............................................. 50
`3.
`“means for deactivating” (claim 10) ............................................... 51
`4.
`“means for allowing” (claim 12) ..................................................... 52
`5.
`“means for reversing” (claim 15) .................................................... 52
`
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`Petitioner Intel Corp., Ex. 1003
`IPR2023-00783
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`

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`U.S. Patent 6,496,939
`IPR2023-00783
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`“means for discharging” (claim 15) ................................................ 53
`6.
`III. Claims 1-3, and 6 would have been obvious over the combination of Nishida
`
`and Nakao (including in further combination with Harari) ........................... 54
`
`IV. Claims 1-3, 6, 10-12, and 15 would have been obvious over the combination
`
`of Nishida, Ergott, and Pilukaitis (including in further combination with
`
`Harari) ..........................................................................................................109
`
`V.
`
`Claims 10-12 and 15 would have been obvious over the combination of
`
`Nishida, Harari, Ergott, Pilukaitis, and Nakamura ......................................174
`
`VI. Combinations based on Supercap Manual ..................................................192
`
`VII. Conclusion ...................................................................................................198
`
`
`
`
`
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`Petitioner Intel Corp., Ex. 1003
`IPR2023-00783
`
`

`

`I.
`
`Introduction
` My name is Carl Sechen, and I have been retained by Perkins Coie
`
`LLP on behalf of Intel Corporation (“Intel” or “Petitioner”), to provide this
`
`Declaration concerning technical subject matter relevant to the petition for Inter
`
`Partes Review (“Petition”) of U.S. Pat. No. 6,496,939 to Portman (“the ’939
`
`patent”). It is my understanding that the ’939 patent is currently assigned to
`
`BiTMICRO LLC (“BiTMICRO” or “Patent Owner”).
`
`
`
`I am over 18 years of age. I have personal knowledge of the facts
`
`stated in this Declaration and could testify competently to them if asked to do so.
`
`
`
`I have reviewed and am familiar with the specification and the claims
`
`of the ’939 patent. In general, I will cite to the specification of a United States
`
`patent using the following formats: (Patent No., Col:Line Number(s)) or (Patent
`
`No., Paragraph Number(s)). For example, the citation (’939 patent, 1:1-10
`
`(INTEL-1001)) points to the ’939 patent specification at column 1, lines 1-10.
`
`Also, for convenience, I use italics to denote limitations from the challenged
`
`claims, which are claims 1-3, 6, 10-12, and 15.
`
`
`
`All of the opinions contained in this Declaration are based on the
`
`documents I reviewed and my knowledge and professional judgment. In forming
`
`the opinions expressed in this Declaration, I reviewed the documents listed in the
`
`Exhibit list of Attachment A to this Declaration. I have also reviewed and am
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`1
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`Petitioner Intel Corp., Ex. 1003
`IPR2023-00783
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`

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`familiar with the other materials referred to in this Declaration. To the best of my
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`U.S. Patent 6,496,939
`IPR2023-00783
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`knowledge, the documents listed above are true and accurate copies of what they
`
`purport to be and are the kinds of materials that an individual with expertise in this
`
`field at the relevant time period would reasonably rely on in formulating opinions,
`
`such as those set forth in this Declaration. In citing documents below, I have added
`
`emphasis to some words and phrases. Unless stated otherwise, I added any
`
`emphasis that appears in the quotations.
`
`
`
`I have been asked to provide my technical opinions regarding how a
`
`person of ordinary skill in the art (“POSITA”) would have understood the claims
`
`of the ’939 patent at the time of the alleged invention. For purposes of whether the
`
`teachings of the prior art render the claims of the ’939 patent obvious, I have been
`
`asked to use September 21, 1999, the filing date of the ’939 patent for the analysis
`
`in this Declaration. I have also been asked to provide my technical opinions on
`
`how concepts in the ’939 patent specification relate to claim limitations of the ’939
`
`patent. In reaching the opinions provided herein, I have considered the ’939 patent,
`
`its prosecution history, and the references cited above and have drawn as
`
`appropriate on my own education, training, research, knowledge, and personal and
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`professional experience.
`
`2
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`Petitioner Intel Corp., Ex. 1003
`IPR2023-00783
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`

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`A. Qualifications and Expertise
`In formulating my opinions, I have relied on my knowledge, training,
`
`
`U.S. Patent 6,496,939
`IPR2023-00783
`
`
`and experience in the relevant field, which I will summarize briefly. A more
`
`detailed summary of my background, education, experience, and publications is set
`
`forth in my curriculum vitae (“CV”), which is provided as exhibit INTEL-1004.
`
`My CV also includes a list of my litigation support experience.
`
`
`
`I earned a B.E.E. in Electrical Engineering from the University of
`
`Minnesota in 1975, followed by a M.S. in Electrical Engineering from the
`
`Massachusetts Institute of Technology in 1977. I earned a Ph.D. in Electrical
`
`Engineering from the University of California, Berkeley in 1986.
`
`
`
`I have been a Professor of Electrical Engineering for 36 years. Since
`
`August 15, 2005, I have been a Professor of Electrical and Computer Engineering
`
`at the University of Texas at Dallas. From July 1992 to August 14, 2005, I served
`
`as a Professor of Electrical Engineering at the University of Washington. From
`
`July 1986 through June 1992, I served as an Assistant Professor and then an
`
`Associate Professor of Electrical Engineering at Yale University.
`
`
`
`Over the course of my academic career, my research has focused on
`
`the design and computer-aided design of digital integrated circuits, including
`
`computer architecture, and the design of dynamic random-access memory
`
`(“DRAM”) and static random-access memory (“SRAM”) modules. I also have
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`3
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`IPR2023-00783
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`designed several chips that included various types of embedded DRAM
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`U.S. Patent 6,496,939
`IPR2023-00783
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`(“eDRAM”). In this research work, I have designed multiple sense amplifier
`
`circuits for the various DRAMs, eDRAMs, and SRAMs. I have authored or co-
`
`authored over 200 papers and one book, the majority of which concern digital
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`integrated circuit design and memory design.
`
` During my undergraduate education at Minnesota and my master’s
`
`degree work at MIT, I fabricated multiple fully-functional semiconductor circuits. I
`
`designed and fabricated circuits comprising depletion mode transistors that
`
`included buried-channels and buried layers. I also designed and fabricated circuits
`
`comprising enhancement mode (or surface channel) transistors in this work.
`
` As a professor, I have developed and taught numerous courses,
`
`including several courses that teach Very Large Scale Integration (“VLSI”) circuit
`
`design, computer architecture and memory design, as well as analog and mixed
`
`signal IC design. I have taught these courses continuously for the past 27 years. I
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`have taught digital integrated circuit design and memory design to undergraduate
`
`and graduate students at the University of Washington and at the University of
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`Texas at Dallas. The design and use of SRAM, DRAM and Flash memories are
`
`covered in these courses, as is the design of sense amplifier circuits for various
`
`types of memory. In these courses I teach the details of the structures and functions
`
`of computer systems and the use of digital tools to design memory circuits. Also
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`4
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`covered are the design of basic power management circuits. I have designed power
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`U.S. Patent 6,496,939
`IPR2023-00783
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`management circuits for several research projects.
`
`
`
`In 2002, I was elected a Fellow of the Institute of Electrical and
`
`Electronics Engineers (“IEEE”) for contributions to placement and routing of
`
`application-specific integrated circuits. IEEE is the leading professional association
`
`for electrical engineers. The Board of Directors of the IEEE awards the rank of
`
`“Fellow” to individuals with an extraordinary record of accomplishments in any of
`
`the IEEE fields of interest. The total number of IEEE members who can be named
`
`Fellows in any one year cannot exceed one-tenth of one percent of the total voting
`
`IEEE membership.
`
`
`
`I received several research and teaching awards during my career. I
`
`received the Semiconductor Research Corporation’s Inventor’s Recognition Award
`
`in 1988 and in 2001. I also received the Technical Excellence Award from the
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`Semiconductor Research Corporation in 1994. While serving as a Professor at the
`
`University of Washington, I received the Outstanding Research Advisor Award
`
`from the Department of Electrical Engineering in 2002. In 2008, I received the
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`Distinguished Teacher of the Year Award from the Department of Electrical
`
`Engineering at the University of Texas at Dallas. I also received the Distinguished
`
`Teaching Award for the Erik Johnson School of Engineering and Computer
`
`Science in 2014.
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`5
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` Over the years, I also have received extensive funding to conduct
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`U.S. Patent 6,496,939
`IPR2023-00783
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`research in computer circuits and memory designs, including area-efficient and
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`reliable eDRAM and SRAM design. Together with my graduate students, I have
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`designed and fabricated various types of computational VLSI chips.
`
`
`
`I am the lead inventor on four issued patents. Three of the patents
`
`concern extremely dense transistor-level field programmable logic.
`
`B. Compensation
`I am being compensated for my time in connection with this inter
`
`
`partes review (“IPR”) proceeding at my standard consulting rate of $400 an hour. I
`
`am also being reimbursed for expenses that I incur during the course of this work.
`
`My compensation is not contingent upon the results of my study and analysis, the
`
`substance of my opinions, or the outcome of any proceeding involving the
`
`challenged claims. I have no financial interest in the outcome of this matter of in
`
`any litigation involving the ’939 patent.
`
`C. Materials Considered and Basis of Opinions
`In forming the opinions set forth in this Declaration, I have considered
`
`
`and relied upon my education, experience, and knowledge of the relevant fields. I
`
`have also reviewed and considered the documents and materials cited in the body,
`
`including exhibits in the IPR such as the ’939 patent and its file history.
`
`6
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`Petitioner Intel Corp., Ex. 1003
`IPR2023-00783
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`

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`U.S. Patent 6,496,939
`IPR2023-00783
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`In forming the opinions set forth in this Declaration, I have considered
`
`
`
`and relied upon my education, experience, and knowledge of the relevant fields. I
`
`have also reviewed and considered the documents, schematics, and publicly
`
`available articles and books cited in the body and exhibits to this Declaration.
`
`
`
`I reserve the right to supplement this Declaration and rely upon any
`
`additional information, deposition testimony, documents, or materials that may be
`
`provided to me or that are relied upon by any of Patent Owner’s experts or
`
`witnesses.
`
`
`
`I also reserve my right to supplement this Declaration and rely upon
`
`additional information that becomes available to me.
`
`
`
`I may rely on visual aids and demonstratives to demonstrate the bases
`
`of my opinions, such as claim charts, patent drawings, excerpts from patent
`
`specifications, file histories, interrogatory responses, deposition transcripts and
`
`exhibits, as well as charts, diagrams, videos and animated or computer-generated
`
`video. The demonstrative exhibits I may use to accompany any testimony I may
`
`give may also include documents, testimony, and other evidence cited in my
`
`Declaration, portions of such evidence, and other portions of my Declaration and
`
`the attached exhibits.
`
`7
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`Petitioner Intel Corp., Ex. 1003
`IPR2023-00783
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`D. Understanding of Relevant Legal Principles
`I am not a lawyer and will not provide any legal opinions. Although I
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`U.S. Patent 6,496,939
`IPR2023-00783
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`am not a lawyer, I have been advised that certain legal standards are to be applied
`
`by technical experts in forming opinions regarding the meaning and validity of
`
`patent claims.
`
`
`
`I understand that a patent claim is invalid if it is anticipated or obvious
`
`in view of the prior art, and that a claim can be unpatentable even if all of the
`
`requirements of the claim cannot be found in a single prior-art reference. I further
`
`understand that invalidity of a claim requires that the claim be anticipated or
`
`obvious from the perspective of a person of ordinary skill in the art at the time the
`
`invention was made.
`
`
`
`I have been informed that a patent claim is invalid if it would have
`
`been obvious to a person of ordinary skill in the art. In analyzing the obviousness
`
`of a claim, I understand the following factors may be taken into account: (1) the
`
`scope and content of the prior art; (2) the differences between the prior art and the
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`claims; (3) the level of ordinary skill in the art; and (4) any so called “secondary
`
`considerations” of non-obviousness if they are present. Such secondary
`
`considerations include: commercial success of products covered by the patent
`
`claims; a long-felt need for the invention; failed attempts by others to make the
`
`invention; copying of the invention by others in the field; unexpected results
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`8
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`achieved by the invention as compared to the closest prior art; praise of the
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`U.S. Patent 6,496,939
`IPR2023-00783
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`invention by the infringer or others in the field; the taking of licenses under the
`
`patent by others; expressions of surprise by experts and those skilled in the art at
`
`the making of the invention; and the patentee proceeded contrary to the accepted
`
`wisdom of the prior art. I am not aware of any evidence of secondary
`
`considerations of non-obviousness relevant to the ’939 patent. I reserve the right to
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`supplement this Declaration if Patent Owner introduces evidence of secondary
`
`considerations of non-obviousness.
`
`
`
`I understand that to prove that prior art or a combination of prior art
`
`renders a patent obvious, it is necessary to:
`
`(1)
`
`(2)
`
`(3)
`
`identify the particular references that, singly or in combination, make
`the patent obvious;
`
`specifically identify which elements of the patent claim appear in each
`of the asserted references; and
`
`explain why a person of ordinary skill in the art would have combined
`the references, and how they would have done so, to create the
`inventions claimed in the patent. I further understand that exemplary
`rationales that may support a conclusion of obviousness include:
`
`• combining prior art elements according to known methods to yield
`predictable results;
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`• simple substitution of one known element for another to obtain
`predictable results;
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`U.S. Patent 6,496,939
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`• use of known technique(s) to improve similar devices (methods or
`products) in the same way;
`
`• applying a known technique to a known device (method or product)
`ready for improvement to yield predictable results;
`
`• “obvious to try” – choosing from a finite number of identified,
`predictable solutions with a reasonable expectation of success;
`
`• known work in one field of endeavor may prompt variations of the
`work for use in either the same field or a different field based on
`design incentives or other market forces if the variations are
`predictable to a person of ordinary skill in the art; and
`
`• some teaching, suggestion, or motivating in the prior art that would
`have led a person of ordinary skill in the art to modify the prior art
`reference or to combine prior art reference teachings to arrive at the
`claimed invention.
`
`
`
`I have been informed that, in considering obviousness, hindsight
`
`reasoning derived from the patent at issue may not be used.
`
`II. The ’939 Patent
` The ’939 patent provides “a method and system for controlling data in
`
`a computer system when the computer system loses power.” (’939 patent, Abstract
`
`(INTEL-1001).) The system described in the ’939 patent “activat[es] a plurality of
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`10
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`super capacitors to supply power to the computing engine based upon power being
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`U.S. Patent 6,496,939
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`removed from the computer system and reconfiguring the data in the computing
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`engine.” (’939 patent, Abstract (INTEL-1001).) In the event of a sudden external
`
`power loss, “a user is able to correctly store large amounts of newly written and
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`modified data from the volatile memory to the non-volatile memory” or “rapidly
`
`and irretrievably erase data from the non-volatile memory automatically.” (’939
`
`patent, 2:32-43 (INTEL-1001).) In this section, I first provide a brief technical
`
`background of power storage for memory systems, a high-level overview of the
`
`’939 patent, a discussion of the prosecution history of the ’939 patent, and a
`
`discussion of claim construction.
`
`A. Technical Background
`Computer Memory System Overview
`1.
` Computer memory is a fundamental structure of a computer system:
`
`“[a]t a top level, a computer consists of CPU, memory, and I/O components, with
`
`one or more modules of each type. These components are interconnected in some
`
`fashion to achieve the basic function of the computer, which is to execute
`
`programs.” (“Computer Organization and Architecture,” 4th Edition, 1996 by
`
`Stallings (“Stallings”), 49 (INTEL-1039).) The process of executing programs
`
`involves the CPU executing “a set of instructions stored in memory.” (Stallings, 52
`
`(INTEL-1039).) “The simplest point of view” for understanding program
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`execution “is to consider instruction processing as consisting of two steps: The
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`U.S. Patent 6,496,939
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`CPU reads (fetches) instructions from memory one at a time, and it executes each
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`instruction.” (Stallings, 52 (INTEL-1039) (emphasis in original).)
`
` Computer memory provides both short-term and long-term data
`
`storage solutions for the computer system. For example, “[a] cache is an area of
`
`memory which serves as a temporary storage area for the device (such as computer
`
`memory or a disk drive).” (U.S. Pat. No. 5,519,831 (“Holzhammer”), 1:27-30
`
`(INTEL-1036).) In contrast, an erasable programmable read-only memory
`
`(EPROM) “holds its data virtually indefinitely.” (Stallings, 110 (INTEL-1039).)
`
`The design process of a computer’s memory system is guided by three major
`
`considerations: storage capacity, data access speed, and cost. A memory system
`
`designer often faces a tradeoff of those factors: faster access time requires higher
`
`cost per bit, while memories with greater storage capacity tend to have slower
`
`access time. (Stallings, 103-104 (INTEL-1039).)
`
` The solution is not to rely on a single type of memory, but to employ a
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`memory hierarchy that includes a combination of different types of memory
`
`devices. As a result, the memory component of a computer system “exhibits
`
`perhaps the widest range of type, technology, organization, performance, and cost
`
`of any feature of a computer system.” (Stallings, 100 (INTEL-1039).) Fortunately,
`
`the computer does not need to access all data at the same frequency or speed.
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`Smaller, faster, and more expensive memories are supplemented by larger, slower,
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`U.S. Patent 6,496,939
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`and less expensive memories to fulfill the different needs and access requests of
`
`the computer system. The figure below illustrates a typical memory hierarchy that
`
`shows different levels of memory devices in a computer system. (Stallings, 101
`
`(INTEL-1039).) I have annotated the figure to show that “[a]s one goes down the
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`hierarchy, the following occur: (a) decreasing cost per bit; (b) increasing storage
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`capacity; (c) increasing access time; and (d) decreasing frequency of access of the
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`memory by the processor.” (Stallings, 100 (INTEL-1039).)
`
`(Stallings, 104 (INTEL-1039).)
`
` One of the memories in the hierarchy is the main memory, which is
`
`“the principal internal memory system of the computer.” (Stallings, 107 (INTEL-
`
`
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`1039).) Main memories are often constructed using semiconductor technology.
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`“Today, the use of semiconductor chips for main memory is almost universal.”
`
`(Stallings, 109 (INTEL-1039).) The table below lists some major types of
`
`semiconductor memory used in computer systems.
`
`
`
`(Stallings, 109 (INTEL-1039).)
`
` The most basic and essential element of a semiconductor memory is
`
`the memory cell. Each memory cell can exhibit two stable states “which can be
`
`used to represent binary 1 and 0.” (Stallings, 111 (INTEL-1039).) A memory cell
`
`is “capable of being written into (at least once), to set the state” and “being read to
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`sense the state.” (Stallings, 111 (INTEL-1039).) To achieve the aforementioned
`
`functionality, a memory cell is usually equipped with “three functional terminals
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`capable of carrying an electrical signal,” including (i) a select terminal that “selects
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`a memory cell for a read or write operation”; (ii) a control terminal that “indicates
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`read or write”; and (iii) a data terminal that sets the state of the cell during a
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`writing operation or sensing the state of the cell during a reading operation.
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`U.S. Patent 6,496,939
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`(Stallings, 111 (INTEL-1039).) The figure below is an abstract illustration that
`
`depicts the operation of a memory cell.
`
`
`
`(Stallings, 111 (INTEL-1039).)
`
` Memory devices require an electrical power supply to perform
`
`these operations. For example, “both the reading and writing are accomplished
`
`through the use of electrical signals.” (Stallings, 109 (INTEL-1039).) Based on
`
`whether a memory device retains data when power is removed, memory devices
`
`can be largely divided into two types: volatile memory devices and non-volatile
`
`memory devices.
`
`2.
`
`Types of Semiconductor Memory
`Volatile Memory
`a)
` Volatile memory devices must receive continuous electrical power
`
`supply to maintain the information stored in their memory cells and would “lose
`
`stored data if the power supplying the computer is interrupted, even momentarily.”
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`(U.S. Pat. No. 4,559,616 (“Bruder”), 1:23-25 (INTEL-1034).). Volatile memory
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`U.S. Patent 6,496,939
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`devices are vital components of a computer system and used as “a temporary
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`storage”. (Stallings, 109 (INTEL-1039).) “All computers have some fast random-
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`access memory called RAM.… RAM is always volatile, which means that its
`
`information evaporates when power is removed.” (“The Art of Electronics,” 2nd
`
`Edition, 1989 by Horowitz, et al. (“Horowitz”), 675 (INTEL-1037).) Specifically,
`
`the bit content in a volatile RAM device is “typically lost whether electric power to
`
`the RAM is momentarily interrupted, fluctuates, or is lost.” (U.S. Pat. No.
`
`5,608,684 (“Reasoner”), 1:15-20 (INTEL-1030).)
`
` The two forms of RAM commonly used in computers are DRAM and
`
`SRAM. DRAM and SRAM devices utilize different circuit configurations that
`
`make them best suited for different data-storing applications. In general, DRAM
`
`has nearly an order of magnitude more cells per unit area and is “less expensive
`
`than a corresponding static RAM,” and on the other hand, “static RAMs are
`
`generally somewhat faster than DRAMs.” (Stallings, 110 (INTEL-1039).)
`
`b) Non-Volatile Memory
` Non-volatile memory devices are read and write accessible memory
`
`devices that retain information even when the power supply is lost. (U.S. Pat. No.
`
`4,974,167 (“Anderson”), 1:23-28 (INTEL-1031).)
`
`16
`
`Petitioner Intel Corp., Ex. 1003
`IPR2023-00783
`
`

`

` Some non-volatile memory is read-only memory (“ROM”) that
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`U.S. Patent 6,496,939
`IPR2023-00783
`
`
`contains a “permanent pattern of data that cannot be changed.” (Stallings, 110
`
`(INTEL-1039).) Data is wired into these types of ROM devices either during chip
`
`fabrication or later using special equipment, and “it is not possible to write new
`
`data into it.” (Stallings, 110 (INTEL-1039).) While there are many applications
`
`suitable for ROM devices (e.g., micro-programming), non-volatile memory
`
`devices with the capability of being written into without using special equipment
`
`are versatile and can be “useful for applications in which read operations are far
`
`more frequent than write operations but for which nonvolatile storage is required.”
`
`(Stallings, 110 (INTEL-1039).)
`
` Non-volatile memory devices that have the capability of being written
`
`into multiple times are referred to as “read-mostly memory.” (Stallings, 110
`
`(INTEL-1039).) “There are three common forms of read-mostly memory:
`
`EPROM, EEPROM, and flash memory.” (Stallings, 110 (INTEL-1039).)
`
`
`
`“[E]rasable programmable read-only memory (EPROM) is read and
`
`written electrically.” (Stallings, 110 (INTEL-1039).) EPROM requires that
`
`“storage cells must be erased to the same initial state” before a write operation can
`
`be performed. (Stallings, 110 (INTEL-1039).) “This erasure process can be
`
`performed repeatedly.” (Stallings, 110 (INTEL-1039).)
`
`17
`
`Petitioner Intel Corp., Ex. 1003
`IPR2023-00783
`
`

`

` Electrically erasable programmable read-only memory (“EEPROM”)
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`U.S. Patent 6,496,939
`IPR2023-00783
`
`
`has the advantage over EPROM due to the capability of being “written into at any
`
`time without erasing prior contents.” (Stallings, 110-111 (INTEL-1039).)
`
` Flash memory was “[f]irst introduced in the mid-1980s” and “is
`
`intermediate between EPROM and EEPROM in both cost and functionality.”
`
`(Stallings, 111 (INTEL-1039).) Flash memory got its name because of “the speed
`
`with which it can be reprogrammed.” (Stallings, 111 (INTEL-1039).) The erasure
`
`operation can be completed “in one or a few seconds, which is much faster than
`
`EPROM.” (Stallings, 111 (INTEL-1039).)
`
`Protecting Data During a Power Outage
`3.
` Problems in the power supply, such as power fluctuations and power
`
`interruptions, can cause errors in data stored in volatile memory devices. These
`
`errors are often referred to as soft errors: “[a] soft error is a random, non-
`
`destructive event that alters the contents of one or more memory cells, without
`
`damaging the memory. Soft errors can be caused by power supply problems or
`
`alpha particles.” (Stallings, 116 (INTEL-1039).)
`
` Vital information in volatile memories may be destroyed due to lost or
`
`corrupt data caused by problems in the power supply. To prevent such a
`
`catastrophic outcome, it was well known to equip computer systems with “memory
`
`backup” capabilities that enable the computer to transfer data from volatile
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`18
`
`Petitioner Intel Corp., Ex. 1003
`IPR2023-00783
`
`

`

`memories to non-volatile memories upon detecting a power interruption. The
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`U.S. Patent 6,496,939
`IPR2023-00783
`
`
`following paragraphs describe several examples of patents and patent application
`
`publications that were published before September 1999 and described computer
`
`systems with memory backup capabilities.
`
`
`
`Japanese Patent Application Publication No. JPH05-108505
`
`(“Nishida”) was published on April 30, 1993 and “relates to computer systems
`
`with memory backup functions.” (Nishida, ¶1 (INTEL-1006).) Nishida’s computer
`
`system includes “a CPU, a volatile main recording memory, a non-volatile external
`
`recording device.” (Nishida, claim 1 (INTEL-1006).) In the event of a power
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`outage, “the data on the main memory is urgently transferred to a non-volatile
`
`external recording device using the power supply for the backup to protect data.”
`
`(Nishida, ¶2 (INTEL-1006); see also ¶¶3, 4, 15.)
`
` U.S. Pat. No. 4,965,828 (“Ergott”) was issued on October 23, 1990
`
`and described “a system that utilizes a volatile SRAM and a non-volatile backup
`
`store implemented by means of E2PROMs in which data is transferred from the
`
`SRAMs to the E2PROMs when the power is turned off or interrupted by using
`
`high voltage energy stored in a backup capacitor to provide operating power for at
`
`least a long enough period of time to effectuate reliable transfer of data from the
`
`SRAM to the E2PROM.” (Ergott, 3:2-10 (INTEL-1008).)
`
`19
`
`Petitioner Intel Corp., Ex. 1003
`IPR2023-00783
`
`

`

` Bruder was issued on December 17, 1985 and described a memory
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`U.S. Patent 6,496,939
`IPR2023-00783
`
`
`system that includes a semiconductor volatile RAM memory and a non-volatile
`
`memory for backing up the volatile memory. (Bruder, Abstract (INTEL-1034).)
`
`Whenever there is a power failure, “the entire contents of CMOS 41 [the volatile
`
`memory] is transferred to non-volatile bubble memory 42.” (Bruder, 7:57-60
`
`(INTEL-1034).)
`
` U.S. Pat. No. 4,327,410 (“Patel”) was issued on April 27, 1982 and
`
`described financial terminals that include a “system for preserving data associated
`
`with a memory unit.” (Patel, Abstract (INTEL-1035).) When normal operation
`
`power is available, the volatile RAM memory stores Terminal Processor (TP) data
`
`such as “teller totals, accumulators, transaction counters, supervisory codes, and
`
`terminal sign-in information.” (Patel, 4: 21-40 (INTEL-1035).) When there is an
`
`impending power failure, the data in the volatile RAM memory is transferred
`
`to the non-volatile memory. (Patel, 4: 21-40 (INTEL-1035).)
`
` Holzhammer was issued on May 21, 1996 and described a method
`
`used in a computer system for saving data from a volatile cache memory during a
`
`power loss. (Holzhammer, Abstract (INTEL-1036).) Specifically, a control logic
`
`