I 1111111111111111 11111 lllll 111111111111111 111111111111111 lll111111111111111
`
`US007299316B2
`
`c12) United States Patent
`Chou et al.
`
`(IO) Patent No.:
`(45) Date of Patent:
`
`US 7,299,316 B2
`*Nov. 20, 2007
`
`(54) MEMORY FLASH CARD READER
`EMPLOYING AN INDEXING SCHEME
`
`(75)
`
`Inventors: Horng-Yee Chou, Palo Alto, CA (US);
`Edward W. Lee, Mountain View, CA
`(US)
`
`(73) Assignee: Super Talent Electronics, Inc., San
`Jose, CA (US)
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by O days.
`
`This patent is subject to a terminal dis(cid:173)
`claimer.
`
`(21) Appl. No.: 10/956,826
`
`(22) Filed:
`
`Oct. 1, 2004
`
`(65)
`
`Prior Publication Data
`
`Sep. 1, 2005
`US 2005/0193162 Al
`Related U.S. Application Data
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`2002/0036922 Al *
`2003/0093606 Al *
`2003/0177300 Al *
`2004/0243749 Al*
`2005/0083741 Al*
`2005/0114587 Al*
`2005/0144360 Al*
`2005/0182858 Al*
`2005/0193161 Al*
`2005/0193162 Al*
`2005/0216624 Al*
`
`3/2002 Roohparvar ........... 365/185.11
`5/2003 Mambakkam et al ....... 710/305
`9/2003 Lee et al.
`................... 711/103
`12/2004 Learmonth ................... 710/73
`4/2005 Chang et al.
`............... 365/200
`5/2005 Chou et al. ................. 711/103
`6/2005 Bennett et al .............. 711/103
`8/2005 Lo et al. ........................ 710/1
`9/2005 Lee et al.
`................... 711/103
`9/2005 Chou et al. ................. 711/103
`9/2005 Deng et al. ................... 710/74
`
`OTHER PUBLICATIONS
`
`Standard Microsystems Corporation, USB97C242, USB 2.0 Flash
`Driver Controller Data Sheet, Oct. 2002, pp. 1-22.*
`
`* cited by examiner
`
`Primary Examiner-Hong Kim
`(7 4) Attorney, Agent, or Firm-Schein & Cai LLP; Douglas
`Mackenzie; James Cai
`
`(63) Continuation-in-part of application No. 10/789,333,
`filed on Feb. 26, 2004, now abandoned.
`
`(57)
`
`ABSTRACT
`
`(51)
`
`Int. Cl.
`G06F 13/00
`(2006.01)
`(2006.01)
`G06F 12/00
`(52) U.S. Cl. ....................... 711/103; 711/115; 711/159;
`711/170
`(58) Field of Classification Search ................ 711/103,
`711/115, 159,170,109; 710/305
`See application file for complete search history.
`
`A memory flash card reader includes a processor for receiv(cid:173)
`ing at least one request from a host system, an index
`comprising information regarding sectors of the memory
`flash card wherein the processor may utilize the index to
`determine sectors of the memory flash card that are available
`for programming, reprogramming, or reading, and at least
`one card controller coupled to the processor.
`
`32 Claims, 18 Drawing Sheets
`
`i---------------------------------------
`600
`615
`CBW 31 b es
`
`Sector
`20 ~
`~
`630
`
`Not Empty
`Interrupt
`
`PBA
`(MSB 6)
`
`430
`
`635
`
`Physical Usage
`Table(PUT)
`
`645
`
`s9_
`~
`-------------- _________________ l ______ _
`
`Block Copy and
`Recycling FIFO
`
`\..552
`
`660
`
`655
`
`650
`
`Card
`Controller
`
`440/460
`
`450/470
`Card_,}
`
`Connector
`
`320
`
`~120
`
`INTEL-1012
`8,010,740
`
`

`

`U.S. Patent
`
`Nov. 20, 2007
`
`Sheet 1 of 18
`
`US 7,299,316 B2
`
`{100
`
`Card Reader
`
`I
`
`I
`I
`
`l120
`
`,.._
`.....
`0
`(_)
`Q.)
`C
`C
`0
`()
`
`Flash
`Memory
`Card
`
`l140
`
`'--13 0
`
`Host System
`110
`
`FIG. 1
`
`

`

`U.S. Patent
`
`Nov. 20, 2007
`
`Sheet 2 of 18
`
`US 7,299,316 B2
`
`USB
`Cable
`~ 210
`-
`
`I
`
`I
`
`I
`
`I
`
`Host
`System
`110
`-
`
`FIG. 2
`
`
`1 20
`_)
`
`-----------
`Card
`Reader
`Box
`200
`-
`
`Connector 140
`
`Memory
`Card
`130
`
`

`

`U.S. Patent
`
`Nov. 20, 2007
`
`Sheet 3 of 18
`
`US 7,299,316 B2
`
`Host USB Controller
`
`33 0
`
`------------- ---------------
`
`I,
`
`I USB Controller -
`
`32 0
`
`)
`_J 0
`
`~
`
`3 00
`
`I
`·~
`------------- ---------------
`,.
`t I
`14
`
`I
`I
`
`I
`
`Memory Card
`
`Connector
`
`Connector
`
`I
`
`uo
`
`Circuits
`
`310
`
`External
`10
`
`FIG. 3
`
`

`

`U.S. Patent
`
`Nov. 20, 2007
`
`Sheet 4 of 18
`
`US 7,299,316 B2
`
`490
`USB
`Connector--'
`
`480
`
`{120
`
`Serial
`Engine
`
`400
`LJ
`
`420
`
`u
`
`CPU
`
`RAM
`
`(410
`
`430
`_)
`
`ROM
`FIRMWARE
`
`440
`
`~o
`
`Card Controller
`#1
`
`CardController
`#2
`
`300a
`
`300b
`
`Connector #1
`
`Connector #2
`
`FIG. 4
`
`

`

`U.S. Patent
`
`Nov. 20, 2007
`
`Sheet 5 of 18
`
`US 7,299,316 B2
`
`140
`Card
`Connector_)
`
`~-----'---~ 560
`_)
`
`Card Controller
`
`./130
`
`CPU
`
`RAM
`
`(510
`
`540
`_)
`
`(550
`
`Flash
`Memory
`Controller
`
`I
`I
`
`I
`
`I
`
`30
`
`ROM
`FIRMWARE
`
`Flash
`Memory
`Array
`
`-
`
`--
`
`FIG. 5
`
`

`

`U.S. Patent
`
`Nov. 20, 2007
`
`Sheet 6 of 18
`
`US 7,299,316 B2
`
`1
`
`,----------------------------------------
`600
`615
`CBW (31 bytes)
`,- - +-8- 103 ~
`620
`I
`Data
`1-1--;-_ __,
`Transferlenth
`Re
`! WR Ptr!
`
`I
`
`I
`
`I
`
`Sector
`FIFO
`
`Sector
`
`LBA
`Reg
`
`Sector
`
`I
`- - - 625
`
`RDPtr
`
`630
`
`Not Empty
`Interrupt
`
`635
`
`Physical Usage
`Table (PUT)
`
`PBA
`(MSB .. 6)
`
`PBA
`(MSB .. 6)
`
`670
`
`Interrupt
`Handler
`
`Micro(cid:173)
`Processor
`105
`
`ROM
`
`430
`
`RD-LUT
`
`645
`
`Block Copy and
`Recycling FIFO
`
`1--PBAx~ S'""-t
`\_662
`660
`655
`._______. 650
`-------------- -----------------l ------
`320
`
`400 640
`
`'1R_ptrl
`
`Card
`Controller
`
`440/460
`
`450/470
`Card__)
`Connector
`
`\_120
`
`FIG. 6
`
`

`

`700
`
`LBAJI LBA[MS
`
`.. 6]
`
`PBAx = PBA[MSB .. 6]
`
`32 bits
`
`705
`
`64 bits
`
`710
`
`Physical
`Usage Table
`)
`
`/ UfU
`
`-
`P81~
`
`,-
`
`Block Copy and
`Recycling FIFO
`650
`
`PBAx
`
`(660
`~
`~
`
`l662
`
`WR-LUT640 _,)
`
`501
`
`502
`
`~
`~
`
`e •
`
`00
`•
`~
`~
`~
`
`~ = ~
`
`z 0
`
`~
`N
`~o
`N
`0
`0
`-....J
`
`('D
`('D
`
`rJ'1 =(cid:173)
`.....
`-....J
`0 ....
`....
`
`QO
`
`RD-LUT 645
`
`LBAx > PBAx
`Look Up Table
`
`FIG. 7
`
`d r.,;_
`
`-....l
`'N
`\0
`\0 w
`"""' 0--, = N
`
`

`

`U.S. Patent
`U.S. Patent
`
`Nov. 20, 2007
`Nov.20, 2007
`
`Sheet 8 of 18
`Sheet 8 of 18
`
`US 7,299,316 B2
`US 7,299,316 B2
`
`OS8Org0z3GLE8—01gpegOLSplayeyeq
`pom[momafom|me
`_Ngold
`
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`CX)
`
`~
`
`CX)
`
`(9
`LL
`
`0
`(")
`CX)
`
`0€8
`_)
`
`
`
`~
`(.)
`0
`Cl)
`
`"C rn
`
`Cl)
`
`0
`LC)
`CX)
`
`'--
`
`0
`s::f"
`
`CX) '--
`
`0
`N
`
`CX) '--
`.....
`
`LC)
`
`CX)
`
`.:,t.'----
`0
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`_Q .9
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`....I
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`c :,
`
`0
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`(I)
`V)
`
`~ w
`
`(.)
`(.)
`w
`
`V)
`(I)
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`CD
`N .....
`.....
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`Jadyiq|
`Q) ~ a. (.)
`49oj|q
`..... 0
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`
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`
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`C -
`
`Joyeolpul]490/qPeg
`
`
`
`

`

`U.S. Patent
`
`Nov. 20, 2007
`
`Sheet 9 of 18
`
`US 7,299,316 B2
`
`PowerUp
`Initialization
`
`No
`
`Command packet type/decode/status interrogation
`
`CBW/CSW Command register ready
`
`✓ 900
`
`No
`
`Flash Recycling Process
`
`920
`
`No
`
`940
`
`Write CBW Sector FIFO
`Trigger interrupt for processor
`
`Write status
`ACK return to
`Host
`
`945
`
`950
`
`Write process
`start by firmware
`
`Yes
`
`970
`
`No
`
`960
`
`Read Sector fifo
`data
`
`Read process
`starts
`
`Read ACK
`return to Host
`
`Read ACK if flash
`data ready
`
`975
`
`return
`
`FIG. 9
`
`

`

`U.S. Patent
`
`Nov. 20, 2007
`
`Sheet 10 of 18
`
`US 7,299,316 B2
`
`No request
`
`Read
`equest
`
`1000 \
`
`No
`
`Send NAK
`Handshake
`Packet back
`to the host
`
`1006
`
`1010
`
`1014
`
`Send ACK
`Handshake
`Packet back
`to the host
`
`Send Read
`Return Data
`Packet back
`to the host
`
`FIG. 10A
`
`

`

`U.S. Patent
`
`Nov. 20, 2007
`
`Sheet 11 of 18
`
`US 7,299,316 B2
`
`Yes
`
`------+1000
`
`9
`>--~-
`
`-5
`
`No
`
`No
`
`Phase I Sector
`Write Process
`1026
`
`Yes
`
`No
`
`Update Block
`Copy and
`Recycling
`FIFO
`1028
`
`FIG. 10B
`
`\_1020
`
`

`

`U.S. Patent
`
`Nov. 20, 2007
`
`Sheet 12 of 18
`
`US 7,299,316 B2
`
`Yes
`
`No
`
`--~_es _____ 1000
`
`Yes
`- - - - - 1020
`
`Phase II Block
`Copy Process
`1038
`
`Increment
`RD_ptr1
`1040
`
`"-1030
`
`FIG. 10C
`
`

`

`U.S. Patent
`
`Nov. 20, 2007
`
`Sheet 13 of 18
`
`US 7,299,316 B2
`
`Yes
`
`No
`
`No
`
`--~_e_s _ _ _ 1000
`
`No >------ 1020
`
`No
`">------1030
`
`Erase Block &
`Recycle
`1060
`
`Increment
`RD_ptr2
`1062
`
`FIG. 10D
`
`\_920
`
`

`

`U.S. Patent
`
`Nov. 20, 2007
`
`Sheet 14 of 18
`
`US 7,299,316 B2
`
`RD_LUT
`
`WR_LUT
`
`550
`
`Flash Media. 4
`sectors per Block
`
`AO A1 A2 A3
`
`A4 A5
`
`PUT m?O
`
`1
`
`1
`
`0
`
`645P
`
`640
`
`I '11:1:!l'I I t1:[l 1
`FIG. 11A
`
`O
`
`O
`
`1
`
`0 AO A1 A2 A3
`
`I
`
`11
`
`: I
`
`I
`
`I
`
`I
`
`I
`
`11
`
`I : I : I
`
`I
`
`1 A4 A5 B
`
`FIG. 11 B
`
`0
`
`1
`
`2
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`0
`
`AO A1 A2
`
`A3
`
`A4 A5 B
`
`co
`
`2
`
`C1
`
`FIG. 11C
`
`0
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`3
`
`4
`
`1
`
`1
`
`1
`
`0
`
`1
`
`0
`
`1
`
`0
`
`Phase
`I
`
`0
`
`AO A1 A2
`
`A3
`
`1
`
`1
`
`1
`
`1
`
`650 652
`Block
`
`1
`
`1
`
`2
`
`1
`
`2
`
`3
`
`4
`
`2
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`Phase
`
`A4 A5 B
`
`co
`
`C1
`
`ao a1 a2
`
`a3
`
`a4 A5 B
`
`co
`
`2
`
`3
`
`4
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`~
`
`/
`
`FIG.11D"
`
`r
`
`WR_ptr--..._
`192
`\
`655
`
`3
`
`4
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`3
`
`0
`
`1
`
`0
`
`1
`
`0
`
`1
`
`1
`
`1
`
`0
`
`0
`
`AO A1 A2
`
`A3
`
`A4 A5 B
`
`co
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`0 0 0 0 0-+-
`
`1 0
`
`1 1 1
`
`2
`
`1
`
`/
`
`3
`
`1
`
`1
`
`1
`
`1
`
`1
`
`Phase
`I
`
`1
`
`1
`
`1
`
`1
`
`Phase
`II
`
`2
`
`3
`
`5
`
`2
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`FIG. 11E
`
`C1 b1
`
`ao a1 a2
`
`a3
`
`a4 A5 B
`
`co
`
`a4 A5 bO
`
`co
`
`2
`
`3
`
`4
`
`5
`
`6
`
`4 1 1 0 1
`
`... ~
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`3
`
`1
`
`1
`
`1
`
`1
`
`A4 A5 B
`
`co
`
`0
`
`0
`
`0
`
`0
`
`0
`
`Erased
`
`0
`
`1
`
`0
`
`1
`
`0
`
`1
`
`0
`
`1
`
`0 0 0 0 0
`
`1 0
`
`1 1
`
`5
`
`2
`
`1
`
`1
`
`1
`
`1
`
`1
`
`6
`
`7
`
`3
`
`6
`
`7
`
`0
`
`1
`
`1
`
`1
`
`1
`
`0
`
`0
`
`1
`
`1
`
`1
`
`0
`
`0
`
`1
`
`1
`
`0
`
`1
`
`0
`
`1
`
`1
`
`0
`
`Phase
`I
`
`2
`
`3
`
`4
`
`C1 b1
`
`aO a1 a2
`
`a3
`
`a4 A5 B
`
`co
`
`Phase 5
`II
`6
`
`a4 A5 bO
`
`co
`
`a4 A5 bO
`
`a6
`
`FIG. 11F
`
`c1
`
`b1
`
`7
`
`8
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`...
`
`4 1
`
`1 - -
`1 0 1
`
`5
`
`1 1 1 1
`
`2 0
`
`1 0 0
`
`1105
`
`

`

`U.S. Patent
`
`Nov. 20, 2007
`
`Sheet 15 of 18
`
`US 7,299,316 B2
`
`1026
`
`\.
`
`Begin
`
`.----__._-~ 1205
`
`LBA, SC from
`CBW
`
`SectorNo <- Black
`Offset of LBA
`
`Block copy and
`recycling FIFO
`
`Entry from test
`WR_LUT
`
`PBAx
`
`I WRPtr I
`
`RD__ptr1
`RD__ptr2
`
`Update WR_LUT
`
`No
`
`~__,__~ 1290
`
`SectorNo <- 0
`
`_M_o_v_e-en-~-inLW-~_L_U_T-to-122O
`Recycle FIFO, Set relevant
`sector valid bits,
`WR ptr=WRptr+1
`
`~----'----1225
`
`Find an available free
`block from PUT,
`update WR-LUT
`
`---'---~ 1285
`
`LBAx <- LBAx + 1
`
`Write Page Data to Flash
`set [LBAx].Sector=1 in LUT
`
`1235
`
`No
`
`Yes
`
`No
`
`Set [PRAx] sector <- 1 in
`PUT
`
`____ .._ __ _
`
`1240
`
`SectorNo <- SectorNo + 1
`
`Yes
`
`SC <-SC-1
`
`1260
`
`No
`
`1270
`
`End
`
`FIG. 12
`
`

`

`U.S. Patent
`
`Nov. 20, 2007
`
`Sheet 16 of 18
`
`US 7,299,316 B2
`
`Begin
`
`No
`
`End
`
`1350
`
`Update RD-LUT <-WR-LUT
`
`No
`
`Block copy and
`recycling FIFO
`
`PBAx
`
`1 - - - - - - - -1 I RD_ptr1 I
`! WRPtr I
`
`Copy sector data to WR-LUT
`pointed new Flash address
`
`Set new [PUT].SectorNo
`<-1
`
`Set [WR-LUT].SectorNo
`<-1
`
`1345
`RD_ptr1 <- RD_ptr+ 1
`
`No
`
`SectorNo<- SectorNo + 1 1 4 - - - - - - - - '
`
`1335
`
`(
`
`1038
`
`FIG. 13
`
`

`

`U.S. Patent
`
`Nov. 20, 2007
`
`Sheet 17 of 18
`
`US 7,299,316 B2
`
`Begin
`
`/1060
`
`Yes
`
`End
`
`No
`
`1420
`
`Erase block pointed by
`RD_ptr2
`
`1430
`
`1440
`
`Update PUT for block availability
`
`RD_ptr2 <- RD_ptr2 +1?
`
`FIG. 14
`
`

`

`U.S. Patent
`
`Nov. 20, 2007
`
`Sheet 18 of 18
`
`US 7,299,316 B2
`
`Begin
`
`LBA, SC from
`CBW
`
`~1500
`
`No
`
`SectorNo = 0
`
`WR_LUT Translation
`LBAx->PBAx
`
`----''---- 1520
`RD-LUT
`Translation
`LBAx-> PBAx
`
`1575
`
`LBAx = LBAx+ 1
`
`1570
`
`Yes
`
`No
`
`Read Sector Data - - - - - - - - - - - - - - '
`from Flash
`1525
`Sector Count<-
`Sector Count-1
`
`SectorNo =
`SectorNo +1
`
`No
`
`1550
`
`ECC correction
`
`Current sector
`data ready to
`be returned
`
`1555
`
`1545 d0
`
`No
`
`Yes
`
`End
`
`FIG. 15
`
`

`

`US 7,299,316 B2
`
`1
`MEMORY FLASH CARD READER
`EMPLOYING AN INDEXING SCHEME
`
`CROSS REFERENCE TO RELATED
`APPLICATIONS
`
`The present application is a continuation in part of appli(cid:173)
`cation Ser. No. 10/789,333, entitled "System and Method for
`Controlling Flash Memory", filed on Feb. 26, 2004, now
`abandoned, the disclosure of which is herein incorporated by
`reference in its entirety.
`
`BACKGROUND OF THE INVENTION
`
`5
`
`2
`require additional computing
`that
`utilizes protocols
`resources at the host system. It is also slow.
`Disadvantages of many of the above-described and other
`known arrangements
`include additional host system
`resources required to process special protocols and the
`resulting added processing time required for managing flash
`memory.
`Accordingly, there is a need for a USB flash memory card
`reader capable of reading a plurality of flash memory card
`10 formats which incorporates an improved system and method
`for controlling the flash memory card. The USB flash
`memory card reader preferably complies with the USB
`standard, is suitable for ASIC hardware implementation, and
`is fast, simple, cost effective and capable of being easily
`15 adapted to existing silicon technology. The present invention
`addresses such a need.
`
`The present invention relates generally to memory sys(cid:173)
`tems and more particularly to a system and method for
`providing a USB flash memory card reader capable of
`reading a plurality of flash memory card formats.
`As flash memory technology becomes more advanced,
`flash memory is replacing traditional magnetic hard disks as 20
`storage media for mobile systems. Flash memory has sig(cid:173)
`nificant advantages over magnetic hard disks such as having
`high-G resistance and low power dissipation. Because of the
`smaller physical sizes of flash memory, they are also more
`the flash 25
`conducive to mobile systems. Accordingly,
`memory trend has been growing because of its compatibility
`with mobile systems and its low-power feature.
`New generation personal computer (PC) card technolo(cid:173)
`gies have been developed that combine flash memory with
`architecture that is compatible with the Universal Serial Bus 30
`(USB) standard. This has further fueled the flash memory
`trend because the USB standard is easy to implement and is
`popular with PC users. In addition to replacing hard drives,
`flash memory is also replacing floppy disks because flash
`memory provides higher storage capacity and faster access 35
`speeds than floppy drives.
`However, the USB standard has several features that
`require additional processing resources. These features
`include fixed-frame times, transaction packets, and enu(cid:173)
`meration processes. For better optimization, these features
`have been implemented in application-specific integrated
`circuits (AS I Cs).
`In addition to the limitations introduced by the USB
`standard, there are inherent limitations with flash memory. 45
`First, flash memory sectors that have already been pro(cid:173)
`grammed must be erased before being reprogrammed. Also,
`flash memory sectors have a limited life span; i.e., they can
`be erased only a limited number of times before failure.
`Accordingly, flash memory access is slow due to the erase- 50
`before-write nature and ongoing erasing will damage the
`flash memory sectors over time.
`Hardware and firmware utilize existing small computer
`systems interface (SCSI) protocols so that flash memory can
`function as mass-storage devices similar to magnetic hard 55
`disks. SCSI protocols have been used in USE-standard
`mass-storage devices long before flash memory devices
`have been widely adopted as storage media. Accordingly,
`the application extensions of the USB standard have incor(cid:173)
`porated traditional SCSI protocols.
`A prior art solution provides a driver procedure for flash
`memory write transactions. This procedure has three differ(cid:173)
`ent sub-procedures. Generally, the data of a requested flash
`memory address is first read. If there is data already written
`to that address, the firmware executes an erase command. 65
`Then, if the erase command executes correctly, the firmware
`executes a write request. However, this driver procedure
`
`SUMMARY OF THE INVENTION
`
`In accordance with one aspect of the invention, a memory
`flash card reader includes a processor for receiving at least
`one request from a host system, an index comprising infor(cid:173)
`mation regarding sectors of the memory flash card wherein
`the processor may utilize the index to determine sectors of
`the memory flash card that are available for programming,
`reprogramming, or reading, and at least one card controller
`coupled to the processor.
`In another aspect of the invention, a method of managing
`a flash memory includes the steps of receiving at least one
`request from a host system in a processor within a flash
`memory controller, determining which sectors of the flash
`memory are available for writing, erasing and reading uti(cid:173)
`lizing the processor and an index coupled to the processor,
`and writing, erasing and reading to a flash memory card
`through at least one card controller coupled to the processor.
`These and other feature, aspects, and advantages of the
`present invention will become better understood with refer(cid:173)
`ence to the following drawings, description, and claims.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`40
`
`FIG. 1 is a schematic representation showing a memory
`card coupleable to a host computer in accordance with the
`invention;
`FIG. 2 is a schematic representation showing a memory
`card coupleable to a host computer through a card reader box
`in accordance with the invention;
`FIG. 3 is a schematic representation showing a logical
`representation of the configuration of FIG. 1 or 2 in accor(cid:173)
`dance with the invention;
`FIG. 4 is a block diagram of a first portion of a peripheral
`device in accordance with the invention;
`FIG. 5 is a block diagram of a second portion of a
`peripheral device in accordance with the invention;
`FIG. 6 is a block diagram of a preferred embodiment of
`the first portion in accordance with the invention;
`FIG. 7 is a block diagram of a logical/physical block
`address translation look up table, a physical usage table, and
`60 a block copy and recycling FIFO in accordance with the
`invention;
`FIG. 8 is a block diagram of a peripheral flash device
`array data structure in accordance with the invention;
`FIG. 9 is a flow chart of a firmware read/write/erase
`method in accordance with the invention;
`FIG. lOA is a flow chart of a main firmware service
`method in accordance with the invention;
`
`

`

`US 7,299,316 B2
`
`3
`FIG. 10B is a flow chart of a phase I flash write method
`in accordance with the invention;
`FIG. lOC is a flow chart of a phase II block copy method
`in accordance with the invention;
`FIG. lOD is a flow chart of an erase and recycle method 5
`in accordance with the invention;
`FIGS. llA through llF are tables showing a representa(cid:173)
`tive example in accordance with the invention;
`FIG. 12 is a detailed flow chart of a write sector method
`in accordance with the invention;
`FIG. 13 is a detailed flow chart of a phase II background
`sector copy method in accordance with the invention;
`FIG. 14 is a flow chart of an erase and recycle method in
`accordance with the invention; and
`FIG. 15 is a flow chart of a read method in accordance
`with the invention.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`The following detailed description is of the best mode of
`carrying out the invention. The description is not to be taken
`in a limiting sense, but is made merely for the purposes of
`illustrating the general principles of the invention, since the
`scope of the invention is best defined by the appended
`claims.
`In a first aspect of the invention, and with reference to
`FIG. 1, there is shown a card reader system generally
`designated 100 including a first portion 120 which may be
`disposed within a host system 110 and a second portion 130
`coupleable to the first portion 120. First portion 120 may
`include a card reader and second portion 130 may include a
`flash memory card. Note that the first portion 120 and the
`host system 110 can reside on the same printed circuit board
`in one specific implementation. In another implementation,
`they can be separate boards. First portion 120 may be
`coupled to the host system 110 by means of a standard
`interface that may provide both mechanical and electrical
`connection between the first portion 120 and the host system
`110. The standard interface may include a conventional 3.5
`inch slot, a 5.25 inch slot, or a riser card. The electrical
`interface between the first portion 120 and the host system
`110 preferably includes the USB interface.
`The second portion 130 may be removably coupled to the
`first portion 120 by means of second portion connector 140.
`The connection between the second portion 130 and the first
`portion 120 may include a proprietary connection, Multi
`Media Card (MMC), Secure Digital (SD) Card, Memory
`Stick (MS), Smart Media (SM), Compact Flash (CF), PC!
`Express, Serial Advanced Technology Attachment (SATA),
`Serial Attached Small Computer System Interface (SCSI),
`and IEEE 1394. The connection may include a MXl (mul(cid:173)
`tiple in one) or a lxl (one in one) connection.
`The second portion connector 140 generally includes pins
`that provide connections to ground, voltage supplies, serial/
`parallel data in and/or out, control lines, select lines, address
`lines, test pins as well as a signal that acknowledges the
`presence of the second or daughter portion 130. Depending
`on selective implementations of these pins, many pins or
`very few pins may be used in the second portion connector
`140 and a first portion second connector 300 (FIG. 3). In a
`minimum pin implementation, data, addresses and com(cid:173)
`mands are multiplexed into a serial stream before being
`passed across the second portion connector 140. Once
`across, the serial stream may be de-multiplexed into its
`respective components. As an example, this serial stream
`may be an MMC interface.
`
`4
`According to one aspect of the invention, a peripheral
`device may include flash memory chips and supporting
`hardware circuits that form a USB controller 320 (FIG. 3)
`for controlling the operations of the flash memory and for
`interfacing to the host system 110. The peripheral device can
`be partitioned such that the USB controller 320 resides on
`the first portion 120 and the flash memory chips reside on the
`second portion 130, such as defined by the XD standard. A
`more popular partition is to put all of the complexity onto the
`10 USB controller 320. In this case a controller on the memory
`card 130 only has a very simple interface control.
`In this manner, a cost-effective flash memory system is
`provided, especially in applications where magnetic floppy
`disks are to be replaced. In accordance with the invention,
`15 second portion 130 may act essentially like a semiconductor
`flash memory "floppy disk" and may or may not have a
`controller on the second portion 130. The USB controller
`320 on the first portion 120 may then serve any number of
`flash memory "floppy disks". The cost of each flash memory
`20 "floppy disk" is therefore reduced by simplifying or elimi(cid:173)
`nating the controller on the "floppy disk" itself. Another
`advantage is an increase in system flexibility. A user may
`add or decrease memory capacity by choosing among sec(cid:173)
`ond portion 130 cards with various amounts of installed
`25 memory. Also, with each update or upgrade of the USB
`controller 320, only the first portion 120 needs be replaced,
`the second portion 130 card "floppy disk" being fully usable
`with an updated or upgraded first portion 120.
`In another aspect of the invention and with reference to
`30 FIG. 2, first portion 120 may include a USB flash memory
`card reader box 200 which may be coupled to the host
`system 110 by means of a USB cable 210. Card reader box
`200 may include USB controller 320. The second portion
`130 may be removably coupled to the card reader box 200
`35 by means of second portion connector 140.
`As shown in FIG. 3, a logical representation of the card
`reader system 100 may include the second portion 130
`having circuits 310 disposed therein. Circuits 310 may
`include flash memory chips. USB controller 320 may be
`40 disposed in first portion 120 which may be coupled to a host
`USB controller 330 disposed in host system 110.
`First portion 120 may include a first portion processor 400
`coupled to a bus 410 as shown in FIG. 4. A random access
`memory device 420 and a read only memory device 430 may
`45 be coupled to bus 410. A USB serial engine 480 may be
`coupled to bus 410 and include a USB connector 490. A pair
`of card controllers 440 and 460 may be coupled to bus 410
`and include connectors 300a and 300b respectively. Card
`controllers 440 and 460 may include controllers adapted to
`50 interface with flash memory cards having different connec(cid:173)
`tions such as a proprietary connection, Multi Media Card
`(MMC), Secure Digital (SD) Card, Memory Stick (MS),
`Smart Media (SM), Compact Flash (CF), XD, PCI Express,
`Serial Advanced Technology Attachment (SATA), Serial
`55 Attached Small Computer System Interface (SCSI), and
`IEEE 1394. Although only two card controllers 440 and 460
`are shown, those skilled in the art will appreciate that a
`plurality of card controllers may be coupled to bus 410.
`Second portion 130 may include a second portion pro-
`60 cessor 500 coupled to a bus 510 as shown in FIG. 5. A
`random access memory device 520 and a read only memory
`device 530 may be coupled to bus 510. A flash memory
`controller 540 may be coupled to bus 510 and to a flash
`memory array 550. A card controller 560 may be coupled to
`65 bus 510 and to second portion connector 140.
`With reference to FIG. 6, USB controller 320 may include
`serial engine 480 having a transceiver 600 operable to
`
`

`

`US 7,299,316 B2
`
`10
`
`5
`convert analog signals to digital streams and to provide a
`phase lock loop circuit for generating precision clocks for
`internal data latching. For USB 2.0, the phase lock loop
`functionality can be sensitive and thus useful due to its
`operating at 480 MHz. Serial engine 480 may also include 5
`a serial interface engine (SIE) 610 which may provide serial
`and parallel data conversion, packet decoding/generation,
`cyclic redundancy code (CRC) generation/checking, non(cid:173)
`return-to-zero (NRZI) encoding/decoding, and bit stuffing
`according to the USB 2.0 standard.
`A bulk-only transport unit (BOT) 615 may receive com(cid:173)
`mand block wrappers (CBW) and may include a data
`transfer length register 620 and a logical block address
`(LBA) register 625.
`A sector FIFO 630 may be used for data buffering. A 15
`FIFO-not-empty interrupt signal 635 may trigger an inter(cid:173)
`rupt service routine at an interrupt handler of processor 400.
`The interrupt routine responds to the host system 110
`confirming that a write process has been completed. In the
`mean time, processor 400 may execute firmware stored in 20
`ROM 430 to take care of sector data in FIFO 630 and
`execute the write process.
`Microprocessor 400 may be an 8-bit or a 16-bit processor.
`Microprocessor 400 may be operable to respond to host
`system 110 requests and communicate with second portion
`130 through card controller 440, 460. As firmware algo(cid:173)
`rithms become more complicated, tradeoffs between perfor(cid:173)
`mance and cost may determine the proper microprocessor
`selected.
`In order to achieve logical to physical address translation, 30
`two look up tables may be used, write look up table 640 for
`write access and read look up table 645 for read access.
`Write look up table 640 and read look up table 645 provide
`an index or indexing scheme to flash memory array 550. A
`block copy and recycling FIFO 650 may be used with a write
`pointer 655 and two read pointers 660 and 662 assigned for
`block valid sector copy and erase operations. These two
`functions may share one FIFO mechanism to fulfill this
`purpose and may run in the background.
`The physical usage table 670 may be used for physical 40
`sector mapping bookkeeping and may provide a bitmap
`indicating programmed sectors, that is, sectors to which data
`has already been written. Card controllers 440 and 460 may
`interface with second portion 130 to carry out commands
`from processor 400. Card controllers 440 and 460 may
`receive physical block addresses (PBAs) from write and
`read look up tables 640 and 645 respectively to service write
`and read requests.
`For optimal ASIC implementation, the write look up table
`640, the read look up table 645, the physical usage table 670, 50
`and the recycling FIFO 650 may be implemented with
`volatile random access memory 420.
`With reference to FIG. 7, logical block addresses (LBAs)
`700 may be used to index the write look up table 640 and the
`read look up table 645. Block offset bits (bit0 to bit5) may 55
`not be needed as both the write look up table 640 and the
`read look up table 645 use a block address based search
`mechanism. PBAx 705 may be a physical block address of
`flash memory array 550 (FIG. 5) and sector valid field 710
`may include a bit which may indicate whether this specific 60
`sector data is valid or not. Each entry in the write look up
`table 640 and read look up table 645 may point to a physical
`block address.
`Read look up table 645 may be dedicated to read trans(cid:173)
`actions while write look up table 640 may be dedicated to
`write transactions. To maintain block address consistency
`and achieve write efficiency, the write process may be
`
`6
`segregated into two phases. Once the exact addresses are
`calculated from the write look up table 640, new data sectors
`may be written into flash memory 550 immediately and
`control returned to the firmware routine. If a next transaction
`is a read transaction, a physical block address may be looked
`up from the read look up table 645 if the read address is
`different from the last write address. In the meantime, a valid
`sector copy from an old block to a new block may be
`performed in the background to maintain data coherency.
`Every time a sector-write occurs, usage information may
`be recorded in the physical usage table 670. Bit mapping of
`the physical usage table 670 is a recording of all sectors
`used.
`Each time a sector-write occurs, an obsolete block may be
`put in the block copy and recycling FIFO 650. The copying
`process may be started when the write process is complete.
`The erasing and recycling processes may be started when all
`necessary copies are completed.
`A flash memory data structure generally designated 800 is
`shown in FIG. 8 including a data field 810 having 512 or
`2112 bytes. Spare fields may include ECC 820, bad block
`indicator 815, erase count 840 for each block as a life time
`mileage indicator, and a logical block address field 850 for
`system initialization. A bad block may occur when read/
`25 write sector data fails or erase block fails. A last block
`bookkeeping field 830 may be easier for the firmware
`routine to read with setting 835 as one bit per block. To
`maintain reliability, four copies of bad block indicators may
`be saved in a last block of the flash memory 550.
`In accordance with the USB 2.0 protocol, host system 110
`is always the command master which sends out commands
`through token packets. In the mass storage class, bulk-only
`transport is the standard which uses Reduced Block Com(cid:173)
`mand (RBC) of the SCSI communication protocol to read/
`35 write a target flash device. A 31 byte command format
`describes the read/write direction, logical block address, and
`transfer sector length as the sector count. The firmware
`routine processes the command by using the flash memory
`550 as a storage medium.
`A method of processing a USB command in accordance
`with the invention generally designated 900 is shown in FIG.
`9. In step 905 receipt of a USB command/status token packet
`from the host system 110 may be determined. If no USB
`command/status token packet has been received, then in step
`45 910 the status of the recycling FIFO 650 may be determined.
`If the recycling FIFO 650 is not empty, then in step 920, a
`flash recycling process may be performed as further
`described herein. If the recycling FIFO 650 is empty, the
`processing returns to step 905.
`If a USB command/status token packet has been received,
`then in step 925, the packet may be processed by the serial
`interface engine 610 (FIG. 6). Next, in step 930 the bulk(cid:173)
`only transport unit 615 may receive command block wrap(cid:173)
`pers.
`In step 935, it may be determined if the packet is an IN
`packet. If the packet is not an IN packet then in step 940
`sector FIFO 630 is filled and an interrupt is sent to micro(cid:173)
`processor 400. Once the write data is written to the sector
`FIFO 630, an ACK write status is returned to the host system
`110 in step 945. In step 950 the write flash process may be
`started by the firmware routine.
`If the packet is an IN packet then in step 955 it may be
`