Carl Sechen
`
`Professor
`Dept. of Electrical Engineering
`University of Texas at Dallas
`carl.sechen@utdallas.edu
`972-835-1611
`
`Research Interests
`My research interests center primarily on the design and computer-aided design of digital and
`analog integrated circuits. Ongoing projects include fast, accurate simulation-based timing
`analysis. Also, the design of secure ICs that cannot be reverse engineered. One aspect of this is
`the design of novel types of embeddable field-programmable circuits for design obfuscation. We
`are also working on reverse engineering of PCBs that are damaged and/or discarded.
`
`Education
`Ph.D., Electrical Engineering, University of California, Berkeley, 1986
`Thesis: Placement and Global Routing of Integrated Circuits Using Simulated
`Annealing
`Advisor: Prof. Alberto Sangiovanni-Vincentelli
`M.S., Electrical Engineering, Massachusetts Institute of Technology, 1977
`Advisor: Prof. Stephen Senturia
`B.E.E., Electrical Engineering, University of Minnesota, 1975
`
`Employment history
`Professor, University of Texas at Dallas August 15, 2005 – present
`Professor, University of Washington July 1999 – August 14, 2005
`Associate Professor, University of Washington July 1992 – June 1999
`Associate Professor, Yale University July 1990 – June 1992
`Assistant Professor, Yale University July 1986 – June 1990
`
`University Administrative Positions
`Director of ECS Tech Support Services, UTD, June 2012 – February 2014
`
`Honors and Awards
` Best Paper Award at the 2017 IEEE PhD Research in Microelectronics and Electronics Con-
`ference (PRIME), for the paper “Improved Lagrangian Relaxation-based Gate Size and VT
`Assignment for Very Large Circuits”, Bariloche, Argentina, February 2017.
` Nominated for a Best Paper Award for: “A Field Programmable Transistor Array Featuring
`Single-Cycle Partial/Full Dynamic Reconfiguration”, Proc. of Design Automation and Test in
`Europe (DATE) Conference, March 27-31, 2017, Lausanne, Switzerland.
` Nominated for UTD’s President's Teaching Excellence Award for Graduate/Professional In-
`struction, 2020.
` Received the Distinguished Teaching Award for the Erik Jonsson School of Engineering and
`Computer Science, University of Texas at Dallas, 2014.
` Received the Distinguished Teacher of the Year Award, Dept. of Electrical Engineering, Erik
`Jonsson School of Engineering and Computer Science, University of Texas at Dallas, 2008.
` Elected IEEE Fellow in 2002
` Received the Outstanding Research Advisor Award, Department of Electrical Engineering,
`University of Washington, 2002.
`
`INTEL-1004
`8,010,740
`
`

`

` Received the Best Project Award, NSF Center for the Design of Digital and Analog ICs
`(CDADIC), July 2002.
` Received the Semiconductor Research Corporation’s 2001 SRC Inventor’s Recognition Award
` Received the Semiconductor Research Corporation’s 1994 SRC Technical Excellence Award
` Received the Semiconductor Research Corporation’s 1988 SRC Inventor's Recognition Award
`
`
`Litigation Support Experience
`
`Expert Engagement
`Type of Matter:
`Law Firm:
`Case Name:
`Services Provided:
`Disposition:
`Date:
`
`Patent litigation
`Latham Watkins
`Cannot disclose
`
`pending
`Started August 2021
`
`Patent litigation
`Orrick, Herrington, and Sutcliffe
`Cannot disclose
`
`pending
`Started August 2020
`
`Patent litigation
`Anova Law Group, PLLC
`Cannot disclose
`
`pending
`Started August 2021
`
`Patent litigation
`Perkins Coie
`Cannot disclose
`
`pending
`Started October 2021
`
`Patent ligitation
`Wilmer Cutler Pickering Hale and Dorr LLP (“WilmerHale”)
`Civil Action No. 6:19-cv-404-ADA FLASH-CONTROL, LLC, Plaintiff, v. IN-
`TEL CORPORATION; IN THE UNITED STATES DISTRICT COURT
`FOR THE WESTERN DISTRICT OF TEXAS AUSTIN DIVISION
`Expert consultation on behalf of Intel
`pending
`Started January 2020
`
`
`Expert Engagement
`Type of Matter:
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`Case Name:
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`Expert Engagement
`Type of Matter:
`Law Firm:
`Case Name:
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`Patent litigation
`Susman Godfrey LLP
`Arigna Technology Limited v. Volkswagen AG et al.,
`Case No. 2:21-cv-00054-JRG-RSP (E.D. Tex.)
`Services Provided: Expert consultation and testimony
`Disposition:
`Pending
`Date:
`Started 12/06/2020
`
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`Expert Engagement
`Type of Matter:
`Law Firm:
`Case Name:
`
`Patent litigation
`Susman Godfrey LLP
`Arigna Technology Limited v. Bayerische Motoren Werke AG et al.,
`Case No. 2:21-cv-00172-JRG-RSP (E.D. Tex.)
`Services Provided: Expert consultation
`Disposition:
`Pending
`Date:
`Started 12/06/2020
`
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`Expert Engagement
`Type of Matter:
`Law Firm:
`Case Name:
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`Patent litigation
`Susman Godfrey LLP
`Arigna Technology Limited v. Porsche AG, et al.,
`Case No. 2:21-cv-00173-JRG-RSP (E.D. Tex.)
`Services Provided: Expert consultation
`Disposition:
`Pending
`Date:
`Started 12/06/2020
`
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`Expert Engagement
`Type of Matter:
`Law Firm:
`Case Name:
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`Patent litigation
`Susman Godfrey LLP
`Arigna Technology Limited v. General Motors Company, et al.,
`Case No. 2:21-cv-00174-JRG-RSP (E.D. Tex.)
`Services Provided: Expert consultation
`Disposition:
`Pending
`Date:
`Started 12/06/2020
`
`
`Expert Engagement
`Type of Matter:
`Law Firm:
`Case Name:
`
`Patent litigation
`Susman Godfrey LLP
`Arigna Technology Limited v. Daimler AG, et al.,
`Case No. 2:21-cv-00175-JRG-RSP (E.D. Tex.)
`Services Provided: Expert consultation
`Disposition:
`Pending
`Date:
`Started 12/06/2020
`
`
`
`

`

`Expert Engagement
`Type of Matter:
`Law Firm:
`Case Name:
`
`ITC Investigation
`Susman Godfrey LLP
`In The Matter of Certain Power Inverters and Converters,
`Vehicles Containing the Same and Components Thereof,
`Inv. No. 337-TA-1267 (ITC)
`Services Provided: Expert consultation and testimony
`Disposition:
`Pending
`Date:
`Started 12/06/2020
`
`IPR filing
`Kirkland & Ellis LLP
`Case 1:19-cv-01006-UNA IPR PACT XPP Schweiz AG v. Intel Corporation
`IN THE UNITED STATES DISTRICT COURT FOR THE DISTRICT OF
`DELAWARE
`Expert consultation toward the filing of an IPR on behalf of Intel
`pending
`Started December 2019
`
`IPR filing
`Wilmer Cutler Pickering Hale and Dorr LLP (WilmerHale)
`VLSI Technology, LLC v. Intel Corporation, No. 3:17-cv-05671-BLF (N.D.
`Cal.),
`VLSI Technology, LLC v. Intel Corporation, No. 1:18-cv-00966-CFC-CJB (D.
`Del.) VLSI Technology, LLC v. Intel Corporation, No. 6:19-cv-00256-ADA
`(W.D. Tex.)
`Two declarations in support of an Intel IPR and two depositions
`pending
`Started May 1, 2019, ended July 30, 2020
`
`Patent infringement and associated IPR filing
`Baker Botts (DC case) and Sterne, Kessler, Goldstein & Fox P.L.L.C. (IPR case)
`Case No. 1:18-cv-555-LY
`
`UNITED STATES DISTRICT COURT
`WESTERN DISTRICT OF TEXAS
`AUSTIN DIVISION
`
`POLARIS INNOVATIONS, LTD., an
`Ireland limited company,
`Plaintiff,
`v.
`ADVANCED MICRO DEVICES, INC
`Filing a declaration in support of the IPR and planning for the district court case
`Case dissolved
`
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`Expert Engagement
`Type of Matter:
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`Date:
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`Expert Engagement
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`Services Provided:
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`Date:
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`Expert Engagement
`Type of Matter:
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`Services Provided:
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`Expert Engagement
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`Started Febrary 2019; ended May 2020
`
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`
`Trade secret case before an Arbitration Panel
`Anova Law Group
`TVL International LLC v. Zhejiang Shenghui Lighting Co., Ltd.
`
`Case No. 01-17-0004-7802
`AMERICAN ARBITRATION ASSOCIATION
`CHARLOTTE, NORTH CAROLINA
`
`
`
`In the matter of arbitration between
`
`
`TVL INTERNATIONAL LLC,
`
`
`Claimant,
`
`
`
`
`
`v .
`
`
`
`
`
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`ZHEJIANG SHENGHUI
`
`
`
`LIGHTING CO., LTD. and
`
`
`
`
`
`
`SENGLED USA, INC.
`
`Three expert reports completed, and testimony before the Arbitration Panel
`Ended with TVL declared the winner
`April 9, 2018 through August 31, 2018.
`
`
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`
`
`
`Challenge of Patent Validity
`Weil, Gotshal and Manges; but in the future: Orrick, Herrington & Sutcliffe
`North Star Innovations, Inc. v Micron Technology, Inc., et al., Case 17-cv-506-
`LPS-CJB,
`D. Del.
`Research in support of an IPR regarding Patent 5,943,274 on behalf of Micron
`In progress but no work performed to date
`March 5, 2018 through present
`
`Challenge of Patent Validity
`Baker Botts
`Advanced Micro Devices v. Broadcom
`One declaration in support of an IPR regarding Patent 7,472,151
`Case No. Unassigned
`Patent 7,472,151
`____________
`DECLARATION OF DR. CARL SECHEN IN SUPPORT OF PETITION FOR
`INTER PARTES REVIEW OF U.S. PATENT NO. 7,472,151
`Settled not long after the IPR was filed
`December 3, 2016 through March 27, 2017
`
`Trade Secret Misappropriation
`Wilson Sonsini Goodrich & Rosati
`
`

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`Case Name:
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`Services Provided:
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`GSI Technology, Inc. v. United Memories, Inc. and Integrated Silicon Solution,
`Inc.;
`Case No. 5:13-cv-1081-PSG in the United States District Court for the Northern
`District of California, San Jose Division
`One declaration on behalf of ISSI, one deposition and one trial testimony before
`a jury
`ISSI was victorious at trial and upon appeal
`May 2014 through November 2015
`
`Patent validity – PTO re-examination proceedings
`Bruce Itchkawitz, Knobbe Martens Olson & Bear; Rich Kim, Mehran Arjomand,
`and David Kim, Morrison & Foerster LLP
`Netlist, Inc. vs. Google, Inphi Corp., and Smart Modular Technologies
`Individual cases in the last 5 years:
`1. Inter Partes Review No. IPR2017-00667
`2. Inter Partes Review No. IPR2017-00549
`3. Inter Partes Review No. IPR2017-00692
`4. Inter Partes Review No. IPR2017-00562
`5. Inter Partes Review No. IPR2017-00561
`6. Inter Partes Review No. IPR2017-00587
`7. Inter Partes Review No. IPR2017-00560
`8. Appeal No. 2015-006849
`9. Appeal No. 2015-007761
`10. Inter Partes Review No. 2015-01021
`11. Reexamination Control No.: 95/001,337
`12. Inter Partes Review No. IPR2014-0097
`13. Inter Partes Review No. IPR2014-00970
`14. Inter Partes Review No. IPR2014-01011
`15. Inter Partes Review No. IPR2014-00883
`16. Inter Partes Review No. IPR2014-00883
`17. Appeal No. 2013-009044
`
`
`
`25 declarations, 5 depositions on behalf of Netlist, Inc., filed July 2011 through
`May 2015 supporting patent validity challenges before the PTO
`Worked on 6 separate IPR's, each involved writing an expert report and giving a
`deposition.
`Pending
`June 28, 2011 through March 2018
`
`Disposition:
`Date:
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`Expert Engagement:
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`Patent invalidity and patent non-infringement
`Wilson Sonsini Goodrich & Rosati (representing the defendant)
`HSM Portfolio, LLC, Technology Properties Limited, LLC v.
` Advanced Micro Devices (defendant)
`Case: 1:11-cv-00770-RGA (D. Del.)
`Services Provided: Work toward declaration on patent non-infringement
`Disposition:
`Settled in defendant’s favor
`Date:
`April 2013 through December 2013
`
`

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`Expert Engagement:
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`Patent non-infringement
`Jones Day (representing the defendant)
`Intellectual Ventures v. Xilinx (defendant)
`IN THE UNITED STATES DISTRICT COURT
`FOR THE DISTRICT OF DELAWARE
`INTELLECTUAL VENTURES I LLC and
`INTELLECTUAL VENTURES II LLC,
`Plaintiffs,
`v.
`ALTERA CORPORATION, MICROSEMI
`CORPORATION, LATTICE
`SEMICONDUCTOR CORPORATION and
`XILINX, INC.,
`Defendants.
`
`C.A. No. 10-1065 (LPS)
`(CONSOLIDATED)
`One declaration on patent non-infringement; one deposition
`Settled in defendants’ favor
`February 2013 through April 2014
`
`Patent non-infringement
`Morrison Foerster (representing the defendant)
`Intellectual Ventures v. Altera (defendant)
`IN THE UNITED STATES DISTRICT COURT
`FOR THE DISTRICT OF DELAWARE
`INTELLECTUAL VENTURES I LLC and
`INTELLECTUAL VENTURES II LLC,
`Plaintiffs,
`v.
`ALTERA CORPORATION, MICROSEMI
`CORPORATION, LATTICE
`SEMICONDUCTOR CORPORATION and
`XILINX, INC.,
`Defendants.
`
`C.A. No. 10-1065 (LPS)
`(CONSOLIDATED)
`One declaration on patent non-infringement; one deposition
`Settled in defendant’s favor
`February 2013 through December 2013
`
`Patent validity and patent infringement
`Antonelli, Harrington & Thompson LLP
`Guardian Media Technologies, Ltd., Plaintiff, v. Acer America Corp, et al., De-
`fendants.
`
`

`

`Cases:
` CIVIL ACTION NO. 6:10-CV-597-LED
`Case No. 2:13-CV-08369 PSG (PLAx)
`
`
`
`One declaration on patent validity and two declarations on patent infringement
`Settled in Plaintiff’s favor
`February 2013 through March 2015
`
`Services Provided:
`Disposition:
`Date:
`
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`Expert Engagement:
`Patent infringement
`Type of Matter:
`Winston & Strawn (Nanya)
`Law Firm:
`On Technologies vs. Nanya
`Case Name:
`Services Provided: Work on claim term definitions
`Disposition:
`Case was transferred from East. Dis. Texas to No. Calif. in late 2010; then set-
`tled
`March 2010 through October 2010
`
`Date:
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`Expert Engagement:
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`Disposition:
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`Patent infringement
`White and Case (Panasonic)
`Freescale Semiconductor vs. Panasonic
`Invalidity and non-infringement expert reports filed November 2010; deposition
`December 2, 2010
`ITC case settled January 2011
`April 2010 through January 2011
`
`Patent infringement
`Weil, Gotshal and Manges (Samsung)
`Rambus vs. Samsung
`One Declaration, One Deposition, and one trial testimony for Samsung
`
`Declaration:
`This report overviewed Rambus technology and patents, their alleged “steering”
`of patent claims, and Samsung’s subsequent DDR products.
`Deposition:
`Dr. Sechen was asked to consider whether Samsung’s subsequent DDR products,
`DDR2, DDR3, GDDR, GDDR2, GDDR3, and GDDR4 fell within the scope of
`their 2000 license agreement with Rambus. Representing attorney: Matt An-
`tonelli.
`Trial Testimony:
`Dr. Sechen testified before Judge Ronald Whyte, San Jose, CA, that Samsung’s
`subsequent DDR products, DDR2, DDR3, GDDR, GDDR2, GDDR3, and
`GDDR4 fell within the scope of their 2000 license agreement with Rambus.
`Representing attorney: Matt Antonelli.
`
`Dr. Sechen’s involvement completed on 30 September 2008 with the conclusion
`of the trial.
`
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`May 2008 through September 2008
`
`Patent infringement
`O’Melveny & Myers (Magma)
`Synopsys vs. Magma Design Automation
`Two Declarations, One Supplemental Declaration and Two Depositions for
`Magma
`
`Declaration:
`June 10, 2005: Dr. Sechen illustrated that the material in the Synopsys patents
`(originally patented by Magma, but awarded to Synospys by the court) were put
`into the public domain by Magma. In addition, he illustrated that the material in
`the Synopsys patents were generally in the public domain prior to the patents.
`
`Declaration:
`Dr. Sechen wrote a declaration supporting Magma’s proposed claim construc-
`tions for the two patents involved on July 21, 2005.
`
`Supplemental Declaration:
`July 13, 2005 Dr. Sechen had a supplemental declaration showing that Synop-
`sys’ expert report in fact was consistent and in agreement with his first declara-
`tion.
`
`Deposition:
`Aug. 10, 2005: Dr. Sechen was deposed on the July 21, 2005 declaration. Rep-
`resenting attorney: Mark Miller.
`
`Deposition:
`Dec. 16, 2005: Dr. Sechen was deposed on the June 10, 2005 declaration and on
`the supplemental declaration of July 13, 2005. Representing attorney: Mark Mil-
`ler.
`
`
`Settled after court made several rulings in Magma’s favor
`Started January 2005; Ended January 2006
`
`Trade Secret Misappropriation and Patent Enforcement
`Susman Godfrey
`UniRAM Technology vs. Monolithic System Technology and TSMC
`3 Expert Reports, 1 Declaration and 2 Depositions, and 2 trial testimonies for
`UniRAM.
`
`Expert Report:
`May 19, 2005: Expert report covered claim construction issues
`
`Declaration:
`
`

`

`May 19, 2005: Declaration in support of plaintiff UniRAM’s response to
`TSMC’s motion for summary judgment of inequitable conduct. (Subject of the
`2nd trial testimony.)
`
`Expert Report:
`May 31, 2007: Expert report that concluded that the UniRAM trade secrets were
`not and are not generally known, and that the UniRAM trade secrets created sig-
`nificant value for the defendants.
`
`Expert Rebuttal Report:
`Expert rebuttal report filed on June 13, 2007.
`
`Deposition:
`June 21, 2005: Deposition concerning expert report of May 19, 2005. Repre-
`senting attorney: Russ Chorush.
`
`Deposition:
`June 28, 2007: Deposition regarding expert report of May 31, 2007 and to a
`lesser degree the May 19, 2005 declaration. Representing attorney: Russ Cho-
`rush.
`
`Trial Testimony:
`September 2007 trial concerning Dr. Sechen’s expert report of May 31, 2007.
`Representing attorneys: Russ Chorush (Heim, Payne and Chorush) and Joseph
`Grinstein (Susman Godfrey).
`
`Trial Testimony:
`January 2008 regarding my declaration of May 19, 2005. Representing attorneys:
`Russ Chorush (Heim, Payne and Chorush) and Joseph Grinstein (Susman God-
`frey). The presiding judge specifically commented on Dr. Sechen’s credibility in
`his final judgment.
`
`
`
`$32 million judgment for UniRAM
`Started February 2005; Ended January 15, 2008
`
`Patent validity and infringement (both to PTO and trial)
`Squire, Sanders and Dempsey (Hitachi)
`Translogic vs. Hitachi
`4 expert reports, 2 declarations, 1 deposition and trial testimony for Hitachi
`
`Expert Disclosure Statement:
`Expert disclosure statement of July 25, 2003.
`Dr. Sechen was retained by Squire, Sanders & Dempsey LLP, counsel for de-
`fendants Hitachi, Ltd., Hitachi America, Ltd. and Renesas Technology America,
`Inc. (collectively “Hitachi”) to compare claims of U.S. Patent No. 5,162,666
`(“the ‘666 Patent”) with certain technical references which were prior art to the
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`Disposition:
`Date:
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`

`‘666 Patent. Plaintiff Translogic Technology, Inc. (“Translogic”) asserted claims
`of the ‘666 Patent against Hitachi.
`
`Supplemental Expert Disclosure:
`Supplemental expert disclosure statement of September 19, 2003.
`Dr. Sechen was retained by Squire, Sanders & Dempsey LLP, counsel for de-
`fendants Hitachi, Ltd., Hitachi America, Ltd. and Renesas Technology America,
`Inc. (collectively “Hitachi”) to compare claims of U.S. Patent No. 5,162,666
`with certain technical references which were prior art. Dr. Sechen supplemented
`the Expert Disclosure Statement he previously submitted in this case based on
`his review of the Report and Recommendation of Special Master Regarding
`Claim Construction.
`
`Expert Disclosure Statement:
`Expert disclosure statement of February 9, 2004.
`Dr. Sechen was retained by Squire, Sanders & Dempsey LLP, counsel for de-
`fendants Hitachi, Ltd., Hitachi America, Ltd. and Renesas Technology America,
`Inc. (collectively “Hitachi”) to analyze certain circuits in Hitachi microproces-
`sors that Translogic Technology, Inc. (“TTI”) accuses of infringing Patent No.
`5,162,666 (“the ‘666 Patent”). Dr. Sechen was also asked to review aspects of
`the design and design process for these Hitachi products.
`
`Supplemental and Restated Expert Disclosure Statement:
`Supplemental and restated expert disclosure statement of September 20, 2004.
`Dr. Sechen was retained by Squire, Sanders & Dempsey LLP, counsel for de-
`fendants Hitachi, Ltd., Hitachi America, Ltd. and Renesas Technology America,
`Inc. (collectively “Hitachi”) to analyze certain circuits in Hitachi microproces-
`sors that Translogic Technology, Inc. (“TTI”) accuses of infringing Patent No.
`5,162,666 (“the ‘666 Patent”). Dr. Sechen was also asked to review aspects of
`the design and design process for these Hitachi products. This report supple-
`ments my earlier expert disclosure statement, however, it is written as a substi-
`tute for that earlier report. This revision now uses the multiplexer drawing con-
`vention used by Hitachi, which is different from the standard U.S. convention.
`
`Declaration in Opposition to Plaintiff’s Motion for Summary Judgment:
`Declaration in opposition to plaintiff’s motion for summary judgment, April
`2004. Dr. Sechen was asked to analyze certain circuits in Hitachi microproces-
`sors that Translogic Technology accused of infringing their patent No.
`5,162,666. Dr. Sechen was also asked to review aspects of the design and design
`process for these Hitachi products.
`
`Second Declaration in Opposition to Plaintiff’s Motion for Summary Judg-
`ment:
`Second declaration in opposition to plaintiff’s motion for summary judgment,
`September 20, 2004. Dr. Sechen was asked to analyze certain circuits in Hitachi
`microprocessors that Translogic Technology accused of infringing their patent
`No. 5,162,666. Dr. Sechen was also asked to review aspects of the design and
`design process for these Hitachi products.
`
`Deposition:
`
`

`

`Aug. 18, 2003: Dr. Sechen was deposed on all of the above-mentioned expert
`disclosures and declarations. Representing attorneys: Nathan Lane and David
`Elkins of Squire, Sanders and Dempsey, as well as Alan Loudermilk of
`Loudermilk Associates.
`
`Trial Testimony:
`January 2004: Representing attorneys: Nathan Lane and David Elkins of Squire,
`Sanders and Dempsey, as well as Alan Loudermilk of Loudermilk Associates.
`
`
`Concluded, PTO ruled in favor of Hitachi but court ruled in favor of Translogic.
`July 2003 to September 2004
`
`Trade Secret Theft
`Keker and Van Ness (Cadence)
`Cadence vs. Avanti
`Two Declarations and One Deposition for Cadence
`
`Declaration:
`Short declaration that verified and substantiated the findings of other Cadence
`experts.
`
`Declaration:
`Dr. Sechen submitted a very long reply declaration that compared an Avanti
`software product to a Cadence software product, and showing that the products
`were not in the public domain.
`
`Deposition:
`Deposition focused primarily on the reply declaration. Representing attorney:
`Michael Page.
`
`Concluded
`July 1995 to July 1996
`
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`Disposition:
`Date:
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`Expert Engagement:
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`Law Firm:
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`Date:
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`

`

`Graduated Ph.D. Students
`1. Kai-Win Lee (Yale May 1990) “Global Routing of Row-Based Integrated Circuits”.
`2. Dahe Chen (Yale May 1992) “Mickey: A Graph-Based Macro-Cell Global Router”.
`3. Mark Chiang (Yale May 1992) “A Perturbation Approach to the Symbolic Analysis of An-
`alog Circuits”.
`4. William Swartz (Yale May 1993) “Automatic Layout of Analog and Digital Mixed
`Macro/Standard Cell Integrated Circuits”.
`5. Ted Stanion (Yale May 1994) “Boolean Algorithms for Combinational Synthesis and Test
`Generation”.
`6. Kalapi Roy (University of Washington June 1994) “A Timing-Driven Multi-Way Partition-
`ing System for Integrated Circuits and Multi-Chip Systems”.
`7. Jer-Jaw Hsu (University of Washington December 1994) “Fully Symbolic Analysis of Large
`Analog Integrated Circuits”.
`8. Wern-Jieh Sun (University of Washington December 1994) “Effective and Efficient Place-
`ment for Very Large Integrated Circuits”.
`9. Qicheng Yu (University of Washington March 1995) “Approximate Symbolic Analysis of
`Large Analog Integrated Circuits”.
`10. Bingzhong David Guan (University of Washington August 1996) “Automatic Layout Gen-
`eration of Static CMOS Combinational Cells and Blocks”.
`11. Eugene Liu (University of Washington, December 1997) “Global Routing and Pin Assign-
`ment for Multi-layer Chip-level Layout”.
`12. Hsiao-Ping Tseng (University of Washington, December 1997) “Detailed Routing Algo-
`rithms for VLSI Circuits”.
`13. Gin Yee (University of Washington, June 1999) “Dynamic Logic Design and Synthesis Us-
`ing Clock-Delayed Domino”.
`14. Tyler Thorp (University of Washington, December 1999), “Design and Synthesis of Dy-
`namic Circuits”.
`15. Tatjana Serdar (University of Washington, December 2000), “Automatic Datapath Tile
`Placement and Routing”.
`16. Jovanka Ciric (University of Washington, August 2001), “Boolean Matching and Level-
`Based Technology Mapping”.
`17. Yi Han (University of Washington, December 2004), “A High-Performance CMOS Pro-
`grammable Logic Core for System-on-Chip Applications”.
`18. Hiran Tennakoon (University of Washington, August 2005), “Efficient and Accurate Gate
`Sizing With Piecewise Convex Delay Models”.
`19. Miodrag Vujkovic (University of Washington, March 2006), “Efficient Fully-Automated,
`Refinement-Based Power-Delay Optimization Design Flow for Standard Cell Designs”.
`20. Kian Hour (Alfred) Chong (University of Washington, June 2006), “Self-Calibrating Differ-
`ential Output Prediction Logic”.
`21. Xinyu (Sunny) Guo (University of Washington, June 2006), “ A High-Throughput Divider
`Based on Output Prediction Logic”.
`22. Sheng Sun (University of Washington, August 2006), “High Performance and Energy Effi-
`cient Adder Design”.
`23. Mohammad Rahman (UT-Dallas, December 2011), “Power and Leakage Minimization for
`Digital ICs”.
`24. Chiu-Wei Pan (UT-Dallas, August 2012), “High Speed and Power Efficient Compression of
`Partial Products”.
`25. Zhao Wang (UT-Dallas, October 2012), “Accurate Wire Endpoint Delay Estimation”.
`26. Akshay Sridharan (UT-Dallas, October 2015), “STARK: Synchronous to Asynchronous Re-
`design Kit”.
`27. Anitha Yella (UT-Dallas, January 2016), “Power Optimization in ICs”.
`
`

`

`28. Meisam Roshan (UT-Dallas, September 2016), “A MEMS-Assisted Dual-Resonator Tem-
`perature-to-Digital Converter”.
`29. Huihua (Helen) Huang (UT-Dallas, May 2018), “A 0.1ps Resolution Coarse-Fine Time-to-
`Digital Converter with 2.21ps Single-Shot Precision”.
`30. Jingxiang (Amelie) Tian (UT-Dallas, December 2019), “Transistor-level Programmable
`Fabric”.
`31. Bo Hu (UT-Dallas, March 2021), “Thermal-Aware Placement and High Level Synthesis For
`Hardware Security”.
`32. Lubaba Nahar, (UT-Dallas, July 2022), “CAD Tools for PCB Reverse Engineering and IC
`Interconnect”.
`33. Qiongdan (Olivia) Huang, (UT-Dallas, July 2022), “Toward Accurate Timing Analysis of
`Transistor-Level Programmable Fabric”.
`34. Xiangyu Xu, (UT-Dallas December 2022), “Routing Methods for Transistor-level Program-
`mable Fabrics”.
`
`
`
`
`
`
`
`
`Current Ph.D. Students
`1. Vibhav Kumarswami Salimath, Ph.D. expected 12/23
`2. Apurva Jain, Ph.D. expected 12/23
`3. Thomas Broadfoot, Ph.D. expected 12/23
`4. Jinkun Feng, Ph.D. expected 06/26
`5. Amir Hossein Torabi, Ph.D. expected 05/27
`
`
`
`
`
`
`
`Teaching Activities
` Yr
`Qtr
`Course
`1992 Aut
`EE538
`1993 Win
`EE356
`1993 Spr
`EE535
`1993 Sum EE332
`1993 Aut
`EE538
`1993 Aut
`EE332
`1994 Win
`EE433
`1994 Spr
`EE476
`1994 Aut
`EE538
`1994 Aut
`EE433
`1995 Win
`EE476
`1995 Spr
`EE473
`1995 Aut
`EE476
`1996 Win
`EE535
`1996 Spr
`EE538
`1996 Aut
`EE476
`1997 Win
`EE477
`1997 Win
`EE541
`
`Brief Title, Credits, #students
`Auto Layout, 4 credits, 20 students
`Analog ICs, 4 credits, 55 students
`VLSI Design, 4 credits, 25 students
`Analog ICs, 5 credits, 35 students
`Auto Layout, 4 credits, 15 students
`Analog ICs, 5 credits, 40 students
`Analog MOS ICs, 4 credits, 65 students
`Digital ICs, 5 credits, 55 students
`Auto Layout, 4 credits, 15 students
`Analog MOS ICs, 4 credits, 55 students
`Digital ICs, 5 credits, 85 students
`Adv. Analog MOS, 5 credits, 45 students
`Digital ICs, 5 credits, 85 students
`VLSI Design, 4 credits, 55 students
`Auto Layout, 4 credits, 15 students
`Digital ICs, 5 credits, 125 students
`Custom Dig ICs, 4 credits, 45 students
`Auto Layout, 4 credits, 20 students
`
`Stud. Opin. Survey
`4.38/4.08
`3.21/3.00
`4.27/4.47
`3.57/3.48
`3.60/3.50
`3.93/3.90
`3.96/4.08
`3.89/3.89
`3.63/3.63
`4.32/4.30
`3.75/3.85
`3.53/3.59
`4.40/4.20
`4.10/4.00
`4.30/4.50
`3.40/3.40
`4.30/4.10
`4.70/4.70
`
`

`

`VLSI Design, 4 credits, 20 students
`EE535
`1997 Spr
`Digital ICs, 5 credits, 60 students
`EE476
`1997 Aut
`Custom Dig ICs, 4 credits, 60 students
`1998 Win EE477
`Digital ICs, 5 credits, 60 students
`1998 Spr
` EE476
`Digital VLSI Design, 4 credits, 35 stud.
`1998 Spr
` EE535
`Digital ICs, 5 credits, 35 students
`1998 Aut
` EE476
`Custom Dig ICs, 4 credits, 55 students
`1999 Win EE477
`Digital VLSI Design, 4 credits, 35 stud.
`1999 Spr
` EE535
`Digital ICs, 5 credits, 50 students
`1999 Aut
` EE476
`Custom Dig ICs, 4 credits, 55 students
`2000 Win EE477
`Digital VLSI Design, 4 credits, 35 stud.
`2000 Spr
` EE535
`Digital ICs, 5 credits, 125 students
`2000 Aut
` EE476
`VLSI II, 5 credits, 75 students
`2001 Win EE477
`VLSI II, 5 credits, 25 students
`2001 Win EE525
`VLSI III, 4 credits, 50 students
`2001 Spr
` EE526
`VLSI I, 5 credits, 150 students
`2001 Aut
` EE476
`VLSI II, 5 credits, 75 students
`2002 Win EE477
`VLSI II, 5 credits, 25 students
`2002 Win EE525
`VLSI III, 4 credits, 50 students
`2002 Spr
` EE526
`VLSI I, 5 credits, 150 students
`2002 Aut
` EE476
`VLSI II, 5 credits, 55 students
`2003 Win EE477
`VLSI II, 5 credits, 25 students
`2003 Win EE525
`VLSI III, 4 credits, 32 students
`2003 Spr
` EE526
`VLSI I, 5 credits, 30 students
`2003 Aut
` EE476
`VLSI II, 5 credits, 12 students
`2004 Win EE477
`VLSI II, 5 credits, 7 students
`2004 Win EE525
`VLSI III, 4 credits, 12 students
`2004 Spr
` EE526
`VLSI I, 5 credits, 65 students
`2004 Aut
` EE476
`2005 Fall
` EE6325 VLSI Design, 3 units, 42 students
`2006 Spr
` EE7325 Advanced VLSI Design, 3 units, 20 students
`2006 Fall
` EE6325 VLSI Design, 3 units, 66 students
`2007 Spr
` EE7325 Advanced VLSI Design, 3 units, 15 students
`2007 Fall
` EE6325 VLSI Design, 3 units, 40 students
`2008 Spr
` EE4325
`Introduction to VLSI Design, 40 students
`2008 Spr
` EE7325 Advanced VLSI Design, 3 units, 19 students
`2008 Sum EE6325 VLSI Design, 3 units, 36 students
`2008 Fall
` EE6325 VLSI Design, 3 units, 40 students
`2009 Spr
` EE4325
`Introduction to VLSI Design, 22 students
`2009 Spr
` EE7325 Advanced VLSI Design, 3 units, 37 students
`2009 Sum EE6325 VLSI Design, 3 units, 17 students
`2009 Fall
` EE6325 VLSI Design, 3 units, 67 students
`2010 Spr
` EE4325
`Introduction to VLSI Design, 25 students
`2010 Spr
` EE7325 Advanced VLSI Design, 3 units, 35 students
`2010 Sum EE6325 VLSI Design, 3 units, 17 students
`2010 Sum EE3320 Digital Circuits, 3 units, 17 students
`2010 Fall
` EE6325 VLSI Design, 3 units, 77 students
`2011 Spr
` EE4325
`Introduction to VLSI Design, 37 students
`2011 Spr
` EE7325 Advanced VLSI Design, 3 units, 17 students
`2011 Sum EE6325 VLSI Design, 3 units, 16 students
`2011 Sum EE3320 Digital Circuits, 3 units, 26 students
`2011 Fall
` EE6325 VLSI Design, 3 units, 91 students
`
`3.83/4.00
`3.88/3.89
`3.66/3.61
`3.39/3.50
`3.57/3.94
`4.15/4.50
`4.00/3.94
`3.79/4.13
`4.70/4.70
`4.53/4.27
`4.35/4.44
`4.20/4.19
`4.30/4.37
`4.25/4.50
`4.35/4.50
`4.1/4.2
`4.1/4.1
`4.1/4.1
`3.6/3.3
`3.7/3.6
`3.4/3.8
`3.6/3.3
`3.3/3.5
`4.5/4.6
`3.2/3.7
`2.2/2.2
`3.2/3.2
`3.8/3.9
`4.4/4.6
`4.5/4.3
`4.4/4.2
`4.5/4.2
`4.8/4.6
`3.5/3.4
`4.6/4.4
`4.0/3.7
`4.1/4.1
`4.2/3.9
`3.7/3.6
`4.1/4.0
`4.3/4.0
`4.6/4.5
`4.4/4.4
`4.7/4.5
`4.1/3.8
`4.4/4.2
`4.0/4.1
`4.2/4.2
`4.14
`4.13
`4.73
`
`
`
`
`
`
`
`

`

`Introduction to VLSI Design, 27 students
` EE4325
`2012 Spr
` EE7325 Advanced VLSI Design, 3 units, 17 students
`2012 Spr
`2012 Sum EE6325 VLSI Design, 3 units, 35 students
`2012 Sum EE3311
`Electronic Circuits, 3 units, 22 students
`2012 Fall
` EE6325 VLSI Design, 3 units, 144 students
`2013 Spr
` EE6325 VLSI Design, 3 units, 41 students
`2013 Spr
` EE4325
`Introduction to VLSI Design, 7 students
`2013 S