UNITED STATES PATENT AND TRADEMARK OFFICE
`__________________________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`__________________________
`
`INTEL CORPORATION,
`Petitioner
`v.
`BiTMICRO LLC,
`Patent Owner.
`
`___________________
`
`IPR2023-00782
`U.S. Patent No. 8,010,740
`_____________________
`
`DECLARATION OF DR. CARL SECHEN, PH.D.
`IN SUPPORT OF INTER PARTES REVIEW OF U.S. 8,010,740
`
`INTEL-1003
`8,010,740
`
`

`

`I. 
`
`II. 
`
`U.S. Patent 8,010,740
`IPR2023-00782
`
`
`TABLE OF CONTENTS
`INTRODUCTION ........................................................................................... 1 
`A.  Qualifications and Expertise ................................................................. 3 
`B. 
`Compensation ........................................................................................ 6 
`C. 
`Previous Expert Witness Experience .................................................... 7 
`D.  Materials Considered and Basis of Opinions ........................................ 7 
`E. 
`Level of Ordinary Skill in the Art ....................................................... 11 
`F. 
`Understanding of Relevant Legal Principles ....................................... 12 
`TECHNOLOGY OVERVIEW ...................................................................... 15 
`A. 
`Flash Memory ...................................................................................... 15 
`B. 
`Address Mapping ................................................................................ 17 
`C. 
`Large-Capacity Flash Memory Systems ............................................. 27 
`D. 
`Interleaving .......................................................................................... 30 
`III.  THE CHALLENGED ’740 PATENT ........................................................... 33 
`A. 
`Summary of the ’740 Patent ................................................................ 33 
`B. 
`Prosecution History of the ’740 Patent ............................................... 36 
`C. 
`Claim Construction ............................................................................. 38 
`1. 
`“LBA” ....................................................................................... 39 
`2. 
`“LBA set” .................................................................................. 39 
`IV.  GROUND 1: CLAIMS 1 AND 14 ARE OBVIOUS OVER
`BRUCE ’006 .................................................................................................. 41 
`A.  Overview of Bruce ’006 ...................................................................... 41 
`B. 
`Independent Claim 1 ........................................................................... 44 
`
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`- i -
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`

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`U.S. Patent 8,010,740
`IPR2023-00782
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`1. 
`Claim 1 Preamble ...................................................................... 45 
`Claim 1, Limitation [A] ............................................................ 58 
`2. 
`Claim 1, Limitation [B] ............................................................. 66 
`3. 
`Claim 1, Limitation [C] ............................................................. 72 
`4. 
`Dependent Claim 14 ............................................................................ 76 
`C. 
`V.  GROUND 2: CLAIMS 1 AND 14 ARE OBVIOUS OVER
`THE COMBINATION OF BRUCE ’006 AND SBC ................................... 78 
`A.  Overview of SBC ................................................................................ 78 
`B.  Motivation to Combine Bruce ’006 with SBC .................................... 80 
`C. 
`Independent Claim 1 ........................................................................... 87 
`1. 
`Claim 1 Preamble ...................................................................... 87 
`2. 
`Claim 1, Limitation [A] ............................................................ 93 
`3. 
`Claim 1, Limitation [B] ............................................................. 93 
`4. 
`Claim 1, Limitation [C] ............................................................. 94 
`D.  Dependent Claim 14 ............................................................................ 98 
`VI.  GROUND 3: CLAIMS 1, 9-15, 32, AND 34 ARE OBVIOUS
`OVER THE COMBINATION OF BRUCE ’006 AND BRUCE
`’251 ................................................................................................................ 99 
`A.  Overview of Bruce ’251 ...................................................................... 99 
`B.  Motivation to Combine Bruce ’006 with Bruce ’251 .......................101 
`C. 
`Independent Claim 1 .........................................................................112 
`1. 
`Claim 1 Preamble ....................................................................112 
`2. 
`Claim 1, Limitations [A]-[C] ..................................................115 
`D.  Dependent Claim 9 ............................................................................115 
`
`
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`- ii -
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`

`

`K. 
`
`U.S. Patent 8,010,740
`IPR2023-00782
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`E. 
`Dependent Claim 10 ..........................................................................122 
`Dependent Claim 11 ..........................................................................123 
`F. 
`G.  Dependent Claim 12 ..........................................................................123 
`H.  Dependent Claim 13 ..........................................................................123 
`I. 
`Dependent Claim 14 ..........................................................................124 
`J. 
`Dependent Claim 15 ..........................................................................124 
`1. 
`Claim 15, Limitation [A] ........................................................124 
`2. 
`Claim 15, Limitation [B] .........................................................126 
`Independent Claim 32 .......................................................................128 
`1. 
`Claim 32 Preamble ..................................................................128 
`2. 
`Claim 32, Limitation [A] ........................................................133 
`3. 
`Claim 32, Limitation [B] .........................................................133 
`4. 
`Claim 32, Limitation [C] .........................................................134 
`5. 
`Claim 32, Limitation [D] ........................................................135 
`6. 
`Claim 32, Limitation [E] .........................................................136 
`Dependent Claim 34 ..........................................................................137 
`L. 
`VII.  GROUND 4: CLAIMS 1, 9-15, 32, AND 34 ARE OBVIOUS
`OVER THE COMBINATION OF BRUCE ’006, BRUCE ’251,
`AND SBC ....................................................................................................138 
`A.  Motivation to Combine Bruce ’006, Bruce ’251, and SBC ..............138 
`B. 
`Independent Claim 1 .........................................................................141 
`1. 
`Claim 1 Preamble ....................................................................141 
`Dependent Claims 9-15 .....................................................................145 
`
`C. 
`
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`- iii -
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`

`

`U.S. Patent 8,010,740
`IPR2023-00782
`
`Independent Claim 32 .......................................................................146 
`1. 
`Claim 32 Preamble ..................................................................146 
`2. 
`Claim 32, Limitations [A]-[D] ................................................147 
`3. 
`Claim 32, Limitation [E] .........................................................147 
`Dependent Claim 34 ..........................................................................148 
`
`
`D. 
`
`E. 
`
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`
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`- iv -
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`

`

`INTRODUCTION
` My name is Carl Sechen, and I have been retained by Perkins Coie
`
`U.S. Patent 8,010,740
`IPR2023-00782
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`
`I.
`
`LLP on behalf of Intel Corporation (“Intel” or “Petitioner”) in the above-
`
`referenced inter partes review proceeding to evaluate United States Patent No.
`
`8,010,740 to Arcedera et al. (“the ’740 Patent”) against certain references that
`
`predate the earliest possible priority date of June 8, 2006 (the “Earliest Priority
`
`Date”) for the ’740 Patent. The ’740 Patent is attached as Exhibit INTEL-1001 to
`
`Intel’s Petition for Inter Partes Review of U.S. Patent No. 8,010,740 based on
`
`United States Patent No. 6,000,006 (“Bruce ’006”), United States Patent No.
`
`5,822,251 (“Bruce ’251”), and American National Standard for Information
`
`Technology - SCSI-3 Block Commands (“SBC”). I am informed that Intel seeks
`
`review of claims 1, 9-15, 32, and 34 of the ’740 Patent (collectively, the
`
`“challenged claims”). I have also been informed that the ’740 Patent is currently
`
`assigned to BiTMICRO LLC (“BiTMICRO” or “Patent Owner”). As detailed in
`
`this declaration, it is my opinion that each of the challenged claims is disclosed
`
`and/or rendered obvious by prior art references that predate the Earliest Priority
`
`Date.
`
`
`
`I am over 18 years of age. I have personal knowledge of the facts
`
`stated in this Declaration and if requested by the Patent Trial and Appeal Board
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`1
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`

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`(“PTAB” or “Board”), I am prepared to testify competently about my opinions
`
`U.S. Patent 8,010,740
`IPR2023-00782
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`
`expressed herein.
`
`
`
`I have reviewed and am familiar with the specification and the claims
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`of the ’740 Patent. In general, I will cite to the specification of a United States
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`patent using the following formats: (Patent No. at Col:Line Number(s)) or (Patent
`
`Publication No. at Paragraph Number(s)). For example, the citation (’740 Patent at
`
`1:1-10) points to the ’740 Patent specification at column 1, lines 1-10. Also, for
`
`convenience, I use italics to denote limitations from the challenged claims.
`
`
`
`All of the opinions contained in this Declaration are based on the
`
`documents I reviewed and my knowledge and professional judgment. In forming
`
`the opinions expressed in this Declaration, I reviewed the documents listed
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`below. I have also reviewed and am familiar with the other materials referred to in
`
`this Declaration. To the best of my knowledge, the documents mentioned above
`
`are true and accurate copies of what they purport to be and are the kinds of
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`materials that an individual with expertise in this field at the relevant time period
`
`would reasonably rely on in formulating opinions, such as those set forth in this
`
`declaration.
`
`
`
`I have been asked to provide my technical opinions regarding how a
`
`person of ordinary skill in the art (“POSITA”) would have understood the claims
`
`of the ’740 Patent at the time of the alleged invention. For purposes of whether the
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`2
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`

`

`U.S. Patent 8,010,740
`IPR2023-00782
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`teachings of the prior art anticipate or render obvious the claims of the ’740 Patent,
`
`I have been asked to assume the date of June 8, 2006, the filing date of the earliest
`
`patent in the priority chain of the ’740 Patent, for the analysis in this document. I
`
`refer to that date as the Earliest Priority Date. I have also been asked to provide
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`my technical opinions on how concepts in the ’740 Patent specification relate to
`
`claim limitations of the ’740 Patent. In reaching the opinions provided herein, I
`
`have considered the ’740 Patent, its prosecution history, and the references cited
`
`above and have drawn as appropriate on my own education, training, research,
`
`knowledge, and personal and professional experience.
`
`A.
`
`Qualifications and Expertise
`I am an expert in the field of memory system design. In formulating
`
`my opinions, I have relied on my knowledge, training, and experience in the
`
`relevant field, which I will summarize briefly. A more detailed summary of my
`
`background, education, experience, and publications is set forth in my curriculum
`
`vitae (“CV”), which is attached as Exhibit INTEL-1004 to the Petition. My CV
`
`also includes a list of all other cases in which, during the previous 4 years, I
`
`testified as an expert at trial or by deposition.
`
`
`
`I earned my B.E.E. in Electrical Engineering from the University of
`
`Minnesota in 1975, followed by my M.S. in Electrical Engineering from the
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`3
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`

`

`Massachusetts Institute of Technology in 1977 and then my Ph.D. in Electrical
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`U.S. Patent 8,010,740
`IPR2023-00782
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`Engineering from the University of California, Berkeley in 1986.
`
`
`
`I have been a Professor of Electrical Engineering for 36 years. Since
`
`August 15, 2005, I have been a Professor of Electrical and Computer Engineering
`
`at the University of Texas at Dallas. From July 1992 to August 14, 2005, I served
`
`as a Professor of Electrical Engineering at the University of Washington. From
`
`July 1986 through June 1992, I served as an Assistant Professor and then Associate
`
`Professor of Electrical Engineering at Yale University.
`
`
`
`Over these years, my research has focused on the design and
`
`computer-aided design of digital integrated circuits, including the design of
`
`dynamic random-access memory (“DRAM”) and static random-access memory
`
`(“SRAM”) modules. I have also designed several chips that included various types
`
`of embedded DRAM (eDRAM). In this research work, I have designed multiple
`
`sense amplifier circuits for the various DRAMs, embedded DRAMs, and SRAMs.
`
`I have authored or coauthored over 200 papers and one book, the majority of which
`
`concern digital integrated circuit design and memory design.
`
` As a professor, I have developed and taught numerous courses,
`
`including several courses that teach digital integrated circuit design and memory
`
`design, including extensive coverage of flash and non-volatile memory design. I
`
`have taught these courses continuously for the past 27 years. I have taught digital
`
`4
`
`

`

`integrated circuit design and memory design, including flash and non-volatile
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`U.S. Patent 8,010,740
`IPR2023-00782
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`
`memory design, to undergraduate and graduate students at the University of
`
`Washington and at the University of Texas at Dallas. NAND-Flash memory
`
`design is taught in detail, including both SLC and MLC variants.
`
`
`
`I was elected a Fellow of the Institute of Electrical and Electronics
`
`Engineers (“IEEE”) in 2002 for contributions to placement and routing of ASICs.
`
`IEEE is the leading professional association for electrical engineers. The Board of
`
`Directors of the IEEE awards the rank of “Fellow” to individuals with an
`
`extraordinary record of accomplishments in any of the IEEE fields of interest. The
`
`total number of IEEE members who can be named Fellows in any one year cannot
`
`exceed one-tenth of one percent of the total voting IEEE membership.
`
`
`
`I received several research and teaching awards during my career. I
`
`received the Semiconductor Research Corporation’s Inventor’s Recognition Award
`
`in 1988 and in 2001. I also received the Technical Excellence Award from the
`
`Semiconductor Research Corporation in 1994. While serving as Professor at the
`
`University of Washington, I received the Outstanding Research Advisor award
`
`from the Department of Electrical Engineering in 2002. In 2008, I received the
`
`Distinguished Teacher of the Year Award from the Department of Electrical
`
`Engineering at the University of Texas at Dallas. I also received the Distinguished
`
`5
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`

`

`Teaching Award for the Erik Johnson School of Engineering and Computer
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`U.S. Patent 8,010,740
`IPR2023-00782
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`Science in 2014.
`
` Over the years, I have also received funding to conduct research in
`
`computer circuits and memory designs, including area-efficient and reliable
`
`embedded DRAM and SRAM design. Together with my graduate students, I have
`
`designed and fabricated various types of computational VLSI chips.
`
`
`
`I am a co-inventor on four issued patents directed to transistor and
`
`computational logic technologies. Three of the patents concern transistor-level
`
`field programmable logic.
`
`B. Compensation
`
`In connection with my work as an expert, I am being compensated at
`
`an hourly rate of $400 for consulting services including time spent testifying at any
`
`hearings that may be held. I am also being reimbursed for reasonable and
`
`customary expenses associated with my work in this case. I receive no other form
`
`of compensation related to this case. My compensation is not dependent or
`
`otherwise contingent upon the specifics of my testimony or the outcome of this
`
`action.
`
`6
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`

`

`Previous Expert Witness Experience
` My CV attached as Exhibit INTEL-1004 to the Petition contains a list
`
`U.S. Patent 8,010,740
`IPR2023-00782
`
`
`C.
`
`of cases in which I have testified at trial, hearing, or by deposition within the
`
`preceding four years.
`
`D. Materials Considered and Basis of Opinions
`
`In forming the opinions set forth in this Declaration, I have considered
`
`and relied upon my education, experience, and knowledge of the relevant fields. I
`
`have also reviewed and considered the ’740 Patent and its prosecution history
`
`(“’740 FH”). The ’740 Patent and its prosecution history are attached as exhibits
`
`INTEL-1001 and INTEL-1002, respectively, to the above-referenced IPR petition.
`
`Additionally, I have relied on and reviewed the following documents and materials
`
`cited in this Declaration, all of which are attached as exhibits to the above-
`
`referenced IPR petitions.
`
`Exhibit
`1001
`
`Reference
`U.S. Patent No. 8,010,740 to Arcedera et al. (“’740 Patent”)
`
`1002
`
`1004
`
`1005
`
`1006
`
`File History of the ’740 Patent (“’740 FH”)
`
`CV of Dr. Carl Sechen, Ph.D.
`
`U.S. Patent No. 6,000,006 to Bruce et al. (“Bruce ’006”)
`
`U.S. Patent No. 5,822,251 to Bruce et al. (“Bruce ’251”)
`
`7
`
`

`

`U.S. Patent 8,010,740
`IPR2023-00782
`
`
`Exhibit
`1007
`
`Reference
`“American National Standard for Information Technology - SCSI-
`3 Block Commands (SBC),” American National Standards
`Institute (1998) (“SBC”)
`
`1008
`
`1009
`
`1010
`
`1011
`
`1012
`
`1013
`
`1014
`
`1015
`
`1016
`
`1017
`
`1018
`
`United States District Courts — National Judicial Caseload
`Profile
`
`The IEEE Standard Dictionary of Electrical and Electronics
`Terms (6th Ed. 1996)
`
`U.S. Patent No. 5,519,844 to Stallmo (“Stallmo”)
`
`Microsoft Press Computer Dictionary (3rd Ed. 1999)
`
`U.S. Patent No. 7,299,316 to Chou et al. (“Chou”)
`
`Summons with Proof of Service, BiTMICRO LLC v. Intel Corp.,
`No. 6:22-cv-00335-ADA (W.D. Tex.), Dkt. 9
`
`Declaration of June Munford in Support of Petition
`
`Claim Construction Order and Memorandum In Support Thereof,
`BiTMICRO LLC v. Kioxia America, Inc., Kioxia Corporation, No.
`6:22-cv-00331-ADA (W.D. Tex.), Dkt. 54
`
`U.S. Patent App. Pub. No. 2003/0163630 to Aasheim et al.
`(“Aasheim”)
`
`Wu et al., An Efficient B-Tree Layer for Flash-Memory Storage
`Systems, RTCSA 2003: Real-Time and Embedded Computing
`Sys. and Applications: 9th Int’l. Conf., Revised Papers, Vol. 2968,
`pp. 409-430 (February 18-20, 2004) (“Wu”)
`
`Gal et al., Algorithms and Data Structures for Flash Memories,
`ACM Computing Survs., Vol. 37, No. 2, pp. 138-163 (June 2005)
`(“Gal”)
`
`8
`
`

`

`U.S. Patent 8,010,740
`IPR2023-00782
`
`
`Exhibit
`1019
`
`Reference
`Kim et al., A Space-Efficient Flash Translation Layer for
`CompactFlash Systems, IEEE Transactions on Consumer Elecs.,
`Vol. 48, No. 2, pp. 366-375 (May 2002) (“Kim”)
`
`1020
`
`1021
`
`1022
`
`1023
`
`1024
`
`1025
`
`1026
`
`1027
`
`1028
`
`1029
`
`Pavan et al., Flash Memory Cells—An Overview, Proc. of the
`IEEE, Vol. 85, No. 8, pp. 1248-1271 (1997) (“Pavan”)
`
`Yim, A Novel Memory Hierarchy for Flash Memory Based
`Storage Systems, JSTS: Journal of Semiconductor Technology
`and Science, Vol. 5, No. 4, pp. 262-269 (2005) (“Yim”)
`
`U.S. Patent No. 5,479,638 to Assar et al. (“Assar”)
`
`U.S. Patent No. 7,000,063 to Friedman et al. (“Friedman”)
`
`Huffman et al., A Standard Interface for NAND Flash, Intel
`Developer Forum (March 7, 2006) (“Huffman”)
`
`Chang et al., An Adaptive Striping Architecture for Flash Memory
`Storage Systems of Embedded Systems, Proceedings. Eighth IEEE
`Real-Time and Embedded Tech. and Applications Symp. pp. 187-
`196 (September 2002) (“Chang”)
`
`Park et al., A High Performance Controller for NAND Flash-
`based Solid State Disk (NSSD), 2006 21st IEEE Non-Volatile
`Semiconductor Memory Workshop, pp. 17-20 (May 15, 2006)
`(“Park”)
`
`U.S. Patent No. 7,506,098 to Arcedera et al. (“Arcedera”)
`
`Tsur, Trends in COTS Storage Solutions for Data Acquisition
`Systems, Airborne Intelligence, Surveillance, Reconnaissance
`(ISR) Systems and Applications III, Vol. 6209, pp. 45-55 SPIE
`(May 5, 2006) (“Tsur”)
`
`Ryu et al., Improvement of Space Utilization in NAND Flash
`Memory Storages, Embedded Software and Systems: Second
`International Conference, ICESS 2005, Xi’an, China, Proceedings
`2, pp. 766-775 (December 16-18, 2005) (“Ryu”)
`
`9
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`

`

`U.S. Patent 8,010,740
`IPR2023-00782
`
`
`Exhibit
`1030
`
`Reference
`Chung et al., LSTAFF: System Software For Large Block Flash
`Memory, Lecture Notes in Computer Science, 3398 pp. 704-710
`(2005) (“Chung”)
`
`1031
`
`1032
`
`1033
`
`U.S. Patent No. 5,404,485 to Ban (“Ban”)
`
`Peterson, Designing A VME-To-SCSI Adapter, The System
`Engineers Handbook, pp. 311-319 (1992) (“Peterson”)
`
`American National Standards Institute (ANSI) X3.131-1986,
`Small Computer System Interface (SCSI) (1986) (“SCSI-1986”)
`
`1034
`
`U.S. Patent No. 6,381,677 to Beardsley et al. (“Beardsley”)
`
`
`
`
`
`I reserve the right to supplement this Declaration and rely upon any
`
`additional information, deposition testimony, documents, or materials that may be
`
`provided to me or that are relied upon by any of Respondent’s experts or witnesses.
`
`
`
`I also reserve my right to supplement this Declaration and rely upon
`
`additional information that becomes available to me.
`
`
`
`In connection with live testimony in this proceeding, should I be
`
`asked to provide it, I may rely on visual aids and demonstratives to demonstrate the
`
`bases of my opinions, such as claim charts, patent drawings, excerpts from patent
`
`specifications, file histories, interrogatory responses, deposition transcripts and
`
`exhibits, as well as charts, diagrams, videos and animated or computer-generated
`
`video. The demonstrative exhibits I may use to accompany any testimony I may
`
`give may also include documents, testimony, and other evidence cited in my
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`10
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`

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`Declaration, portions of such evidence, and other portions of my Declaration and
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`U.S. Patent 8,010,740
`IPR2023-00782
`
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`the attached exhibits.
`
`E.
`
`
`
`Level of Ordinary Skill in the Art
`I am told that certain issues relating to the validity of the ’740 Patent
`
`must be judged from the perspective of a person of ordinary skill in the relevant
`
`art, as I discuss below. I have been asked to define the level of a “person of
`
`ordinary skill in the art” or “POSITA” at the time the alleged invention as claimed
`
`was made. In deciding the level of ordinary skill, I have considered the following
`
`factors, which I have been informed are relevant to the determination of ordinary
`
`skill in the art:
`
`
`
`
`
`
`
`
`
`
`
`the levels of education and experience of persons working in the field;
`
`the types of problems encountered in the art;
`
`the prior art solutions to these problems;
`
`the rapidity with which innovations are made; and
`
`the sophistication of the technology.
`
`
`
`In my opinion, for the purposes of the ’740 Patent, a POSITA, at the
`
`Earliest Priority Date (June 8, 2006), would have had at least a bachelor’s degree
`
`in electrical engineering or computer engineering and at least two years of
`
`experience in memory system design, including solid-state memory, or equivalent
`
`combined education, work, and/or experience.
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`11
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`

`

` My opinion below explains how a POSITA would have understood
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`U.S. Patent 8,010,740
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`the technology described in the references I have identified in this declaration as of
`
`the Earliest Priority Date.
`
`F. Understanding of Relevant Legal Principles
`
`I am not a lawyer and will not provide any legal opinions. Although I
`
`am not a lawyer, I have been advised that certain legal standards are to be applied
`
`by technical experts in forming opinions regarding the meaning and validity of
`
`patent claims.
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`
`
`I understand that a patent claim is invalid if it is anticipated or obvious
`
`in view of the prior art, and that a claim can be unpatentable even if all of the
`
`requirements of the claim cannot be found in a single prior-art reference. I further
`
`understand that invalidity of a claim requires that the claim be anticipated or
`
`obvious from the perspective of a person of ordinary skill in the art at the time the
`
`invention was made.
`
`
`
`I have been informed that a patent claim is invalid if it would have
`
`been obvious to a person of ordinary skill in the art. In analyzing the obviousness
`
`of a claim, I understand the following factors may be considered: (1) the scope and
`
`content of the prior art; (2) the differences between the prior art and the claims; (3)
`
`the level of ordinary skill in the art; and (4) any so called “secondary
`
`considerations” of non-obviousness if they are present. Such secondary
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`12
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`considerations include: commercial success of products covered by the patent
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`U.S. Patent 8,010,740
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`claims; a long-felt need for the invention; failed attempts by others to make the
`
`invention; copying of the invention by others in the field; unexpected results
`
`achieved by the invention as compared to the closest prior art; praise of the
`
`invention by the infringer or others in the field; the taking of licenses under the
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`patent by others; expressions of surprise by experts and those skilled in the art at
`
`the making of the invention; and the patentee proceeded contrary to the accepted
`
`wisdom of the prior art. I am not aware of any evidence of secondary
`
`considerations of non-obviousness relevant to the ’740 Patent. I reserve the right
`
`to supplement this Declaration if Patent Owner introduces evidence of secondary
`
`considerations of non-obviousness.
`
`
`
`I understand that to prove that prior art or a combination of prior art
`
`renders a patent obvious, it is necessary to:
`
`
`
`
`
`
`
`identify the particular references that, singly or in combination, make
`
`the patent obvious;
`
`specifically identify which elements of the patent claim appear in each
`
`of the asserted references; and
`
`explain why a person of ordinary skill in the art would have combined
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`the references, and how they would have done so, to create the
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`inventions claimed in the patent. I further understand that exemplary
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`rationales that may support a conclusion of obviousness include:
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`combining prior art elements according to known methods to
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`yield predictable results;
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`simple substitution of one known element for another to obtain
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`predictable results;
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`use of known technique(s) to improve similar devices (methods
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`or products) in the same way;
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`“obvious to try” – choosing from a finite number of identified,
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`predictable solutions with a reasonable expectation of success;
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`known work in one field of endeavor may prompt variations of
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`the work for use in either the same field or a different field based
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`on design incentives or other market forces if the variations are
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`predictable to a person of ordinary skill in the art; and
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`some teaching, suggestion, or motivating in the prior art that
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`would have led a person of ordinary skill in the art to modify the
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`prior art reference or to combine prior art reference teachings to
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`arrive at the claimed invention.
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`
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`I have been informed that, in considering obviousness, hindsight
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`reasoning derived from the patent-at-issue may not be used.
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`II. TECHNOLOGY OVERVIEW
`A.
`Flash Memory
` Rotating mechanical hard disk drives (“HDDs”) have been widely
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`used for persistent (i.e., non-volatile) storage in computing systems since their
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`introduction by IBM in 1956. HDDs, however, are mechanical devices with many
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`moving parts. As a result, they are large, slow, consume a lot of power, and prone
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`to failure. These characteristics reduce HDD’s suitability as a portable storage
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`medium.
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` Flash memory was first invented in the early 1980s by Japanese
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`engineer Masuoka Fujio as a technology that would replace existing data-storage
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`media such as HDDs. Like the HDD, flash memory is non-volatile. A
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`semiconductor-based non-volatile storage medium with no moving parts, flash
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`memory is smaller, hardier, and consumes less power than HDDs. Flash memory
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`has thus gained use in a wide range of applications, particularly those requiring
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`portability or high performance.
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` There are two types of flash memories: NOR and NAND. NOR flash
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`is better suited for random data access as it uses no shared components and
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`connects individual memory cells in parallel. NAND, on the other hand, is better
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`suited for serial data access as it stores data in “blocks” of “pages.” Bruce ’006 at
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`1:20; Bruce ’251 at 1:46; Chang at 1; Aasheim at ¶[0030]; Wu at 411. Toshiba
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`commercially launched the first NAND flash memory in 1987 and Intel introduced
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`U.S. Patent 8,010,740
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`the first commercial NOR type flash chip in 1988.
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` While flash memory is smaller, hardier, and consumes less power than
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`HDDs, flash memory does have two downsides as compared to HDDs. First, flash
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`memory must be erased before it can be rewritten, an attribute sometimes referred
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`to as “erase-before-write.” Bruce ’006 at 1:26-28, 5:60-61; Bruce ’251 at 1:53-54;
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`Chang at 1; Wu at 411-412; Aasheim at ¶¶[0033]-[0039]; Kim at 366; Yim at 262.
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`Erase operations are typically performed on regions of fixed size greater than are
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`required for read/write operations. Ryu at 768; Bruce ’006 at 1:28-31; Bruce ’251
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`at 1:53-57. For example, NAND flash—the most popular type of flash memory—
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`is read and written a page at a time but must be erased a block at a time. Yim at
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`262-263; Wu at 411.
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` Second, flash memory has a finite number of erase/write cycles,
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`meaning the memory cells will eventually “wear out.” Bruce ’006 at 1:34-36;
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`Friedman at 1:19-24; Assar at 1:37-38; Gal at 138; Wu at 3-4. Put differently,
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`there is a limited number of times that any particular block of flash memory can be
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`erased and rewritten, typically between 10,000 and 1,000,000 cycles as of the
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`Earliest Priority Date. Gal at 138; Aasheim at ¶[0037]; Assar at 1:39-43; Chang at
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`1.
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`B. Address Mapping
` Before the Earliest Priority Date, flash memories were commonly
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`U.S. Patent 8,010,740
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`used as non-volatile storage replacements for HDDs in “host” systems such as
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`personal computers, mobile phones, digital cameras, PDAs, and portable music
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`players. Bruce ’251 at 1:24-34 (“[F]lash-memory systems are frequently used as a
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`mass-storage replacement for a hard disk on a personal computer and are thus
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`sometimes referred to as a flash ‘disk’, even though no rotating disks are used.”);
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`Assar at Abstract; Pavan at 1248.
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` The unique read/write/erase behaviors of flash memory caused
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`compatibility issues with systems designed for use with other types of data-storage
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`devices. Ban, a U.S. patent filed in 1993 titled “Flash File System” and originally
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`assigned to M-Systems Flash Disk Pioneers Ltd., acknowledges this problem in the
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`Background of the Invention section:
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`In a typical computer system, the operating system program is
`responsible for data management of the data storage devices that
`are a part of the system. A necessary, and usually sufficient, attribute
`of a data storage device to achieve compatibility with the operating
`system program is that it can read data from, and write data to, any
`location in the data storage medium. Thus, flash memories are not
`compatible with typical existing operating system programs, since
`data cannot be written to an area of flash memory in which data
`has previously been written, unless the area is first erased.
`Ban at 1:29-39 (emphasis added).
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` Well-known techniques before the Earliest Priority Date allowed host
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`systems using storage-management techniques designed for other types of memory
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`devices like HDDs to better interface with flash-memory systems. Gal at 138-139;
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`Ryu at 766-770. Some of these techniques were invented specifically for flash
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`memories, but many were adapted from older techniques that were originally
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`invented for other storage devices. “Address mapping,” sometimes called “logical-
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`to-physical” mapping, is an example of the latter. Chang at 2; Aasheim at ¶[0005