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`
`UNITED STATES PATENT AND TRADEMARK OFFICE
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`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`
`
`
`KIOXIA AMERICA, INC. and KIOXIA CORPORATION,
`
`Petitioners,
`
`
`
`
`
`v.
`
`BITMICRO LLC, LLC,
`
`Patent Owner.
`
`Case No.: IPR2023-00743
`U.S. Patent No. 6,496,939
`
`DECLARATION OF R. JACOB BAKER, PH.D., P.E.
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`KIOXIA Ex-1003, Page 1
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`I.
`II.
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`TABLE OF CONTENTS
`INTRODUCTION ........................................................................................... 1
`QUALIFICATIONS ........................................................................................ 1
`A.
`Industry Experience ............................................................................... 2
`B.
`Academic Experience ............................................................................ 7
`C.
`Other Relevant Experience .................................................................... 8
`III. MATERIALS CONSIDERED ........................................................................ 9
`IV. TECHNOLOGY BACKGROUND ............................................................... 14
`V. OVERVIEW OF THE ’939 PATENT .......................................................... 17
`A.
`Specification of the ’939 Patent .......................................................... 17
`B.
`Prosecution History ............................................................................. 20
`VI. LEGAL PRINCIPLES USED IN ANALYSIS ............................................. 23
`A.
`Prior Art ............................................................................................... 23
`B.
`Anticipation ......................................................................................... 24
`C.
`Obviousness ......................................................................................... 25
`D.
`Claim Construction.............................................................................. 30
`VII. LEVEL OF ORDINARY SKILL IN THE ART ........................................... 32
`VIII. CLAIM CONSTRUCTION .......................................................................... 33
`A.
`“predetermined level”.......................................................................... 33
`B.
`“computing engine”/“computer engine” ............................................. 34
`C.
`“means for activating a plurality of super capacitors to supply
`power to the computing engine based upon power being
`removed from the computer system” .................................................. 36
`1.
`Step 1 – Recited Function ......................................................... 36
`2.
`Step 2 – Corresponding Structure ............................................. 37
`“means for reconfiguring the data in the computing engine” ............. 38
`1.
`Step 1 – Recited Function ......................................................... 38
`2.
`Step 2 – Corresponding Structure ............................................. 38
`“means for deactivating the plurality of super capacitors to cut
`off power to the computing engine based upon the plurality of
`
`D.
`
`E.
`
`i
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`KIOXIA Ex-1003, Page 2
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`F.
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`G.
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`super capacitors discharging to a predetermined level” ...................... 39
`1.
`Step 1 – Recited Function ......................................................... 40
`2.
`Step 2 – Corresponding Structure ............................................. 40
`“means for allowing all data to be transferred from the at least
`one volatile memory to the at least one non-volatile memory” .......... 40
`1.
`Step 1 – Recited Function ......................................................... 41
`2.
`Step 2 – Corresponding Structure ............................................. 41
`“reversing the flow of current between the computing engine
`and the plurality of super capacitors” .................................................. 42
`“means for reversing the flow of current between the computing
`engine and the plurality of super capacitors” ...................................... 43
`1.
`Step 1 – Recited Function ......................................................... 43
`2.
`Step 2 – Corresponding Structure ............................................. 43
`“means for discharging current from the plurality of super
`capacitors to the computing engine” ................................................... 44
`1.
`Step 1 – Recited Function ......................................................... 44
`2.
`Step 2 – Corresponding Structure ............................................. 44
`IX. OVERVIEW OF THE PRIOR ART ............................................................. 47
`A.
`Bruder Discloses Systems and Methods for Storing Data in a
`Computer System When Power Is Lost .............................................. 47
`B. Weber Discloses a Transfer Memory Backup System To
`Safeguard Data When Power Is Lost .................................................. 49
`Germer Discloses an Electronic Register That Preserves Data
`When Power Is Lost ............................................................................ 50
`D. Horning Discloses A Data Protection System That Uses
`Reserve Power To Maintain Data in Volatile Memory ...................... 52
`Stokes Discloses a Super Capacitor-Based Backup Power
`System for a Nonvolatile Realtime Clock Calendar Module .............. 54
`THE PRIOR ART RENDERS ALL OF THE CLAIMED
`X.
`ELEMENTS OF THE ’939 PATENT OBVIOUS ........................................ 55
`A.
`Claims 1-3 Are Rendered Obvious by Horning in View of
`Stokes .................................................................................................. 55
`1.
`Claim 1 Is Rendered Obvious by Horning in View of
`
`H.
`
`I.
`
`C.
`
`E.
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`-ii-
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`KIOXIA Ex-1003, Page 3
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`B.
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`C.
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`D.
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`2.
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`3.
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`2.
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`3.
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`Stokes ........................................................................................ 59
`Claim 2 Is Rendered Obvious by Horning in View of
`Stokes ........................................................................................ 66
`Claim 3 Is Rendered Obvious by Horning in View of
`Stokes ........................................................................................ 66
`Claims 1-3 Are Rendered Obvious by Germer in View of
`Horning Further in View of Stokes ..................................................... 67
`1.
`Claim 1 Is Rendered Obvious by Germer in View of
`Horning Further in View of Stokes ........................................... 72
`Claim 2 Is Rendered Obvious by Germer in View of
`Horning Further in View of Stokes ........................................... 81
`Claim 3 Is Rendered Obvious by Germer in View of
`Horning Further in View of Stokes ........................................... 82
`Each of the Challenged Claims Is Rendered Obvious by Bruder
`in View of Horning Further in View of Stokes ................................... 83
`1.
`Claim 1 Is Rendered Obvious by Bruder in View of
`Horning Further in View of Stokes ........................................... 88
`Claim 2 Is Rendered Obvious by Bruder in View of
`Horning Further in View of Stokes ........................................... 98
`Claim 3 Is Rendered Obvious by Bruder in View of
`Horning Further in View of Stokes ........................................... 98
`Claim 6 Is Rendered Obvious by Bruder in View of
`Horning Further in View of Stokes ........................................... 99
`Claim 10 Is Rendered Obvious by Bruder in View of
`Horning Further in View of Stokes ......................................... 103
`Claim 11 Is Rendered Obvious by Bruder in View of
`Horning Further in View of Stokes ......................................... 116
`Claim 12 Is Rendered Obvious by Bruder in View of
`Horning Further in View of Stokes ......................................... 117
`Claim 15 Is Rendered Obvious by Bruder in View of
`Horning Further in View of Stokes ......................................... 119
`Claims 1-3 and 6 Are Rendered Obvious by Weber in View of
`Horning Further in View of Stokes ................................................... 122
`1.
`Claim 1 Is Rendered Obvious By Weber in View of
`Horning Further in View of Stokes ......................................... 127
`Claim 2 Is Rendered Obvious By Weber in View of
`Horning Further in View of Stokes ......................................... 137
`
`2.
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`3.
`
`4.
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`5.
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`6.
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`7.
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`8.
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`2.
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`-iii-
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`KIOXIA Ex-1003, Page 4
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`3.
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`4.
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`Claim 3 Is Rendered Obvious by Weber in View of
`Horning Further in View of Stokes ......................................... 138
`Claim 6 Is Rendered Obvious by Weber in View of
`Horning Further in View of Stokes ......................................... 139
`XI. CONCLUSION ............................................................................................ 143
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`-iv-
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`KIOXIA Ex-1003, Page 5
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`

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`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 6,496,939
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`
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`I, Dr. R. Jacob Baker, declare as follows:
`
`I.
`
`INTRODUCTION
`I have been retained by KIOXIA Corporation and KIOXIA America,
`1.
`
`Inc. (“Petitioners”) as an independent expert in this inter partes review before the
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`United States Patent and Trademark Office (“PTO”) regarding U.S. Patent No.
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`6,496,939 (“the ’939 patent”), Ex-1001. Specifically, I have been asked to consider
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`whether certain references disclose or suggest the features recited in claims 1-3, 6,
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`10-12, and 15 of the ’939 patent (“challenged claims”). As explained below, it is
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`my opinion that the challenged claims are invalid as anticipated and/or obvious in
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`view of the prior art references discussed in this Declaration and the accompanying
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`Petition.
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`2.
`
`I am being compensated at my ordinary consulting rate of $655.00 per
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`hour. No part of my compensation is dependent on the outcome of this proceeding
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`or any other proceeding involving the ’939 patent or any of its related patents. I
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`have no other interests in this proceeding.
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`II. QUALIFICATIONS
`3. My qualifications are generally set forth in my Curriculum Vitae, which
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`is attached as Ex-1004. My Curriculum Vitae also includes a list of the publications
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`I have authored and a list of the other cases in which I have testified during the last
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`-1-
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`KIOXIA Ex-1003, Page 6
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`

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`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 6,496,939
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`four years.
`
`4.
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`I have been working as an Engineer since 1985 and have been teaching
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`Electrical and Computer Engineering courses since 1991. I am currently a Professor
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`of Electrical and Computer Engineering at the University of Nevada, Las Vegas
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`(“UNLV”).
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`5.
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`I received B.S. and M.S. degrees in Electrical Engineering from UNLV
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`in 1986 and 1988, respectively. I received my Ph.D. in Electrical Engineering from
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`the University of Nevada, Reno, in 1993.
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`6. My doctoral research, culminating in the award of a Ph.D., investigated
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`the use of power MOSFETs in the design of very high peak power, and high-speed,
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`instrumentation. I developed techniques to reliably stack power MOSFETs to switch
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`higher voltages, that is, greater than 1,000 volts and 100 amps of current with
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`nanosecond switching times. This work was reported in the paper entitled
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`“Transformerless Capacitive Coupling of Gate Signals for Series Operation of
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`Power MOSFET Devices,” published in the IEEE Transactions on Power
`
`Electronics. The paper received the Best Paper Award in 2000.
`
`A.
`7.
`
`Industry Experience
`I have done technical and expert witness consulting for over 200
`
`companies and their subsidiaries since I started working as an engineer in 1985,
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`-2-
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`KIOXIA Ex-1003, Page 7
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`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 6,496,939
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`which included design experience with circuits employing capacitors. This
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`experience ranged from designing computer memory employing a one-transistor,
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`one-capacitor memory (DRAM, dynamic random access memory) to the design of
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`power supply circuits where capacitors are used for filtering. I’ve also worked on
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`the design of capacitors to supply power to a modem in the event of a power failure.
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`From 1985 to 1993, I worked for EG&G Energy Measurements and the Lawrence
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`Livermore National Laboratory designing nuclear diagnostic instrumentation for
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`underground nuclear weapon tests at the Nevada test site. During this time, I
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`designed, and oversaw the fabrication of, over 30 electronic and electro-optic
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`instruments, including high-speed cable and fiber-optic receiver/transmitters, PLLs,
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`frame and bit-syncs, data converters, streak-camera sweep circuits, Pockel’s cell
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`drivers, micro-channel plate gating circuits, charging circuits for battery backup of
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`equipment for recording test data, and analog oscilloscope electronics.
`
`8. My work during this time, as one example, had a direct impact on my
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`doctoral research work using power MOSFETs, subsequent publishing efforts, and
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`industry designs. In addition to the 2000 Best Paper Award from the IEEE Power
`
`Electronics Society, I published several other papers in related areas while working
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`in industry. I hold a patent, US Patent No. 5,874,830, in the area of power supply
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`design, titled, “Adaptively biased voltage regulator and operating method,” which
`
`-3-
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`KIOXIA Ex-1003, Page 8
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`

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`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 6,496,939
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`was issued on February 23, 1999. I have designed dozens of linear and switching
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`power supplies for commercial products and scientific instrumentation.
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`9.
`
`I am a licensed Professional Engineer and have extensive industry
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`experience in circuit design, fabrication, and manufacture of Dynamic Random
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`Access Memory (DRAM) semiconductor integrated circuit chips, Phase-Change
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`Random Access Memory (PCRAM) chips, and CMOS Image Sensors (CISs) at
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`Micron Technology, Inc. (“MTI”) in Boise, Idaho. I spent considerable time
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`working on the development of flash memory chips while at MTI. My efforts
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`resulted in more than a dozen patents relating to flash memory. One of my projects
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`at MTI included the development, design, and testing of circuit design techniques
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`for a multi-level cell (MLC) flash memory using signal processing. This effort
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`resulted in higher-density memories for use in solid-state drives and flash memory
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`cards having an ATA interface that are ubiquitous in consumer electronics, including
`
`cameras and data storage systems. Further, the use of higher-density memory can
`
`result in fewer changes in the flash translation layer for logical-to-physical
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`addressing, less need for garbage collection, and larger data segments that can
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`improve a computing system’s performance.
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`10. Another project I worked on at MTI focused on the design of buffers
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`for high-speed double-data rate DRAM, which resulted in around 10 U.S. patents in
`
`-4-
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`KIOXIA Ex-1003, Page 9
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`

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`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 6,496,939
`
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`buffer design. Among many other experiences, I led the development of the delay
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`locked loop (DLL) in the late 1990s so that MTI DRAM products could transition
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`to the DDR memory protocol, used in mobile and non-mobile (server, desktop, cell
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`phones, tablets, etc.) computing systems as main computer memory, for addressing
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`and controlling accesses to memory via interprocess communications (IPC) with the
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`memory controller (MC). I provided technical assistance with MTI’s acquisition of
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`Photobit during 2001 and 2002, including transitioning the manufacture of CIS
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`products into MTI’s process technology. Further, I did consulting work at Sun
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`Microsystems and then Oracle on the design of memory modules during 2009 and
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`2010. This work entailed the design of low-power, high-speed, and wide
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`interconnection methods with the goal of transmitting data to/from the memory
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`module and the MC at higher speeds.
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`11.
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`I have extensive experience in the development of instrumentation and
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`commercial products
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`in
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`a multitude of
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`areas
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`including:
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`integrated
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`electrical/biological circuits and systems, array (memory, imagers, and displays)
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`circuit design, CMOS analog and digital circuit design, diagnostic electrical and
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`electro-optic instrumentation for scientific research, CAD tool development and
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`online tutorials, low-power interconnect and packaging techniques, design of
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`communication/interface circuits (to meet commercial standards such as USB,
`
`-5-
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`KIOXIA Ex-1003, Page 10
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`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 6,496,939
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`firewire, DDR, PCIe, SPI, etc.), circuit design for the use and storage of renewable
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`energy, and power electronics. For example, a part of my research at Boise State,
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`for many years, focused on the use of Thru-Silicon-Vias (TSVs), aka Thru-Wafer
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`Vias (TWVs), for high-density packaging. These packaging techniques were
`
`utilized in the memory module development work I did with Sun Microsystems and
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`Oracle. As another example, I designed circuitry for use in implementing Universal
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`Serial Bus (USB) interface circuits while consulting at Tower Semiconductor. I
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`designed PCI communication circuits for IPC between a Graphics Processor Unit
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`(GPU) and memory while consulting for Rendition, Inc.
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`12. My current research work is focused in part on the design of integrated
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`circuits for wireless sensing using LIDAR (LIght Detection And Ranging). I have
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`worked with several companies in the development of these circuits and systems
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`including Freedom Photonics, Aerius Photonics, and FLIR. In the early 1990s, I
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`worked on wireless systems for wideband impulse radar while at Lawrence
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`Livermore Laboratory. Further, part of my research for several years focused on the
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`digitization of IQ channels using delta-sigma modulation. The knowledge and
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`experience gained from this effort are reflected in my textbook CMOS Mixed-Signal
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`Circuit Design and a presentation, which I have presented at several universities and
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`companies, http://cmosedu.com/jbaker/papers/talks/BP_DSM_talk.pdf.
`
`-6-
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`KIOXIA Ex-1003, Page 11
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`

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`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 6,496,939
`
`
`
`B. Academic Experience
`I was an adjunct faculty member in the Electrical Engineering
`13.
`
`departments of UNLV and UNR from 1991-1993. From 1993 to 2000, I served on
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`the faculty at the University of Idaho as an Assistant Professor and then as a tenured
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`Associate Professor of Electrical Engineering. In 2000, I joined a new Electrical and
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`Computer Engineering program at Boise State University (“BSU”), where I served
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`as department chair from 2004 to 2007. At BSU, I helped establish graduate
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`programs in Electrical and Computer Engineering including, in 2006, the
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`university’s second Ph.D. degree. In 2012, I re-joined the faculty at UNLV. Over
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`the course of my career as a professor, I have advised more than 100 masters and
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`doctoral students.
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`14.
`
`I have been recognized for my contributions as an educator in the field.
`
`While at Boise State University, I received the President’s Research and Scholarship
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`Award (2005), Honored Faculty Member recognition (2003), and Outstanding
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`Department of Electrical Engineering Faculty recognition (2001). In 2007, I
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`received the Frederick Emmons Terman Award (the “Father of Silicon Valley”),
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`which is bestowed annually upon an outstanding young electrical/computer
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`engineering educator in recognition of the educator’s contributions to the profession.
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`In 2011, I received the IEEE Circuits and Systems Education Award. I received the
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`-7-
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`KIOXIA Ex-1003, Page 12
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`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 6,496,939
`
`
`Tau Beta Pi Outstanding Electrical and Computer Engineering Professor Award
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`every year it was awarded while I have been back at UNLV.
`
`15.
`
`I have authored several books and papers in the electrical and computer
`
`engineering area. My published books include CMOS Circuit Design, Layout, and
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`Simulation (Baker, R.J., Wiley-IEEE, ISBN: 9781119481515 (4th ed., 2019)) and
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`CMOS Mixed-Signal Circuit Design
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`(Baker, R.J., Wiley-IEEE,
`
`ISBN:
`
`9780470290262 (2nd ed., 2009) and ISBN: 9780471227540 (1st ed., 2002)). I co-
`
`authored DRAM Circuit Design: Fundamental and High-Speed Topics (Keeth, B.,
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`Baker, R.J., Johnson, B., and Lin, F., Wiley-IEEE, ISBN: 9780470184752 (2008)),
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`DRAM Circuit Design: A Tutorial (Keeth, B. and Baker, R.J., Wiley-IEEE, ISBN:
`
`0-7803-6014-1 (2001)), and CMOS Circuit Design, Layout and Simulation (Baker,
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`R.J., Li, H.W., and Boyce, D.E., Wiley - IEEE, ISBN: 9780780334168 (1998)). I
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`contributed as an editor and co-author on several other electrical and computer
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`engineering books.
`
`C. Other Relevant Experience
`I have performed technical and expert witness consulting for more than
`16.
`
`200 companies and their subsidiaries and given more than 50 invited talks at
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`conferences, companies, and universities. Further, I am the author or co-author of
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`more than 100 papers and presentations in the areas of electrical and computer
`
`-8-
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`KIOXIA Ex-1003, Page 13
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`

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`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 6,496,939
`
`
`engineering design, fabrication, and packaging.
`
`17.
`
`I currently serve, or have served, as a volunteer on the IEEE Press
`
`Editorial Board (1999-2004); as editor for the Wiley-IEEE Press Book Series on
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`Microelectronic Systems (2010-2018); as the Technical Program Chair of the 2015
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`IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS
`
`2015); on the IEEE Solid-State Circuits Society (SSCS) Administrative Committee
`
`(2011-2016); as a Distinguished Lecturer for the SSCS (2012-2015); the Technology
`
`Editor (2012-2014) and Editor-in-Chief (2015-2020) for IEEE Solid-State Circuits
`
`Magazine; IEEE Kirchhoff Award Committee (2020-2023); and advisor for the
`
`student branch of the IEEE at UNLV (2013-present). These meetings, groups, and
`
`publications are intended to allow researchers to share and coordinate research. My
`
`active participation in these meetings, groups, and publications allowed me to see
`
`what other researchers in the field have been doing.
`
`18.
`
`In addition to the above, I am an IEEE Fellow for contributions to
`
`semiconductor memory design and a member of the honor societies Eta Kappa Nu
`
`and Tau Beta Pi.
`
`III. MATERIALS CONSIDERED
`19. My opinions, as set forth in this Declaration, are based on the
`
`documents I have reviewed, my experience and background, and my knowledge and
`
`-9-
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`KIOXIA Ex-1003, Page 14
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`

`

`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 6,496,939
`
`
`professional judgment. In forming these opinions, I have reviewed the ’939 patent
`
`(Ex-1001), the prosecution history for the ’939 patent (Ex-1002), the prior art
`
`discussed below, and any other material and information identified in this
`
`Declaration. I have also relied on my experience and knowledge in the field of
`
`computer memory and data storage devices.
`
`20.
`
`In particular, my opinions regarding the invalidity of the challenged
`
`claims are based on the following prior art references, as informed by my knowledge
`
`in the field of computer memory and data storage devices.
`
`Exhibit
`
`Description
`
`1005
`
`U.S. Patent No. 4,559,616 (“Bruder”). It is my understanding that
`
`Bruder issued on December 17, 1985. Petitioners’ counsel has
`
`informed me
`
`that Bruder
`
`is prior
`
`art under pre-AIA
`
`35 U.S.C. § 102(b). See infra § VI.B for a more detailed description
`
`regarding my understanding of this category of prior art.
`
`1006
`
`U.S. Patent No. 5,596,708 (“Weber”). It is my understanding that
`
`Weber issued on January 21, 1997. Petitioners’ counsel has informed
`
`me that Weber is prior art under pre-AIA 35 U.S.C. § 102(b). See
`
`infra § VI.B for a more detailed description regarding my
`
`understanding of this category of prior art.
`
`-10-
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`KIOXIA Ex-1003, Page 15
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`

`

`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 6,496,939
`
`
`
`Exhibit
`
`Description
`
`1007
`
`U.S. Patent No. 4,591,782 (“Germer”). It is my understanding that
`
`Germer issued on May 27, 1986. Petitioners’ counsel has informed
`
`me that Germer is prior art pursuant to 35 U.S.C. § 102(b). See
`
`infra § VI.B
`
`for a more detailed description
`
`regarding my
`
`understanding of this category of prior art.
`
`1008
`
`U.S. Patent No. 5,414,861 (“Horning”). It is my understanding that
`
`Horning issued on May 9, 1995. Petitioners’ counsel has informed me
`
`that Horning is prior art pursuant to 35 U.S.C. § 102(b). See
`
`infra § VI.B
`
`for a more detailed description
`
`regarding my
`
`understanding of this category of prior art.
`
`1009
`
`Claim Construction Order and Memorandum in Support Thereof,
`
`BiTMicro LLC v. KIOXIA Am., Inc., WDTX-6-22-00331-ADA, Dkt.
`
`No. 54 (WDTX, Feb. 16, 2023).
`
`1010
`
`U.S. Patent No. 3,980,935 (“Worst”). It is my understanding that
`
`Worst issued on September 14, 1976. Petitioners’ counsel has
`
`informed me that Worst is prior art pursuant to 35 U.S.C. § 102(b).
`
`See infra § VI.B for a more detailed description regarding my
`
`understanding of this category of prior art.
`
`-11-
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`KIOXIA Ex-1003, Page 16
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`

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`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 6,496,939
`
`
`
`Exhibit
`
`Description
`
`1011
`
`U.S. Patent No. 4,306,299 (“Check”). It is my understanding that
`
`Check issued on December 15, 1981. Petitioners’ counsel has
`
`informed me that Check is prior art pursuant to 35 U.S.C. § 102(b).
`
`See infra § VI.B for a more detailed description regarding my
`
`understanding of this category of prior art.
`
`1012
`
`U.S. Patent No. 4,431,134 (“Hendricks”). It is my understanding that
`
`Hendricks issued on February 14, 1984. Petitioners’ counsel has
`
`informed me that Hendricks is prior art pursuant to 35 U.S.C. §
`
`102(b). See infra § VI.B for a more detailed description regarding my
`
`understanding of this category of prior art.
`
`1013
`
`U.S. Patent No. 4,701,858 (“Stokes”). It is my understanding that
`
`Stokes issued on October 20, 1987. Petitioners’ counsel has informed
`
`me that Stokes is prior art pursuant to 35 U.S.C. § 102(b). See
`
`infra § VI.B
`
`for a more detailed description
`
`regarding my
`
`understanding of this category of prior art.
`
`1014
`
`U.S. Patent No. 4,453,117 (“Elms”). It is my understanding that Elms
`
`issued on June 5, 1984. Petitioners’ counsel has informed me that
`
`Elms is prior art pursuant to 35 U.S.C. § 102(b). See infra § VI.B for
`
`-12-
`
`KIOXIA Ex-1003, Page 17
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`

`

`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 6,496,939
`
`
`
`Exhibit
`
`Description
`
`a more detailed description regarding my understanding of this
`
`category of prior art.
`
`1015
`
`U.S. Patent No. 4,412,284 (“Kerforne”). It is my understanding that
`
`Kerforne issued on October 25, 1983. Petitioners’ counsel has
`
`informed me that Kerforne is prior art pursuant to 35 U.S.C. § 102(b).
`
`See infra § VI.B for a more detailed description regarding my
`
`understanding of this category of prior art.
`
`1016
`
`U.S. Patent No. 3,562,555 (“Ahrons”). It is my understanding that
`
`Ahrons issued on February 9, 1971. Petitioners’ counsel has informed
`
`me that Ahrons is prior art pursuant to 35 U.S.C. § 102(b). See
`
`infra § VI.B
`
`for a more detailed description
`
`regarding my
`
`understanding of this category of prior art.
`
`1017
`
`U.S. Patent No. 4,636,963 (“Nakajima”). It is my understanding that
`
`Nakajima issued on January 13, 1987. Petitioners’ counsel has
`
`informed me that Nakajima is prior art pursuant to 35 U.S.C. § 102(b).
`
`See infra § VI.B for a more detailed description regarding my
`
`understanding of this category of prior art.
`
`
`
`-13-
`
`KIOXIA Ex-1003, Page 18
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`

`

`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 6,496,939
`
`
`IV. TECHNOLOGY BACKGROUND
`I understand that the ’939 patent issued on December 17, 2002 and was
`21.
`
`filed on September 21, 1999. The ’939 patent purportedly relates to controlling data
`
`in a computer system in the event of a power failure. See, e.g., Ex-1001, Abstract.
`
`In particular, the ’939 patent discusses using super-capacitors to power the transfer
`
`of data from volatile to non-volatile memory during a power failure. Id.
`
`22. Using capacitors as back-up power to enable the preservation of data
`
`stored in volatile memory during an external power loss predates the September
`
`1999 filing date of the ’939 patent by many years. As early as the 1960’s, it was
`
`known to use capacitors to provide back-up power for memory devices. For example,
`
`Ahrons—which was filed in 1967—describes a “memory protecting circuit”
`
`utilizing a capacitor as an “emergency power source to supply the current
`
`requirements” for memory. Ex-1016 at 3:21-24. And by the early 1980s, it was
`
`common to find a variety of devices and systems that employed capacitors as back-
`
`up power systems for preserving data in volatile memory, including in the context
`
`of microprocessor controlled motors (Ex-1014, filed on Apr. 14, 1983); postage
`
`meters (Ex-1011, filed on November 13, 1979); thermostats (Ex-1012, filed on Nov.
`
`8, 1982); electric utility meters (Ex-1013, filed on Dec. 31, 1984); and even
`
`household appliances such as washing machines (Ex-1015, filed on March 20, 1981).
`
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`KIOXIA Ex-1003, Page 19
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`

`

`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 6,496,939
`
`
`These devices employed back-up power, stored on capacitors, to ensure that data
`
`written into volatile memory was preserved until power could be restored.
`
`23.
`
` Similarly, preserving data by using capacitors to power the transfer of
`
`data from volatile to non-volatile memory was well-known long before the filing of
`
`the ’939 patent. For example, Check, which was filed in 1979 and claims priority to
`
`an application filed in 1974, discloses an electronic postage meter that uses
`
`capacitors as a backup power supply to preserve data stored in volatile memory. See,
`
`e.g., Ex-1011 at Abstract; id. at 18:36-47; claim 18. As Check explains, postage
`
`meters contain “critical information” and “crucial accounting functions,” such as
`
`postage balances and credits, that must be preserved in non-volatile memory when
`
`external power is lost. Id. at 6:58-7:4; see also id. at 2:4-11 (explaining that the use
`
`of non-volatile memory is important to ensure that “the remaining balance in the
`
`postal meter” and the “continuous accumulation of charges thereto” is “permanently
`
`stored in the nonvolatile memory when the system is de-energized.”). Accordingly,
`
`Check describes a method for preserving this crucial data during a power failure by
`
`using capacitors to power the transfer of data “from the [volatile] working memory
`
`to the non-volatile memory.” See e.g., id., Abstract; 10:55-58; 18:36-47; claim 1;
`
`claim 18.
`
`24. Likewise, Germer, which was filed on April 12, 1984, describes an
`
`-15-
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`KIOXIA Ex-1003, Page 20
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`

`

`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 6,496,939
`
`
`electronic register in an electric meter. Ex-1007, Abstract. As Germer explains,
`
`electric meters include volatile memory to store electric usage data, which may be
`
`lost in the event of a power outage Id. at 1:62-2:5. Germer thus teaches the use of
`
`capacitors as a temporary power store. Id., Abstract. In the event of a power loss,
`
`energy from the capacitors is used by a processor to power the transfer of data from
`
`the volatile memory to non-volatile memory, where it will be preserved. Id. at 5:49-
`
`57, 5:64-6:10.
`
`25. Super capacitors were also well-known in the art for providing back up
`
`power for memory well before the priority date of the ’939 patent. For example,
`
`Stokes, which issued in 1987, discloses super capacitors for use as backup power in
`
`a volatile memory system. Ex-1013 at 2:57-3:61. Likewise, Nakajima, which also
`
`issued in 1987, teaches a system comprising memory “whose power source is
`
`backed-up by an electric cell or an electric double layer capacitor (a capacitor
`
`generally referred to as a super capacitor having a great capacitance and with very
`
`low leaking current).” Ex-1017 at 3:65-4:3.
`
`26.
`
`In conclusion, well before the September 1999 priority date of the ’939
`
`patent, there was a long history of using capacitors and super capacitors to supply
`
`back-up power in order to preserve data in devices in the case of a sudden loss of
`
`power.