United States Patent 19
`Sukegawa
`
`(54) FLASH MEMORY CHIPS
`75) Inventor: Hiroshi Sukegawa, Tokyo, Japan
`73) Assignee: Kabushiki Kaisha Toshiba, Kawasaki,
`Japan
`
`Appl. No.: 132,313
`(21
`(22 Filed:
`Oct. 6, 1993
`30)
`Foreign Application Priority Data
`Oct. 6, 1992 (JPl
`Japan .................................... 4-267212
`(51) Int. Cl." ....................................... G11C 17/00
`52 U.S. Cl. ................................ 365/185.33; 365/185.11;
`365/185.12; 365/185.29; 365/230.01; 365/230.03;
`365/230.06; 365/239
`58) Field of Search ............................... 365/900, 230.01,
`365/185,230.05, 185.33, 185.11, 185.12,
`185.29, 230.03, 230.06, 239
`References Cited
`U.S. PATENT DOCUMENTS
`4,817,035 3/1989 Timsit.
`4,849,929 7/1989 Timsit.
`
`(56)
`
`|||||||III
`US005572466A
`5,572,466
`11) Patent Number:
`45) Date of Patent:
`Nov. 5, 1996
`
`... 36.5/218
`5,270,979 12/1993 Harari et al......
`... 395/500
`5,291584 3/1994 Challa et al. ....
`5,297,148 3/1994 Harariet al. ........................... 371/10.2
`FOREIGN PATENT DOCUMENTS
`4-57295 2/1992 Japan.
`Primary Examiner-Viet Q. Nguyen
`Attorney, Agent, or Firm-Oblon, Spivak, McClelland,
`Maier & Neustadt, P.C.
`57
`ABSTRACT
`A plurality of consecutive sector numbers are assigned to a
`plurality of flash EEPROM chips in a semiconductor
`memory system. The results of assigning the consecutive
`sector numbers are held in an address conversion table as
`address conversion information. Thus, the flash EEPROM
`chips are simultaneously accessed when a host CPU desig
`nates the consecutive sector numbers for the same track. The
`access speed of the semiconductor memory system can
`therefore be increased when the system is controlled by the
`existing disk access method in which the sectors to be
`accessed sequentially are assigned to the same track. The
`semiconductor memory system can thereby be used effi
`ciently in place of a data storage disk.
`
`10 Claims, 14 Drawing Sheets
`
`PAGE
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`KIOXIA Ex-1005, Page 1
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`

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`U.S. Patent
`
`Nov. 5, 1996
`
`Sheet 1 of 14
`
`5,572,466
`
`TRANSFERED ADDRESS FROM HOST
`
`--N
`N
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`X
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`W
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`BTS TO BE
`V
`DECODED
`TO CS SGNAL
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`ADDRESS IN CHIP
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`F G.
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`(PRIOR ART)
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`F G. 2 (PRIOR ART)
`
`KIOXIA Ex-1005, Page 2
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`

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`U.S. Patent
`
`Nov. 5, 1996
`
`Sheet 2 of 14
`
`5,572,466
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`F G.
`3E
`(PRIOR ART)
`
`O O O O O
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`6 BTS
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`KIOXIA Ex-1005, Page 3
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`

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`U.S. Patent
`
`Nov. 5, 1996
`
`Sheet 3 of 14
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`5,572,466
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`REQUEST WRTNG
`ACCESS
`
`A
`
`ACCESS BLOCK
`
`A3
`
`A5
`
`A7
`
`NO
`
`
`
`
`
`
`
`
`
`NCREASE REWRITE
`COUNT DATA OF
`BLOCK
`
`
`
`HAS CARRY
`OCCURRED
`2
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`
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`S T PROPER
`FOR SWAPPNG
`2
`
`SWAP BLOCK
`
`
`
`REWRITE TABLE
`
`A5
`
`ERASE DATA
`N BLOCK AND
`WRITE DATA INTO
`THE BLOCK
`
`F G. 5 (PRIOR ART)
`
`KIOXIA Ex-1005, Page 4
`
`

`

`U.S. Patent
`
`
`
`5,572,466
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`O}9 9 | -
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`MJETTO MJ1N00 J / I ISOH
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`KIOXIA Ex-1005, Page 5
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`

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`U.S. Patent
`
`Nov. 5, 1996
`
`Sheet 5 of 14
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`5,572,466
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`KIOXIA Ex-1005, Page 6
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`KIOXIA Ex-1005, Page 6
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`

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`U.S. Patent
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`Nov. 5, 1996
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`Sheet 6 of 14
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`5,572,466
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`WRITING PAGE
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`2 sector
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`7
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`BRASE BLOCK
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`KIOXIA Ex-1005, Page 7
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`

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`U.S. Patent
`
`Nov. 5, 1996
`
`Sheet 7 of 14
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`5,572,466
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`KIOXIA Ex-1005, Page 8
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`

`

`U.S. Patent
`
`
`
`Nov. 5, 1996
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`Sheet 8 of 14
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`5,572,466
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`KIOXIA Ex-1005, Page 9
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`

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`Nov. 5, 1996
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`2
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`5,572,466
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`Sheet 9 of 14
`
`U.S. Patent
`ADDRESS
`CONVERSION
`TABLE
`REAL MEMORY ADDRESS
`LOGICAL ADDRESS
`TRACK NoSECTOR Noll CHP No. BLOCK No.
`PAGE NO.
`
`
`
`KIOXIA Ex-1005, Page 10
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`

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`U.S. Patent
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`Nov. 5, 1996
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`Sheet 10 of 14
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`5,572,466
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`KIOXIA Ex-1005, Page 11
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`

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`U.S. Patent
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`Nov. 5, 1996
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`Sheet 11 of 14
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`5,572,466
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`PAGEO
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`DATA
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`LWC
`
`FOR
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`PAGE5
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`DATA
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`BLOCK
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`WRITE COUNT TABLE
`
`KIOXIA Ex-1005, Page 12
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`

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`U.S. Patent
`
`Nov. 5, 1996
`
`Sheet 12 of 14
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`5,572,466
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`KIOXIA Ex-1005, Page 13
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`

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`U.S. Patent
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`Nov. 5, 1996
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`Sheet 13 of 14
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`5,572,466
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`
`
`
`
`
`
`REQUEST WRITING
`ACCESS
`
`B
`
`ACCESS BLOCK
`
`B3
`
`NCREASE LWC
`OF BLOCK
`
`B5
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`B7
`
`HAS PREDETERMINED
`BTS INCREMENTED
`
`IS IT PROPER
`FOR SWAPPING
`N CHP 2
`
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`EXECUTE
`SWAPPNG PROCESS
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`REW RTE TABLES
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`THE BLOCK
`
`KIOXIA Ex-1005, Page 14
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`

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`U.S. Patent
`
`Nov. 5, 1996
`
`Sheet 14 of 14
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`5,572,466
`
`
`
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`
`KIOXIA Ex-1005, Page 15
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`

`

`1.
`FLASH MEMORY CHIPS
`
`5,572,466
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`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates to a semiconductor memory
`system equipped with a flash EEPROM (Electrically Eras
`able and Programable Read Only Memory) which is a
`non-volatile memory that is electrically and collectively
`erasable. More particularly, this invention relates to a semi
`conductor memory system that can employ an existing disk
`accessing scheme.
`2. Description of the Related Art
`Most conventional information processing system, such
`as a work station and a personal computer, use a magnetic
`disk drive as a memory device. The magnetic disk drive has
`advantages such as a high recording reliability and low bit
`price while having some short-comings such as its being
`large and susceptible to physical impact.
`The operational principle of magnetic disk drives is to
`move a magnetic head on a rotating disk to write or read data
`on or from that disk. The mechanical moving portions, such
`as the rotatable disk and the magnetic head, may malfunc
`tion or may be damaged when a physical shock is applied to
`the disk drive. Further, the necessity of those mechanical
`movable portions gets in the way of making the whole drive
`compact.
`To compensate for data when the aforementioned mal
`function or damage occurs, conventionally, there is a tech
`nique of distributively storing data into a plurality of disk
`drives. This technique divides each word constituting data
`sent from a host system (computer main body) into prede
`termined bits and stores the data in the individual disk drives
`in that form. According to this technique, a spare disk drive
`for storing redundant or dummy data is provided to correct
`data even when one of a plurality of magnetic disk drives
`becomes entirely disabled.
`As data is distributively stored into a plurality of disk
`drives to accomplish error correction according to this
`conventional technique, the length of one unit of data
`assigned to each disk drive is limited. According to this
`technique, after data is transferred to a magnetic disk drive,
`the transferred data is immediately recorded into a storage
`medium. To perform fast data reading/writing effectively
`using the performance of the magnetic disk drive, it is
`necessary to keep fast data transfer to the storage medium in
`a plurality of magnetic disk drives. Further, to read data from
`a plurality of disk drives, a buffer is necessary to restore a
`50
`word that has been divided into predetermined bits.
`Since magnetic disk drives require the mechanical mov
`able portions as described above, it is difficult to make the
`entire disk drive compact. While such a magnetic disk drive
`will not raise any problem when used in a desktop computer
`which stays on a desk for usage, the aforementioned draw
`backs become a bottleneck when it is used in a small
`portable laptop computer or notebook type computer.
`Today, therefore, a lot of attention has been paid to a
`semiconductor disk drive which is small in size and is not
`60
`susceptible to physical impact. Like the conventional mag
`netic disk drive, this semiconductor disk drive uses a flash
`EEPROM (Electrically Erasable and Programmable Read
`Only Memory), which is a non-volatile memory that is
`electrically and collectively erasable by the units of prede
`termined blocks, as a secondary memory device for a
`personal computer or the like. Like a DRAM (Dynamic
`
`45
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`30
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`40
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`65
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`2
`Random Access Memory) and mask ROM (Read Only
`Memory) the flash EEPROM, which is also a semiconductor
`memory device, can achieve high density. As the semicon
`ductor disk drive, unlike the magnetic disk drive, has no
`mechanical movable portions, it will not easily have a
`physical-impact oriented malfunction or damage. In addi
`tion, it has a smaller size which is advantageous.
`Jpn. Pat. Appln. KOKAI Publication No. 4-57295,
`entitled "Electrically Programmable Memory Circuit,”
`applied by NEC Corporation, discloses an example of a
`semiconductor disk drive which is designed to accomplish
`efficient data writing without wait using a plurality of
`semiconductor chips. The disclosed technique is designed to
`eliminate the wait time in one write cycle. This technology
`is targeted to an EEPROM as a semiconductor memory
`device. Normally, data is written byte by byte in an
`EEPROM in accordance with byte-by-byte data transfer. In
`a flash EEPROM, on the other hand, after data consisting of
`a predetermined number of consecutive bytes is transferred,
`it is written in the chips independently.
`FIG. 1 illustrates an address which is sent to a semicon
`ductor device (chip) from a host according to the technology
`by NEC Corporation. As shown in FIG. 1, predetermined
`bits of the address are used to control a CS (Chip Select)
`signal which selects one of a plurality of chips provided in
`the memory device. For instance, when four memory chips
`#0 to #3 are provided in the memory device as shown in FIG.
`2, two bits in the logical address are used to control the CS
`signal. Those two bits are input to a predetermined decoder
`and is decoded into the CS signal there.
`The upper and lower bits, excluding those two bits to
`control the CS signal, become a real memory address of that
`memory chip which become active by the CS signal. The
`number of the lower bits is enough to address the amount of
`data which can be written at a time, i.e., the amount of data
`which is written by the writing operation in one cycle. When
`64-byte page writing is possible by the writing operation in
`one cycle for each of the memory chips #0 to #3, therefore,
`nine bits are assigned to the lower bits of the memory
`address so that 64 bytes can be addressed.
`This bit assignment in the memory device provided with
`a plurality of memory chips can eliminate the wait time
`included in one writing cycle when data corresponding to
`consecutive addresses are written.
`The continuous writing operation will now be described
`referring to FIGS. 2, 3A to 3E and 4A to 4D. Suppose that
`a semiconductor memory device is provided with the
`memory chips #0 to #3 as shown in FIG. 2, and those
`memory chips #0-#3 can each accomplish 64-byte page
`writing by one writing cycle. A write enable signal is output
`from the decoder to the memory chip #0 when predeter
`mined two bits are "00," to the memory chip #1 when they
`are "01,” the memory chip #2 when they are “10," and to the
`memory chip #3 when they are “11."
`First,
`in writing data at consecutive address
`("00000000000000000” to "000001001111111111") shown
`in FIGS. 3A-3E, as the predetermined bits in the data
`corresponding to the address shown in FIG. 3A are "00," the
`data is stored on one page (page A, see FIG. 2) correspond
`ing
`to
`the
`address
`("000000000000000”
`to
`"000000111111111") in the memory chip #0. Likewise, the
`data corresponding to the addresses shown in FIGS. 3B to
`3D are stored in the areas which correspond to the address
`("000000000000000” to "000000111111111") in the respec
`tive memory chips #1 to #3 (pages B-D; see FIG. 2). As the
`predetermined bits in the data corresponding to the address
`
`KIOXIA Ex-1005, Page 16
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`

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`3
`shown in FIG. 3E are "00," the data is stored on page E (see
`FIG.
`2)
`corresponding
`O
`the
`addresses
`("000001000000000” to "000001111111111") again in the
`memory chip #0.
`The target memory chip for data writing therefore
`changes page by page in the order of #0, #1, #2, #3 and #0
`again as shown in FIG. 2. Accordingly, the wait time
`becomes as shown in the timing charts given in FIGS. 4A to
`4D; it is apparent that the wait time included in one writing
`cycle can be eliminated.
`Since this scheme produces a CS signal by decoding
`predetermined bits in the address sent from a host, the
`addresses in each memory chip should be fixed in a con
`secutive order. If a specific area (block) becomes disabled
`due to deterioration or the like, therefore, data cannot be
`written at consecutive addresses including the address which
`corresponds to that area.
`Suppose page B in the memory chip #1 shown in FIG. 2
`is damaged and unaccessible. Then, since the addresses
`corresponding to the areas of pages A to E (the addresses
`sent from a host) are fixed and consecutive, page F cannot
`be used for the lost page B. It is apparent that while the
`scheme taught by NEC Corporation can eliminate the wait
`time included in one writing cycle, it cannot flexibly cope
`with a damage or the like of a memory area (block) which
`may be caused by deterioration or the like.
`There is a so-called swapping process which is designed
`to cope with damaged blocks in a flash EEPROM which are
`originated from the frequent erasing/writing action or the
`like. This swapping process prevents the concentration of
`rewriting to a specific block in a flash EEPROM, whose
`rewrite count is limited, at the time data is written. In
`addition, the swapping processes is executed only in each
`flash EEPROM chip.
`The swapping processes will be briefly described with
`reference to the flowchart illustrated in FIG. 5. The details
`of the swapping process are described in U.S. patent appli
`cation Ser. No. 001,750.
`To execute a swapping process, a memory area for storing
`data of the rewrite count is provided block by block in a flash
`EEPROM chip. This rewrite count data is incremented every
`time the accessed block is rewritten. In addition to the
`memory area for the rewrite count data, an area for storing
`the upper data (upper bits) of the rewrite count data of each
`block is provided. The upper data to be stored in this area is
`updated when a predetermined carry of the rewrite count
`(renewal of predetermined upper bits) occurs, and will not
`be updated every time a normal rewriting action is taken.
`When a writing access to a designated address is
`requested under the above conditions, the block which
`corresponds to this designated address is accessed (steps A1
`and A3). Then, the rewrite count data stored in the accessed
`block is incremented after which it is determined if a
`predetermined carry has occurred (steps A5 and A7).
`When a predetermined carry occurs (YES in steps A7), it
`is determined if a swapping process should be performed,
`referring to the upper data of the rewrite count data (step
`A9). This decision on the swapping process is performed for
`example by comparing the upper data of the accessed block
`with the upper data of other blocks and detecting that block
`whose rewrite count is less by more than a predetermined
`number than the rewrite count of the accessed block. Con
`sequently, the block whose rewire count is less by more than
`a predetermined number than the rewire count of the
`accessed block is selected and the execution of the swapping
`process is determined. Then, data to be written in the
`
`4
`accessed block is replaced with the data that is held in the
`block selected in step A9 (step A11).
`When data replacement is complete, a table which cor
`relates the area for storing the upper data, the logical address
`and the real memory address with one another are changed
`(step A13).
`When a predetermined carry has not occurred (No in step
`A7) or no block whose rewrite count is less by more than a
`predetermined number than the rewrite count of the accessed
`block has not been detected (NO in step A9), the swapping
`process will not be performed and the accessed block is
`entirely erased before the requested data is written there
`(step A15).
`This swapping process prevents the concentration of
`rewriting to a specific block to thereby provide the average
`rewrite frequency for the individual blocks. It is therefore
`possible to prolong the service life of the individual blocks
`in a flash EEPROM whose rewrite counts are limited.
`As mentioned above, the swapping of data is limited
`within each chip in this swapping process. While the rewrit
`ing frequencies of the individual block in each chip can be
`averaged, therefore, the average rewrite frequency cannot be
`provided for the individual chips provided in the semicon
`ductor disk drive.
`If a semiconductor disk drive using a flash EEPROM is
`used as a spare disk, the logical address sent from a host
`system is converted into the real address in the semicon
`ductor disk drive. Normally, a plurality of semiconductor
`chips are populated on a semiconductor disk drive. The
`above address conversion is executed by correlating the
`track number and sector number given by the logical address
`from the host system to the real memory address by which
`the flash EEPROMs in the semiconductor disk drive are
`selectively accessed.
`There is no established scheme for determining how to
`correlate the track number and sector number given by the
`logical address from the host system with the internal real
`memory address.
`With a semiconductor disk drive in use, therefore, the
`conventional disk accessing scheme in the host system
`which arranges consecutive data within the same track to
`suppress the frequency per track as much as possible cannot
`be used effectively. In other words, conventionally, the
`conventional disk access scheme of the host system cannot
`be employed, making it difficult to effectively use a semi
`conductor disk drive as a spare disk.
`
`SUMMARY OF THE INVENTION
`It is therefore a primary object of the present invention to
`provide a semiconductor memory system which is designed
`to permit parallel access to a plurality of flash EEPROMs
`when consecutive sector numbers in the same track are
`designated, so that the existing disk access scheme of a host
`System for limiting consecutive sectors to be accessed to the
`same track can be effectively used.
`It is another object of this invention to provide a semi
`conductor memory system, which can give the averaged
`rewrite frequency for the individual flash EEPROM chips
`using a swapping process as well as can achieve the first
`object.
`To achieve the foregoing objects, according to one aspect
`of this invention, there is provided a semiconductor memory
`system having a plurality of flash EEPROM chips, compris
`ing: address converting means for converting a logical
`
`5,572,466
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`KIOXIA Ex-1005, Page 17
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`5,572,466
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`6
`obvious from the description, or may be learned by practice
`of the invention. The objects and advantages of the invention
`may be realized and obtained by means of the instrumen
`talities and combinations particularly pointed out in the
`appended claims.
`
`10
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`15
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`20
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`5
`address designated by a host system by using a track number
`and a sector number, into a real memory address for access
`ing at least one of the plurality of flash EEPROM chips
`based on address conversion information, memory access
`means for performing a read/write access to the plurality of
`flash EEPROM chips in accordance with the real memory
`address converted from the logical address by the address
`converting means, and means for assigning sequential
`sector number sets to sequential flash EEPROM chips so as
`to permit the memory access means to parallelly access the
`plurality of flash EEPROM chips, and for holding results of
`assigning the sequential-sector number sets as the address
`conversion information.
`The system according to the aspect of this invention,
`further comprising: means for performing a swapping pro
`cess for averaging numbers of a respective write operation
`of each memory area corresponding to one track number in
`a logical address.
`According to another aspect of this invention, there is
`provided a method of controlling data stored in a semicon
`ductor memory system connected to a host system and
`having a plurality of flash EEPROM chips, means for
`assigning sequential-sector number sets to sequential flash
`EEPROM chips so as to permit the memory access means to
`parallelly access the plurality of flash EEPROM chips,
`means for holding results of assigning the sequential-sector
`number sets as the address conversion information, means
`for performing a swapping process for uniforming a number
`of write operations each performed in units of blocks each
`having a predetermined size, and group information holding
`means for holding group information having real memory
`addresses corresponding to the sector numbers assigned to
`one track, the method comprising: a conversion step for
`converting a logical address designated by the host system
`by using a track number and a sector number, into a real
`memory address for accessing at least one of the plurality of
`flash EEPROM chips based on address conversion informa
`tion; a memory access step of performing a read/write access
`to the plurality of flash EEPROM chips in accordance with
`the real memory address converted in the conversion step;
`and a step of determining, based on the group information
`held by the group information holding means, whether the
`swapping process should be performed on the blocks which
`belong to different chips.
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`With the above-described semiconductor memory system,
`consecutive sector numbers are allocated to flash EEPROM
`chips so as to cover the latter and the contents of the
`allocation are stored as address conversion information used
`for converting the logical address from the host system into
`the real memory address. This allows flash EEPROM chips
`to be accessed parallelly, when consecutive sector numbers
`in the same track are specified by the host system. Accord
`ingly, by an existing disk accessing technique in the host
`system of arranging consecutively accessed sectors in the
`same track, the accessing speed of the semiconductor disk
`system can be improved, making possible effective use of
`the semiconductor disk system as an alternative disk unit.
`Additionally, to achieve the swapping process inside and
`outside the memory chips, the correspondence between the
`logical address and the read addresses in the address con
`version information only has to be rewritten, enabling the
`use of an existing disk accessing method. With the above
`described semiconductor memory system, it is possible to
`execute a swapping process in units of chips.
`Additional objects and advantages of the invention will be
`set forth in the description which follows, and in part will be
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`BRIEF DESCRIPTION OF THE DRAWINGS
`The accompanying drawings, which are incorporated in
`and constitute a part of the specification, illustrate a pres
`ently preferred embodiment of the invention, and together
`with the general description given above and the detailed
`description of the preferred embodiment given below, serve
`to explain the principles of the invention, in which:
`FIG. 1 is a pictorial diagram of the structure of an address
`sent from the host system in a memory device using
`EEPROMs;
`FIG. 2 shows the arrangement of the individual EEPROM
`chips for explaining the continuous write operations in the
`memory device;
`FIGS. 3A to 3E show an address per page sent from the
`host system, respectively, all the addresses shown in FIGS.
`3A to 3E being consecutive;
`FIGS. 4A to 4D are timing charts for the write operation
`according to the consecutive addresses shown in FIGS. 3A
`to 3E, and correspond to memory chips #0 to #3, respec
`tively;
`FIG. 5 is a flowchart for explaining the swapping process
`in a flash EEPROM;
`FIG. 6 is a block diagram of a semiconductor disk drive
`according to an embodiment of the present invention;
`FIG. 7 is an illustration for explaining the principle of
`allocating addresses to flash EEPROM chips provided in the
`semiconductor disk drive of the embodiment;
`FIG. 8 is an illustration for explaining an example of data
`write unit/erase unit in the flash EEPROM chips provided in
`the semiconductor disk drive of the embodiment;
`FIG. 9 is an illustration for describing a concrete example
`of allocating addresses to the flash EEPROMs provided in
`the semiconductor disk drive of the embodiment;
`FIG. 10 is an illustration for describing a concrete
`example of allocating addresses to the flash EEPROMs
`provided in the semiconductor disk drive of the embodi
`ment,
`FIG. 11 shows an example of the structure of an address
`conversion table provided in the semiconductor disk drive of
`the embodiment;
`FIG. 12 is an illustration for explaining the data write
`operation in the semiconductor disk drive of the embodi
`ment;
`FIG. 13 is a block diagram of a schematic structure of
`each page constituting blocks of the flash EEPROM chips of
`the embodiment;
`FIG. 14 is an illustration of a write count table provided
`in the flash EEPROM chips of the embodiment;
`FIG. 15 is an illustration for describing allocating groups
`in executing the swapping process between the flash
`EEPROM chips of the embodiment;
`FIG.16 is a flowchart for explaining the swapping process
`of the embodiment; and
`FIGS. 17A to 17C are illustrations for describing blocks
`in which the data to be changed by the swapping process of
`the embodiment is stored.
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`KIOXIA Ex-1005, Page 18
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`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`Hereinafter, an embodiment of the present invention will
`be described with reference to the accompanying drawings.
`FIG. 6 shows the structure of a semiconductor disk drive
`according to an embodiment of the present invention. The
`semiconductor disk drive 10 is used as a secondary memory
`for a personal computer in place of a hard disk drive or a
`floppy disk drive, and has a PCMCIA (Personal Computer
`Memory Card International Association) interface or an IDE
`(Integrated Drive. Electronics) interface, for example. The
`semiconductor disk drive 10 is provided with flash
`EEPROM chips 11-0 through 11-4 as data storage elements.
`In these flash EEPROM chips 11-0 through 11-4, the mini
`mum unit of data amount handled in a write or an erase
`operation is determined and the unit amount of data will be
`handled in unison. Here, as an example, it is assumed that
`the flash EEPROM chips 11-0 through 11-4 allow data write
`in pages of 256 bytes and data erase in blocks of 4K bytes.
`In this case, for these flash EEPROMs, it is preferable to use
`Toshiba's 16M-bit NAND flash EEPROMs. Each of the
`flash EEPROMs 11-0 through 11-4 is provided with a WC
`(write count) table explained later, so that the number of
`writes in each block more than a predetermined value may
`be stored in one block of a memory area.
`The semiconductor disk drive 10 comprises an access
`controller 12, a host interface controller 13, a host interface
`14, and a data buffer 15. The access controller 12 provides
`access control of the flash EEPROM chips 11-0 through 11-4
`via the host interface 14 and the host interface controller 13,
`in response to an disk access request supplied from a host
`CPU.
`This access can be achieved by a command method where
`an operation mode of the flash EEPROM chips is specified
`by a command. Specifically, the access controller 12 first
`specifies an operation mode (write, read, erase, verify, etc.)
`of the flash EEPROM chips and then supplies an address (an
`address and the write data in the case of the write mode)
`indicating an access position to the flash EEPROM chips.
`Each flash EEPROM chip is provided with, for example, a
`256-byte input/output register. Thus, for example, in the
`write mode, after the write data has been transferred to the
`register by the access controller 12, a write operation is
`carried out inside the flash EEPROM chips. As a result, the
`access controller 12 is freed from the write access control.
`The access controller 12 is provided with an address
`conversion table 121 and a group table 122. In the address
`conversion table 121, the correspondence between the logi
`cal addresses (the track numbers and the sector numbers)
`from the host CPU and the real addresses for accessing the
`flash EEPROM chips 11-0 through 11-4 is defined. In this
`case, the consecutive sector numbers in the same track are
`arranged so as to cover the flash EEPROM chips 11-0
`through 11-4. In the group table 122, a block of each flash
`EEPROM chip corresponding to one track is defined as a
`group.
`The host interface 14, like a hard disk drive connectable
`to a host system bus, has, for example, a 40-pin arrangement
`conforming with the IDE interface, or like an IC card
`installable in an IC card slot, has, for example, a 68-pin
`arrangement conforming with the PCMCIA interface.
`The host interface controller 13, which is used as an
`interface between the host interface 14 and the access
`controller 12, comprises a real track.sector number register
`131, a register 13 representing the access start position, a
`sector count register 133, and a data register 134. These
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`registers can be read from and written into by the host CPU.
`The register 132 is composed of a sector number register
`132a, a cylinder number register 132b, and a head number
`register 132c.
`The real track.sector number register 131 holds the infor
`mation indicating the number of sectors per track allocated
`to the flash EEPROM chips 11-0 through 11-4. This infor
`mation is read by the host CPU. The access start position
`logical address specified by the host CPU is written into the
`access start position register 132. The data representing the
`data length specified by the host CPU is written into the data
`length register 133. The write data inputted from the host
`CPU or the read data outputted to the host CPU is set in the
`data register 134.
`The data buffer 15 holds the write data sent from the host
`CPU or the read data from the flash memories 11-0 through
`11-4. The access controller 12 selects flash EEPROMs 11-0
`through 11-4 and reads and writes data from and into the
`selected flash EEPROM. In this case, the access controller
`12 selectively supplies chip select signals CS-0 through
`CS-4 to the flash EEPROMs 11-0 through 11-4 in order to
`select the flash EEPROM corresponding to the memory chip
`number outputted from the address conversion table 121.
`The access controller 12 counts up the start address so that
`the data of the size generated with the memory address from
`the address conversion table 121 as the start address and sent
`from the host CPU may be read and written.
`Referring to FIG. 7, the principle of allocating addresses
`to the flash EEPROMs 11-0 through 11-4 will be described.
`In FIG. 7, () represents a write unit. In , the numbers 00,
`01, 02, 03, 04, 05, . . . on the left indicate track numbers
`viewed from the host CPU, and the numbers 00, 0, 02,03,
`04, ... on the right indicate sector numbers viewed from the
`host CPU.
`In this way, a write unit for the flash EEPROMs 11-0
`through 11-4 is allocated consecutive sector numbers in the
`same track viewed from the host CPU so that the numbers
`may cover the flash EEPROMs 11-0 through 11-4. With this
`allocation, when the host CPU specifies a write operation for
`five consecutive sectors in the same track, the flash
`EEPROMs 11-0 through 11-4 are written into parallelly,
`enabling parallel write operation on the five sectors.
`FIG. 8 shows a write unit and an erase unit for the flash
`EEPROM 11-0. As shown, the flash EEPROM 11-0 has an
`erase block size of 4K bytes and is designed to perform a
`write operation in pages of 256 by