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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
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`KIOXIA AMERICA, INC. and KIOXIA CORPORATION
`
`Petitioners,
`
`v.
`
`BITMICRO LLC, LLC,
`
`Patent Owner.
`
`Case No.: IPR2023-00742
`U.S. Patent No. 8,010,740
`
`DECLARATION OF R. JACOB BAKER, Ph.D., P.E.
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`KIOXIA Ex-1003, Page 1
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`I. 
`II. 
`
`TABLE OF CONTENTS
`INTRODUCTION ........................................................................................... 1 
`QUALIFICATIONS ........................................................................................ 1 
`A. 
`Industry Experience ............................................................................... 2 
`B. 
`Academic Experience ............................................................................ 6 
`C. 
`Other Relevant Experience .................................................................... 8 
`III.  MATERIALS CONSIDERED ........................................................................ 9 
`IV.  TECHNOLOGY BACKGROUND ............................................................... 12 
`V.  OVERVIEW OF THE ’740 PATENT .......................................................... 14 
`A. 
`Specification of the ’740 Patent .......................................................... 14 
`B. 
`Prosecution History for the ’740 Patent .............................................. 17 
`VI.  LEGAL PRINCIPLES USED IN ANALYSIS ............................................. 18 
`A. 
`Prior Art ............................................................................................... 18 
`B. 
`Anticipation ......................................................................................... 18 
`C. 
`Obviousness ......................................................................................... 19 
`D. 
`Claim Construction ............................................................................. 24 
`VII.  LEVEL OF ORDINARY SKILL IN THE ART ........................................... 25 
`VIII.  CLAIM CONSTRUCTION .......................................................................... 27 
`A. 
`“LBA”.................................................................................................. 27 
`B. 
`“PBA” .................................................................................................. 29 
`C. 
`“FDE” and “FDE identifier” ............................................................... 30 
`D. 
`“group identifier” ................................................................................ 32 
`IX.  OVERVIEW OF THE PRIOR ART ............................................................. 33 
`A. 
`Sukegawa Discloses a LBA to PBA Mapping Table That
`Facilitates Optimized Operations ........................................................ 33 
`Bennett Discloses a Logical‒to‒Physical Address Mapping
`Table That Enables Optimized Operations in Memory Systems ........ 37 
`Bruce Discloses Specific Access Parameters for Solid State
`Memory Systems, Each Having Unique Identifiers ............................ 41 
`
`B. 
`
`C. 
`
`i
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`KIOXIA Ex-1003, Page 2
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`X. 
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`3. 
`
`4. 
`
`5. 
`
`6. 
`
`7. 
`
`8. 
`
`THE PRIOR ART DISCLOSES ALL OF THE CLAIMED
`ELEMENTS OF THE ’740 PATENT ........................................................... 45 
`A. 
`Each of the Challenged Claims Is Anticipated or Rendered
`Obvious by Sukegawa ......................................................................... 45 
`1. 
`Claim 1 Is Anticipated by Sukegawa ........................................ 45 
`2. 
`Claim 9 Is Rendered Obvious by Sukegawa in View of
`Bruce ......................................................................................... 58 
`Claim 10 Is Rendered Obvious by Sukegawa in View of
`Bruce ......................................................................................... 72 
`Claim 11 Is Rendered Obvious by Sukegawa in View of
`Bruce ......................................................................................... 75 
`Claim 12 Is Rendered Obvious by Sukegawa in View of
`Bruce ......................................................................................... 77 
`Claim 13 Is Rendered Obvious by Sukegawa in View of
`Bruce ......................................................................................... 78 
`Claim 14 Is Rendered Obvious by Sukegawa in View of
`Bruce ......................................................................................... 80 
`Claim 15 Is Rendered Obvious by Sukegawa in View of
`Bruce ......................................................................................... 82 
`Claim 32 Is Anticipated By Sukegawa ..................................... 87 
`9. 
`10.  Claim 34 Is Anticipated by Sukegawa .................................... 104 
`Each of the Challenged Claims Is Anticipated or Rendered
`Obvious by Bennett ........................................................................... 109 
`1. 
`Claim 1 Is Anticipated by Bennett .......................................... 109 
`2. 
`Claim 9 Is Rendered Obvious by Bennett in View of
`Bruce ....................................................................................... 124 
`Claim 10 Is Rendered Obvious by Bennett in View of
`Bruce ....................................................................................... 137 
`Claim 11 Is Rendered Obvious by Bennett in View of
`Bruce ....................................................................................... 140 
`Claim 12 Is Rendered Obvious by Bennett in View of
`Bruce ....................................................................................... 142 
`Claim 13 Is Rendered Obvious by Bennett in View of
`Bruce ....................................................................................... 143 
`Claim 14 Is Rendered Obvious by Bennett in View of
`Bruce ....................................................................................... 145 
`Claim 15 Is Rendered Obvious by Bennett in View of
`
`B. 
`
`3. 
`
`4. 
`
`5. 
`
`6. 
`
`7. 
`
`8. 
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`-ii-
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`KIOXIA Ex-1003, Page 3
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`Bruce ....................................................................................... 147 
`Claim 32 Is Anticipated by Bennett ........................................ 152 
`9. 
`10.  Claim 34 Is Rendered Obvious by Bennett in View of
`Bruce ....................................................................................... 169 
`XI.  CONCLUSION ............................................................................................ 172 
`
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`-iii-
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`KIOXIA Ex-1003, Page 4
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`

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`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 8,010,740
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`
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`I, R. Jacob Baker, Ph.D., P.E., declare as follows:
`
`I.
`
`INTRODUCTION
`1.
`I have been retained by KIOXIA Corporation and KIOXIA America,
`
`Inc. (“Petitioners”) as an independent expert in this inter partes review before the
`
`United States Patent and Trademark Office (“PTO”) regarding U.S. Patent No.
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`8,010,740 (“the ’740 patent”), Ex-1001. Specifically, I have been asked to consider
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`whether certain references disclose or suggest the features recited in claims 1, 9-15,
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`32, and 34 of the ’740 patent (“challenged claims”). As explained below, it is my
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`opinion that the challenged claims are invalid as anticipated and/or obvious in view
`
`of the prior art references discussed in this Declaration and the accompanying
`
`Petition.
`
`2.
`
`I am being compensated at my ordinary consulting rate of $655.00 per
`
`hour. No part of my compensation is dependent on the outcome of this proceeding
`
`or any other proceeding involving the ’740 patent or any of its related patents. I have
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`no other interests in this proceeding.
`
`II. QUALIFICATIONS
`3. My qualifications are generally set forth in my Curriculum Vitae, which
`
`is attached as Ex-1004. My Curriculum Vitae also includes a list of the publications
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`I have authored and a list of the other cases in which I have testified during the last
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`-1-
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`KIOXIA Ex-1003, Page 5
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`

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`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 8,010,740
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`four years.
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`4.
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`I have been working as an Engineer since 1985 and have been teaching
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`Electrical and Computer Engineering courses since 1991. I am currently a Professor
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`of Electrical and Computer Engineering at the University of Nevada, Las Vegas
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`(“UNLV”).
`
`5.
`
`I received B.S. and M.S. degrees in Electrical Engineering from UNLV
`
`in 1986 and 1988, respectively. I received my Ph.D. in Electrical Engineering from
`
`the University of Nevada, Reno (“UNR”) in 1993.
`
`6. My doctoral research, culminating in the award of a Ph.D., investigated
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`the use of power MOSFETs in the design of very high peak power, and high-speed,
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`instrumentation. I developed techniques to reliably stack power MOSFETs to switch
`
`higher voltages, that is, greater than 1,000 V and 100 Amps of current with
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`nanosecond switching times. This work was reported in the paper entitled
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`“Transformerless Capacitive Coupling of Gate Signals for Series Operation of
`
`Power MOSFET Devices,” published in the IEEE Transactions on Power
`
`Electronics. The paper received the Best Paper Award in 2000.
`
`A.
`7.
`
`Industry Experience
`I have done technical and expert witness consulting for over 200
`
`companies and their subsidiaries since I started working as an Engineer in 1985.
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`-2-
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`KIOXIA Ex-1003, Page 6
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`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 8,010,740
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`From 1985 to 1993, I worked for EG&G Energy Measurements and the Lawrence
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`Livermore National Laboratory designing nuclear diagnostic instrumentation for
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`underground nuclear weapon tests at the Nevada test site. During this time, I
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`designed, and oversaw the fabrication of, over 30 electronic and electro-optic
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`instruments, including high-speed cable and fiber-optic receiver/transmitters, PLLs,
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`frame and bit-syncs, data converters, streak-camera sweep circuits, Pockel’s cell
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`drivers, micro-channel plate gating circuits, charging circuits for battery backup of
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`equipment for recording test data, and analog oscilloscope electronics.
`
`8. My work during this time, as one example, had a direct impact on my
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`doctoral research work using power MOSFETs, subsequent publishing efforts, and
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`industry designs. In addition to the 2000 Best Paper Award from the IEEE Power
`
`Electronics Society, I published several other papers in related areas while working
`
`in industry. I hold a patent, Patent No. 5,874,830, in the area of power supply design,
`
`titled, “Adaptively biased voltage regulator and operating method,” which was
`
`issued on February 23, 1999. I have designed dozens of linear and switching power
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`supplies for commercial products and scientific instrumentation.
`
`9.
`
`I am a licensed Professional Engineer and have extensive industry
`
`experience in circuit design, fabrication, and manufacture of Dynamic Random
`
`Access Memory (DRAM) semiconductor integrated circuit chips, Phase-Change
`
`-3-
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`KIOXIA Ex-1003, Page 7
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`

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`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 8,010,740
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`Random Access Memory (PCRAM) chips, and CMOS Image Sensors (CISs) at
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`Micron Technology, Inc. (“MTI”) in Boise, Idaho. I spent considerable time
`
`working on the development of flash memory chips while at MTI. My efforts
`
`resulted in more than a dozen patents relating to flash memory. One of my projects
`
`at MTI included the development, design, and testing of circuit design techniques
`
`for a multi-level cell (MLC) flash memory using signal processing. This effort
`
`resulted in higher-density memories for use in solid-state drives and flash memory
`
`cards having an ATA interface that are ubiquitous in consumer electronics, including
`
`cameras and data storage systems. Further, the use of higher-density memory can
`
`result in fewer changes in the flash translation layer for logical-to-physical
`
`addressing, less need for garbage collection, and larger data segments that can
`
`improve a computing system’s performance.
`
`10. Another project I worked on at MTI focused on the design of buffers
`
`for high-speed double-data rate DRAM, which resulted in around 10 U.S. patents in
`
`buffer design. Among many other experiences, I led the development of the delay
`
`locked loop (DLL) in the late 1990s so that MTI DRAM products could transition
`
`to the DDR memory protocol, used in mobile and non-mobile (server, desktop, cell
`
`phones, tablets, etc.) computing systems as main computer memory, for addressing
`
`and controlling accesses to memory via interprocess communications (IPC) with the
`
`-4-
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`KIOXIA Ex-1003, Page 8
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`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 8,010,740
`
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`memory controller (MC). I provided technical assistance with MTI’s acquisition of
`
`Photobit during 2001 and 2002, including transitioning the manufacture of CIS
`
`products into MTI’s process technology. Further, I consulted at Sun Microsystems
`
`and then Oracle on the design of memory modules during 2009 and 2010. This work
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`entailed the design of low-power, high-speed, and wide interconnection methods
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`with the goal of transmitting data to/from the memory module and the MC at higher
`
`speeds.
`
`11.
`
`I have extensive experience in the development of instrumentation and
`
`commercial products
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`in
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`a multitude of
`
`areas
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`including:
`
`integrated
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`electrical/biological circuits and systems, array (memory, imagers, and displays)
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`circuit design, CMOS analog and digital circuit design, diagnostic electrical and
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`electro-optic instrumentation for scientific research, CAD tool development and
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`online tutorials, low-power interconnect and packaging techniques, design of
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`communication/interface circuits (to meet commercial standards such as USB,
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`firewire, DDR, PCIe, SPI, etc.), circuit design for the use and storage of renewable
`
`energy, and power electronics. For example, a part of my research at Boise State, for
`
`many years, focused on the use of Thru-Silicon-Vias (TSVs), aka Thru-Wafer Vias
`
`(TWVs), for high-density packaging. These packaging techniques were utilized in
`
`the memory module development work I did with Sun Microsystems and Oracle. As
`
`-5-
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`KIOXIA Ex-1003, Page 9
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`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 8,010,740
`
`
`another example, I designed circuitry for use in implementing Universal Serial Bus
`
`(USB) interface circuits while consulting at Tower Semiconductor. I designed PCI
`
`communication circuits for IPC between a Graphics Processor Unit (GPU) and
`
`memory while consulting for Rendition, Inc.
`
`12. My current research work is focused in part on the design of integrated
`
`circuits for wireless sensing using LIDAR (LIght Detection And Ranging). I have
`
`worked with several companies in the development of these circuits and systems,
`
`including Freedom Photonics, Aerius Photonics, and FLIR. In the early 1990s, I
`
`worked on wireless systems for wideband impulse radar while at Lawrence
`
`Livermore Laboratory. Further, part of my research for several years focused on the
`
`digitization of IQ channels using delta-sigma modulation. The knowledge and
`
`experience gained from this effort are reflected in my textbook CMOS Mixed-Signal
`
`Circuit Design and a presentation, which I have presented at several universities and
`
`companies, http://cmosedu.com/jbaker/papers/talks/BP_DSM_talk.pdf.
`
`B. Academic Experience
`13.
`I was an adjunct faculty member in the Electrical Engineering
`
`departments of UNLV and UNR from 1991-1993. From 1993 to 2000, I served on
`
`the faculty at the University of Idaho as an Assistant Professor and then as a tenured
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`Associate Professor of Electrical Engineering. In 2000, I joined a new Electrical and
`
`-6-
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`KIOXIA Ex-1003, Page 10
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`

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`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 8,010,740
`
`
`Computer Engineering program at Boise State University (“BSU”), where I served
`
`as department chair from 2004 to 2007. At BSU, I helped establish graduate
`
`programs in Electrical and Computer Engineering including, in 2006, the
`
`university’s second Ph.D. degree. In 2012, I re-joined the faculty at UNLV. Over the
`
`course of my career as a professor, I have advised more than 100 masters and
`
`doctoral students.
`
`14.
`
`I have been recognized for my contributions as an educator in the field.
`
`While at Boise State University, I received the President’s Research and Scholarship
`
`Award (2005), Honored Faculty Member recognition (2003), and Outstanding
`
`Department of Electrical Engineering Faculty recognition (2001). In 2007, I received
`
`the Frederick Emmons Terman Award (the “Father of Silicon Valley”), which is
`
`bestowed annually upon an outstanding young electrical/computer engineering
`
`educator in recognition of the educator’s contributions to the profession. In 2011, I
`
`received the IEEE Circuits and Systems Education Award. I received the Tau Beta
`
`Pi Outstanding Electrical and Computer Engineering Professor Award every year it
`
`was awarded while I have been back at UNLV.
`
`15.
`
`I have authored several books and papers in the electrical and computer
`
`engineering area. My published books include CMOS Circuit Design, Layout, and
`
`Simulation (Baker, R.J., Wiley-IEEE, ISBN: 9781119481515 (4th ed., 2019)) and
`
`-7-
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`KIOXIA Ex-1003, Page 11
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`

`

`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 8,010,740
`
`
`CMOS Mixed-Signal Circuit Design
`
`(Baker, R.J., Wiley-IEEE,
`
`ISBN:
`
`9780470290262 (2nd ed., 2009) and ISBN: 9780471227540 (1st ed., 2002)). I co-
`
`authored DRAM Circuit Design: Fundamental and High-Speed Topics (Keeth, B.,
`
`Baker, R.J., Johnson, B., and Lin, F., Wiley-IEEE, ISBN: 9780470184752 (2008)),
`
`DRAM Circuit Design: A Tutorial (Keeth, B. and Baker, R.J., Wiley-IEEE, ISBN:
`
`0-7803-6014-1 (2001)), and CMOS Circuit Design, Layout and Simulation (Baker,
`
`R.J., Li, H.W., and Boyce, D.E., Wiley - IEEE, ISBN: 9780780334168 (1998)). I
`
`contributed as an editor and co-author on several other electrical and computer
`
`engineering books.
`
`C. Other Relevant Experience
`16.
`I have performed technical and expert witness consulting for more than
`
`200 companies and their subsidiaries and given more than 50 invited talks at
`
`conferences, companies, and universities. Further, I am the author or co-author of
`
`more than 100 papers and presentations in the areas of electrical and computer
`
`engineering design, fabrication, and packaging.
`
`17.
`
`I currently serve, or have served, as a volunteer on the IEEE Press
`
`Editorial Board (1999-2004); as editor for the Wiley-IEEE Press Book Series on
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`Microelectronic Systems (2010-2018); as the Technical Program Chair of the 2015
`
`IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS
`
`-8-
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`KIOXIA Ex-1003, Page 12
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`

`

`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 8,010,740
`
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`2015); on the IEEE Solid-State Circuits Society (SSCS) Administrative Committee
`
`(2011-2016); as a Distinguished Lecturer for the SSCS (2012-2015); the Technology
`
`Editor (2012-2014) and Editor-in-Chief (2015-2020) for IEEE Solid-State Circuits
`
`Magazine; IEEE Kirchhoff Award Committee (2020-2023); and advisor for the
`
`student branch of the IEEE at UNLV (2013-present). These meetings, groups, and
`
`publications are intended to allow researchers to share and coordinate research. My
`
`active participation in these meetings, groups, and publications allows me to see
`
`what other researchers in the field have been doing.
`
`18.
`
`In addition to the above, I am an IEEE Fellow for contributions to
`
`semiconductor memory design and a member of the honor societies Eta Kappa Nu
`
`and Tau Beta Pi.
`
`III. MATERIALS CONSIDERED
`19. My opinions, as set forth in this Declaration, are based on the
`
`documents I have reviewed, my experience and background, and my knowledge and
`
`professional judgment. In forming these opinions, I have reviewed the ’740 patent
`
`(Ex-1001), the prosecution history for the ’740 patent (Ex-1002), the prior art
`
`discussed below, and any other material and information identified in this
`
`Declaration. I have also relied on my experience and knowledge in the field of
`
`computer memory and data storage devices.
`
`-9-
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`KIOXIA Ex-1003, Page 13
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`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 8,010,740
`
`
`
`20.
`
`In particular, my opinions regarding the invalidity of the challenged
`
`claims are based on the following prior art references, as informed by my knowledge
`
`in the field of computer memory and data storage devices.
`
`Exhibit
`
`Description
`
`1005
`
`U.S. Patent No. 5,572,466 (“Sukegawa”). It is my understanding that
`
`Sukegawa was issued on November 5, 1996. Petitioners’ counsel has
`
`informed me that Sukegawa is prior art under pre-AIA 35 U.S.C. §
`
`102(b). See infra § VI.B for a more detailed description regarding my
`
`understanding of this category of prior art.
`
`1006
`
`U.S. Patent No. 5,822,251 (“Bruce”). It is my understanding that
`
`Bruce issued on October 13, 1998. Petitioners’ counsel has informed
`
`me that Bruce is prior art under pre-AIA 35 U.S.C. § 102(b). See infra
`
`§ VI.B for a more detailed description regarding my understanding of
`
`this category of prior art.
`
`1007
`
`U.S. Patent No. 7,139,864 (“Bennett”). It is my understanding that
`
`Bennett was filed on December 30, 2003, and was published June 30,
`
`2005. Petitioners’ counsel has informed me that Bennett is prior art
`
`under pre-AIA 35 U.S.C. § 102(a). See infra § VI.B for a more
`
`detailed description regarding my understanding of this category of
`
`-10-
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`KIOXIA Ex-1003, Page 14
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`

`

`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 8,010,740
`
`
`
`Exhibit
`
`Description
`
`prior art.
`
`Ex-1008 Claim Construction Order and Memorandum in Support Thereof,
`
`BiTMicro LLC v. KIOXIA Am., Inc., Case No. 6:22-cv-00331-ADA,
`
`Dkt. No. 54 (W.D. Tex. Feb. 16, 2023).
`
`Ex-1009 U.S. Patent No. 6,000,006 (“the ’006 patent”)
`
`Ex-1010 U.S. Patent No. 7,506,098 (“the ’098 patent”)
`
`Ex-1013 U.S. Pat. No. 5,404,485 (“Ban”)
`
`Ex-1014 BRIAN DIPERT & MARKUS LEVY, DESIGNING WITH FLASH MEMORY
`
`(Annabooks 1994) (“Dipert”).
`
`Ex-1015 H. Niijima, Design of a Solid-State File Using Flash EEPROM, IBM
`
`JOURNAL OF RESEARCH AND DEVELOPMENT, vol. 39, no. 5, pp. 531-
`
`545, Sept. 1995 (“Niijima”)
`
`Ex-1016 Eran Gal et al., Mapping Structures for Flash Memories: Techniques
`
`and Open Problems, PROCEEDINGS OF THE IEEE INTERNATIONAL
`
`CONFERENCE
`
`ON
`
`SOFTWARE—SCIENCE,
`
`TECHNOLOGY &
`
`ENGINEERING, Herzlia,
`
`Israel,
`
`2005,
`
`pp.
`
`83-92,
`
`doi:
`
`10.1109/SWSTE.2005.14 (“Gal”)
`
`
`
`-11-
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`KIOXIA Ex-1003, Page 15
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`

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`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 8,010,740
`
`
`IV. TECHNOLOGY BACKGROUND
`21. Before June 8, 2006, flash memory devices generally were widely used.
`
`Likewise, the concept of mapping between logical address used by a host and
`
`physical address in the memory, would have been implemented in flash memory
`
`systems and POSITAs would have reliably and predictably known how to do so
`
`22. For example, Flash memory systems utilize a Flash Translation Layer
`
`(FTL) that allows for the mapping (also referred to as “translating,” “indexing,” or
`
`“converting”) of logical addresses to physical addresses and is implemented on the
`
`flash device itself. Ex-1016 at 6-9. Logical addresses are the addresses used by
`
`computer operating systems to identify certain data. Physical addresses indicate a
`
`physical storage location of the data. In platter hard drives, physical addresses would
`
`indicate a cylinder, sector, and/or head of a platter where data is stored. In flash
`
`drives, physical addresses indicate the block (and also usually pages) of flash
`
`memory where data is stored.
`
`23. The FTL was patented by Ban in 1995 in U.S. Pat. No. 5,404,485 titled
`
`“Flash file system,” more than ten years before the priority date for the ’740 patent.
`
`Ex-1013. The FTL was also adopted as part of the PCMCIA standard before the
`
`priority date of the 740 patent. Ex. 1016 at 7. It is used in conjunction with both
`
`wear leveling and garbage collection in flash devices. Ex-1015 at 5-9.
`
`-12-
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`KIOXIA Ex-1003, Page 16
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`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 8,010,740
`
`
`
`24. An FTL is well-known to map the logical to physical addresses using
`
`various data structures, such as an “index,” “table,” or other similar structure. See,
`
`e.g., Ex-1016 at 7-9; Id., Fig. 1; Ex-1005, Figure 11; Ex.-1007, Figures 3B and 17B.
`
`The copy of the FTL table preserved on nonvolatile memory may be a direct copy
`
`(Ex. 1014 at 15-17), an inverse/reverse table (Ex-1015 at 5, Ex. 1016 at 7-9), or some
`
`other structure that allows the FTL table to be reconstructed. During powered
`
`operation, the FTL data structure maintaining the relationship between logical and
`
`physical addresses may be reconstructed in volatile memory, such as SRAM or
`
`DRAM, for faster access and updating. Ex-1015 at 5; Ex-1016 at 6-9.
`
`25. The FTL mapping between logical and physical identifiers is updated
`
`in response to changes in the data. Ex-1016 at 9 (“data structures that map logical
`
`blocks to sectors are updated if necessary, to reflect the relocation”). For example,
`
`if the physical storage location of data is changed (such as due to wear leveling or
`
`garbage collection) then the logical-to-physical address mapping for that data will
`
`be updated to reflect the new physical storage location. Similarly, if data is erased
`
`altogether, then the corresponding logical-to-physical entry may either be deleted
`
`(typically for any mapping is stored in RAM, where erasures are easily performed)
`
`or marked as invalid/erased (more common if the mapping is stored in flash, where
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`erasures are relatively slow). By using an FTL, an operating system can track the
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`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 8,010,740
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`location of data using only the logical address. This simplifies the management by
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`the operating system, which can remain oblivious to where data is physically stored.
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`By using FTLs and operating on logical addresses only, operating systems do not
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`need to know how each and every unique storage device uniquely stores and
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`uniquely updates data in different physical locations-such tracking is offloaded to
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`the FTL.
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`26.
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`In conclusion, well before the January 8, 2006, priority date of the ’740
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`patent, there was a long history of using mapping tables and schemes to correlate
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`logical host addresses with physical addresses in the memory
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`V. OVERVIEW OF THE ’740 PATENT
`A.
`Specification of the ’740 Patent
`27.
`I understand that the application for the ’740 patent was filed on March
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`19, 2009, and claims priority to a parent application filed on June 8, 2006. Claim 1
`
`of the ’740 patent is an independent claim, while claims 9-15 depend from claim 1.
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`Likewise, claim 32 is an independent claim, and claim 34 depends from claim 32.
`
`28. The ’740 patent purportedly relates to “optimizing memory operations
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`in a memory system suitable for use in an electronic storage device.” Ex-1001 at
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`1:16-18. As the ’740 patent acknowledges, use of non-volatile solid state memory
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`was “commonly known” at the time the ’740 patent was filed. Id. at 1:28-32.
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`KIOXIA Ex-1003, Page 18
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`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 8,010,740
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`The ’740 patent further recognizes that “flash memory related techniques that
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`include read-modify-write transactions, wear leveling, bad block management or
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`any combination of these,” as well as the use “flash translation layers,” were
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`similarly well-known at the time of filing. Id. at 1:54-65. Nonetheless, the ’740
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`patent purports to identify a need for “optimizing” memory operations by
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`“increasing the likelihood that . . . the operational load imposed on the storage device
`
`by these memory operations will be optimally distributed across different storage
`
`device resources.” Id. at 2:11-21.
`
`29. The ’740 patent purports to address this alleged need through the use of
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`a “mapping table” that is “disposed to associate” sets of logical block addresses
`
`(“LBAs”) from a host system to physical block addresses (“PBAs”) in a memory
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`store. Id. at Abstract. According to the ’740 patent, the PBAs—which “represent a
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`unique addressable physical memory location” in a memory store—may be
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`“represented” by a set of “access parameter fields.” Id. at 5:30-35. These access
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`parameter fields may include a bus identifier, a flash DMA engine (or “FDE”)
`
`identifier, and a group identifier. Id. at 5:36-38. In other words, the ’740 patent
`
`purports to identify a PBA by listing the bus, DMA engine, and group of flash
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`devices associated with the PBA.
`
`30. Annotated Figure 2 of the ’740 patent, reproduced below, illustrates this
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`KIOXIA Ex-1003, Page 19
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`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 8,010,740
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`LBA to PBA mapping table. In particular, Figure 2 illustrates the access parameters
`
`comprising a bus identifier, FDE identifier, and group identifier.
`
`
`
`31. As explained below, however, logical to physical address mapping
`
`tables were well known before the priority date of the ’740 patent. Both Sukegawa
`
`and Bennett disclose such tables and confirm that they had been in use long before
`
`the priority date of the ’740 patent. Similarly, identifying a unique addressable
`
`physical memory location (or PBA) by the bus, DMA engine (or FDE), and group
`
`of flash devices the DMA engine is connected to was well known before the priority
`
`date of the ’740 patent. Bruce, which was filed nearly a decade before the ’740
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`patent, discloses such identifiers. Moreover, the use of mapping tables, as taught by
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`KIOXIA Ex-1003, Page 20
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`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 8,010,740
`
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`Sukegawa, represents a common design approach to improving memory system
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`performance and allowing for optimization of memory operations, which would
`
`reasonably include the access parameters taught by Bruce. Accordingly, nothing
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`recited in the claims of the ’740 patent would have been novel or non-obvious to a
`
`person of ordinary skill in the art at the time the application for the ’740 patent was
`
`filed.
`
`B.
`32.
`
`Prosecution History for the ’740 Patent
`It is my understanding that, during prosecution, the Examiner did not
`
`apply any prior art references to reject the claims. Instead, I understand that, on
`
`October 25, 2010, the Examiner rejected the claims as failing to comply with the
`
`written description requirement. Ex-1002 at 3-4. In this rejection, the Examiner
`
`stated that the specification “does not describe how the mapping table causes the
`
`storage device to perform optimized memory operation[s] on memory location[s] in
`
`such a way that is understood by one having ordinary skill in the related art.” Id.
`
`33.
`
`I understand that, in a response dated February 25, 2011, the applicant
`
`argued that the specification provided sufficient written description support for the
`
`claims, after which the Examiner issued a Notice of Allowance on April 13, 2011.
`
`Id. at 28-36. Following the Notice of Allowance, I understand that the applicant
`
`made clerical amendments to the claims on July 12, 2011, which were subsequently
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`KIOXIA Ex-1003, Page 21
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`Declaration of R. Jacob Baker
`Inter Partes Review of U.S. Patent No. 8,010,740
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`entered by the Examiner.
`
`VI. LEGAL PRINCIPLES USED IN ANALYSIS
`34.
`I am not an attorney and I offer no opinions on the law. I have been
`
`advised by Petitioners’ counsel of certain legal principles relevant to an invalidity
`
`analysis, as summarized below. I have conducted my analysis in accordance with
`
`these principles.
`
`A.
`35.
`
`Prior Art
`I understand that a patent or other publication must qualify as prior art
`
`before it can be used to invalidate a patent claim.
`
`36.
`
`I understand that a U.S. or foreign patent qualifies as prior art to a
`
`challenged claim if the patent was issued prior to the invention date of the challenged
`
`claim. I also understand that a U.S. or foreign patent or published patent application
`
`qualifies as prior art to a challenged claim if it was published before the invention
`
`date of the challenged claim.
`
`B. Anticipation
`37.
`I understand that a prior art reference “anticipates” an asserted claim,
`
`thereby rendering the claim invalid, if all elements of the cl