I II IIIII II Ill Ill II Ill I Ill 111111111111111
`
`[11]Patent Number:5,692,211
`
`United States Patent
`[19]
`
`Nov. 25, 1997
`[451 Date of Patent:
`
`US005692211A
`
`Gulick et al.
`
`8/1996 Bowes ..................................... 395/294
`
`
`
`5,546,547
`
`
`
`9/1996 Gephardt et al ........................ 395/306
`5,557,757
`
`
`
`9/1996 Dunstan .................................. 395n50
`5,SCi0,022
`
`
`10/1996 Lewis ...................................... 395/154
`5,564,001
`
`
`
`11/1996 Windrem et al .................... 395/514 R
`5,574,662
`
`
`
`
`11/1996 Goodrum .•......•..•......•••.....••••.• 395/500
`5,579,512
`
`
`1/1997 Garrett .................................... 395/281
`5,594,873
`
`FOREIGN PATENT DOCUMENTS
`0 537 932 A3 5/1992 European Pat. Off . .
`OTHER PUBLICIJ'IONS
`
`[54]COMPUTER SYSTEM AND METHOD
`HAVING A DEDICATED MULTIMEDIA
`ENGINE AND INCLUDING SEPARATE
`COMMAND AND DATA PATHS
`
`[75] Inventors: Dale E. Gulick; Andy Lambrecht;
`
`Mike Webb; Larry Hewitt, all of
`
`Austin; Brian Barnes, Round Rock. all
`of Tex.
`
`[21]Appl. No.: SUi,531
`
`[56]
`
`
`
`References Cited
`
`[73]Assignee: Advanced Micro Devices, Inc.,
`
`
`Sunnyvale, Calif.
`Kettler. Kevin A. and Jay K. Strosnider, "Scheduling Analy­
`
`
`
`
`
`sis of the MicroChannel Architecture for Multimedia Appli­
`
`
`
`cations," Department of Electrical and Computer Engineer­
`
`
`
`ing, Carnegie Mellon University. Pittsburgh, PA. May 1994,
`[22]Filed:Sep. 11, 1995
`pp. 403-414.
`[51]Int. Cl.6 ......................................................
`
`PCI Local Bus-PC/ Multimedia Design Guide-Revision
`G06F 13/00
`1.0-Mar. 29, 1994, 43 pages.
`
`
`[52]U.S. Cl .............................................. 395/800; 395/281
`
`
`
`[58]Field of Search ..................................... 395/281, 800,
`
`Primary Examiner-Eric Coleman
`395/842
`
`Firm-Conley, Rose & Tayon; Jeffrey C.
`
`Attorney. Agent, or
`Hood
`[57]
`
`ABSTRACT
`
`U.S. PATENT DOCUMENTS
`The present invention comprises a computer system and
`
`
`
`
`
`
`
`
`
`1/1981 Richter ...................................... 371/68
`4,245,344
`
`
`method optimized for real-time applications which provides
`
`
`
`
`7/1983 Bernstein ................................ 395/800
`4,394,736
`
`
`increased performance over cU1Tent computer architectures.
`
`
`
`2/1991 Davis et al. . ............................. 370n7
`4,991,169
`
`
`
`
`The system includes a dedicated multimedia engine and
`
`
`7/1992 Bland ...................................... 395n25
`5,129,090
`
`
`
`5/1993 Quentin et al .......................... 364/188
`5,208,745
`
`
`
`dedicated multimedia memory coupled directly to the main
`
`
`
`
`9/1993 Di.nwiddie, Jr. et al. ............... 345/115
`5,245,322
`
`
`memory. The computer system includes a data path to the
`
`
`
`
`11/1993 Siegel ...................................... 395/425
`5,261,072
`
`
`main memory and the multimedia memory, and includes a
`
`
`
`1/1994 Nakamura ............................... 395/325
`5,280,589
`
`
`separate command path to the multimedia engine. In one
`
`
`
`
`6/1994 Lewis ...................................•.... 379/90
`5,325,423
`
`
`
`embodiment, the CPU includes a separate command path
`
`
`7 /1994 Koval ...................................... 395/550
`5,333,299
`
`
`
`
`through the chipset logic to the multimedia engine. In an
`
`
`
`
`12/1994 lizuka ...................................... 369/124
`5,373,493
`
`
`4/1995 Carmon et al .......................... 395/650
`5,404,522
`
`
`
`alternate embodiment, the CPU includes a separate com­
`
`
`
`8/1995 Buhro et al ............................... 348/13
`5,440,336
`
`
`mand path to the multimedia engine through the PCl bus. In
`
`
`8/1995 Chen et al .............................. 395/650
`5,440,740
`
`
`
`
`this alternate embodiment, the multimedia engine includes a
`
`
`9/1995 Anderson et al ....................... 395/650
`5,448,735
`
`
`PCl interface which couples to the PCl bus. The multimedia
`
`
`9/1995 Amnri et al. ............................ 395/299
`5,450,551
`
`
`
`engine executes commands and data from the multimedia
`
`
`10/1995 Nonnile et al ......................... 382/304
`5,461,679
`
`memory to perform a number of real-time operations,
`
`
`1/1996 Di.nallo et al. .......................... 395/650
`5,487,167
`
`
`
`3/1996 Hulen et al ............................... 370n9
`5,497,373
`
`
`including audio and video functions, as well as others. Thus
`
`
`
`4/1996 Rossmere et al .......•........... 364/514 A
`5,508,940
`
`
`the computer system of the present invention provides
`
`
`5/1996 Farrell et al ........................... 327/108
`5,519,345
`
`
`
`greater performance for real-time applications than prior
`
`
`
`5/1996 Gilley et al ............................ 395/310
`5,519,839
`systems.
`
`
`
`6/1996 Garbe ................................. 364n28.01
`5,530,661
`
`
`6/1996 McRoberts et al ..................... 395/848
`5,530,902
`
`
`711996 Kim ........................................ 395/280
`5,535,339
`34 Claims, 11 Drawing Sheets
`
`110
`
`MAIN
`MEMORY
`
`106
`
`108
`
`126
`
`124
`
`107
`
`120
`
`Cisco Exhibit 1008
`Cisco et al. v. LS Cloud Storage Technologies
`IPR2023-00733, Page 1 of 22
`
`

`

`102
`
`CPU
`CACHE
`
`106
`
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`MAIN
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`108
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`
`126
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`
`107
`
`120
`
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`
`AT
`150
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`
`160 112
`
`MULTIMEDIA
`MEMORY
`
`166
`
`MULTIMEDIA
`ENGINE
`
`152
`
`172
`AUDIO J..r-115
`DAC
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`Cisco et al. v. LS Cloud Storage Technologies
`IPR2023-00733, Page 2 of 22
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`106
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`
`108
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`
`126
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`107
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`112
`
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`152
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`
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`Cisco Exhibit 1008
`Cisco et al. v. LS Cloud Storage Technologies
`IPR2023-00733, Page 3 of 22
`
`

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`�112
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`166 TRANSFER ::: DUAL PORT
`'162
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`
`....160
`MULTIMEDIA MEMORY
`
`
`
`� 210
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`I
`
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`
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`1/0
`
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`\.
`
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`176
`174
`COMMUNICATION
`AUDIO
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`��
`
`Cisco Exhibit 1008
`Cisco et al. v. LS Cloud Storage Technologies
`IPR2023-00733, Page 4 of 22
`
`

`

`106
`CHIP SET
`108
`104
`ARB I I / I
`161 160
`LOGIC
`MULTIMEDIA
`MEMORY
`1 ts6 164
`
`102
`CPU
`CACHE
`
`124
`126
`NETWORK
`SCSI
`INTERFACE
`ADAPlER
`CONTROLLER
`120
`
`107
`
`HARD
`122-I DISK
`
`s
`
`AT r150
`BRIDGE
`
`152
`I t )
`
`s
`
`110
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`
`.1 '-. L- -
`
`/112
`
`MULTIMEDIA
`ENGINE
`r'176
`112
`�
`115
`I
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`114 lsP�ERS�116
`
`FIG. 4
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`Cisco Exhibit 1008
`Cisco et al. v. LS Cloud Storage Technologies
`IPR2023-00733, Page 5 of 22
`
`

`

`102
`
`CPU
`CACHE
`
`104
`
`110
`
`MAIN
`
`MEMORY
`
`106
`
`CHIP SET
`
`108
`
`' I
`L��cl I
`
`126
`
`124
`
`107
`
`SCSI
`NETWORK
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`CONTROLl.ER
`
`120
`
`160
`
`161
`MULTIMEDIA
`
`MEMORY
`
`112
`
`/
`
`122 HARD
`DISK
`
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`v 150
`BRIDGE
`
`152
`
`MULTIMEDIA
`ENGINE
`
`172 .::1 J;.114 �; 76
`
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`fl
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`VIDEO
`MONITOR
`
`SPEAKERSJ...,--116
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`"' \0
`FIG. 5
`�
`�
`
`Cisco Exhibit 1008
`Cisco et al. v. LS Cloud Storage Technologies
`IPR2023-00733, Page 6 of 22
`
`

`

`U.S. Patent Nov. 25, 1997
`5,692,211
`
`
`Sheet 6 of 11
`
`(0
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`Cisco Exhibit 1008
`Cisco et al. v. LS Cloud Storage Technologies
`IPR2023-00733, Page 7 of 22
`
`

`

`102
`.J..._CPU
`CACHE
`104
`
`106
`
`CHIP SET
`I
`AABI
`
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`
`124
`
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`
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`
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`
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`Cisco Exhibit 1008
`Cisco et al. v. LS Cloud Storage Technologies
`IPR2023-00733, Page 8 of 22
`
`

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`•
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`
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`
`Cisco Exhibit 1008
`Cisco et al. v. LS Cloud Storage Technologies
`IPR2023-00733, Page 9 of 22
`
`

`

`U.S. Patent Nov. 25, 1997
`
`Sheet 9 of 11
`
`5,692,211
`
`
`
`MULTIMEDIA MEMORY
`
`
`
`ADDRESS SPACE
`
`GENERAL
`ADDRESS
`
`SPACE
`
`GENERAL
`ADDRESS
`SPACE
`
`FIG. 9
`
`Cisco Exhibit 1008
`Cisco et al. v. LS Cloud Storage Technologies
`IPR2023-00733, Page 10 of 22
`
`

`

`U.S. Patent Nov. 25, 1997 Sheet 10 of 11 5,692,211
`
`CPU TRANSFERS MULTIMEDIA
`
`DATA TO MAIN MEMORY
`402 -
`ON DATA PATH
`
`I
`
`CPU TRANSFERS DATA
`STRUCTURE TO MULTIMEDIA
`404 -
`ENGINE ON COMMAND PATI-1
`
`I
`
`MULTIMEDIA ENGINE
`
`
`RIORmZES DATA STRUCTURE
`IN COMMAND QUEUE
`
`-P
`
`406
`
`I
`
`408 -
`
`MULTIMEDIA ENGINE
`
`
`ARBITRATES FOR
`MAIN MEMORY
`
`I
`
`MULTIMEDIA ENGINE
`
`
`TRANSFERS MULTIMEDIA
`DATA FROM MAIN MEMORY
`410 -
`
`TO MULTIMEDIA MEMORY
`
`I
`
`412 -
`
`MULTIMEDIA ENGINE
`
`ACCESSES MULTIMEDIA
`DATA FROM
`MULTIMEDIA MEMORY
`
`I
`
`MULTIMEDIA ENGINE
`
`PERFORMS OPERATIONS
`414 -
`
`USING MULTIMEDIA DATA
`
`I
`
`416
`
`MULTIMEDIA ENGINE
`
`
`GENERATES MULTIMEDIA
`OUTPUTS
`
`FIG. 10
`
`Cisco Exhibit 1008
`Cisco et al. v. LS Cloud Storage Technologies
`IPR2023-00733, Page 11 of 22
`
`

`

`U.S. Patent Nov. 25, 1997 Sheet 11 of 11 5,692,211
`
`-.,,
`
`502
`
`CPU TRANSFERS
`
`MULTIMEDIA DATA TO
`MAIN MEMORY ON
`DATA PATH
`
`I
`
`CPU TRANSFERS DATA
`STRUCTURE TO OMA
`504 -
`ENGINE ON COMMAND PATH
`
`I
`
`DMA ENGINE PRIORITIZES
`DATA STRUCTURE
`IN COMMAND QUEUE
`
`506 --
`
`I
`
`_.,
`
`608
`
`OMA ENGINE
`ARBITRATES FOR
`MAIN MEMORY
`
`I
`
`OMA ENGINE
`
`TRANSFERS MULTIMEDIA
`510 DATA FROM MAIN MEMORY
`
`TO MULTIMEDIA MEMORY
`
`I
`
`MULTIMEDIA ENGINE
`ACCESSES MULTIMEDIA
`DATA FROM
`512 -
`
`MULTIMEDIA MEMORY
`
`I
`
`MULTIMEDIA ENGINE
`
`514 PERFORMS OPERATIONS
`
`USING MULTIMEDIA DATA
`
`I
`
`516
`
`MULTIMEDIA ENGINE
`
`GENERATES MULTIMEDIA
`OUTPUTS
`
`FIG. 11
`
`Cisco Exhibit 1008
`Cisco et al. v. LS Cloud Storage Technologies
`IPR2023-00733, Page 12 of 22
`
`

`

`5,692,211
`
`1
`
`FIELD OF THE INVENTION
`
`DESCRIPI1ON OF THE RELATED
`
`ARI'
`
`SUMMARY OF THE INVENTION
`
`COMPUTER SYSTEM AND METHOD
`HAVING A DEDICATED MULTIMEDIA
`ENGINE AND INCLUDING SEPARATE
`COMMAND AND DATA PATHS
`
`2
`video accelerator cards are typically configured with one to
`
`
`
`
`four Megabytes of video RAM. Audio cards, video capture
`
`
`cards, and other multimedia cards are also generally con­
`
`
`figured with dedicated on-board memory. This requirement
`
`
`5 of additional memory adds undesirable cost to the system.
`
`
`
`As multimedia applications become more prevalent, mul­
`
`
`timedia hardware will correspondingly become essential
`
`
`
`
`The present invention relates to a computer system and
`
`
`
`
`components in personal computer systems. Therefore, an
`
`
`
`
`method including a dedicated multimedia engine and mul­
`
`
`improved computer system architecture is desired which is
`
`timedia memory and having separate command and data
`10 optimized for real-time multimedia
`
`applications as well as
`
`
`paths for transferring commands and data to the dedicated
`
`
`
`
`for non-realtime applications. In addition. improved meth­
`
`
`multimedia engine and multimedia memory.
`
`
`
`ods are desired for transferring real-time data to multimedia
`hardware.
`
`Computer architectures generally include a plurality of
`
`
`
`15
`
`
`devices interconnected by one or more various buses. For
`The present invention comprises a computer system and
`
`
`
`
`
`
`
`
`
`example, modem computer systems typically include a CPU
`
`
`method optimized for real-time applications which provides
`
`coupled through bridge logic to main memory. The bridge
`
`
`increased performance over current computer architectures.
`
`
`
`logic also typically couples to a high bandwidth local
`
`
`
`The system includes a dedicated multimedia engine and
`
`
`expansion bus, such as the peripheral component intercon­
`20 dedicated
`
`
`
`multimedia memory coupled directly to the main
`
`nect (PCI) bus or the VESA (Video Electronics Standards
`
`memory. The computer system includes a data path to the
`
`
`Association) VL bus. Examples of devices which can be
`
`
`main memory and the multimedia memory, and includes a
`
`
`
`coupled to local expansion buses include video accelerator
`
`
`separate command path to the multimedia engine. The
`
`
`cards, audio cards. telephony cards, SCSI adapters. network
`
`
`multimedia engine executes commands and data from the
`
`
`interface cards, etc. An older type expansion bus is generally
`25 multimedia memory to perform a number of real-time
`
`
`coupled to the local expansion bus. Examples of such
`
`
`
`operations, including audio and video functions, as well as
`
`
`
`expansion buses included the industry standard architecture
`
`
`
`others. Thus the computer system of the present invention
`
`(ISA) bus, also referred to as the AT bus, the extended
`
`
`
`provides greater performance for real-time applications than
`
`industry standard architecture (EISA) bus, or the rnicrochan­
`prior systems.
`
`
`nel architecture (MCA) bus. Various devices may be coupled
`30
`The computer system includes a CPU coupled to chip set
`
`
`
`
`
`to this second expansion bus, including a fax/modem, sound
`or bridge logic to a memory bus, and main memory is
`card. etc.
`
`
`coupled to the memory bus. The bridge logic also couples to
`for
`
`
`
`Personal computer systems were originally developed
`
`
`a local expansion bus such as the PCI bus. Various devices
`
`business applications such as word processing and
`
`
`may be connected to the PCI bus, including a hard drive,
`
`
`
`
`spreadsheets, among others. However, computer systems are
`35
`
`network interface card, etc. The bridge logic and main
`
`currently being used to handle a number of real time
`
`memory are also coupled through the memory bus or a
`
`
`
`
`
`applications, including multimedia applications having
`
`
`
`
`separate local bus to a dedicated multimedia engine as well
`
`video and audio components, video capture and playback.
`
`
`
`as dedicated multimedia memory. The multimedia memory
`
`
`
`telephony applications, and speech recognition and
`
`
`
`to theengine or external 40 may reside either in the multimedia
`
`
`
`synthesis, among others. These real time applications typi­
`
`
`engine. A direct memory access (DMA) engine is preferably
`
`
`cally require a large amount of system resources and band­
`
`coupled to the multimedia memory, and in one embodiment
`width.
`is comprised in the multimedia engine.
`
`One problem that has arisen is that computer systems
`
`
`The computer system also includes a separate command
`
`
`
`originally designed for business applications are not well
`
`
`the CPU45 path to the multimedia engine. In one embodiment,
`
`
`suited for the real-time requirements of modem multimedia
`
`
`
`includes a separate command path through the chipset logic
`
`
`
`applications. For example, modem personal computer sys­
`
`
`to the multimedia engine. In an alternate embodiment, the
`
`
`
`
`tem architectures still presume that the majority of applica­
`
`
`CPU includes a separate command path to the multimedia
`
`tions executing on the computer system are non real-time
`
`
`engine through the PCI bus. In this alternate embodiment,
`
`
`
`business applications such as word processing and/or
`
`50 the multimedia engine includes a PCI interface which
`
`
`
`spreadsheet applications, which execute primarily on the
`
`
`couples to the PCI bus. Where the multimedia memory is
`
`
`
`main CPU. In general, computer systems have not tradition­
`
`
`
`separate from the multimedia engine, the separate command
`
`
`
`ally been designed with multimedia hardware as part of the
`
`path may be to a DMA engine coupled to the multimedia
`
`
`
`
`system, and thus the system is not optimized for multimedia
`memory.
`
`
`applications. Rather, multimedia hardware is typically
`one or more DSP engines 55 The multimedia engine includes
`
`
`
`designed as an add-in card for optional insertion in an
`
`which comprise either one or more general purpose DSP
`
`expansion bus of the computer system.
`
`engines or dedicated audio and video engines. The one or
`
`
`
`In many cases, multimedia hardware cards situated on an
`
`
`
`more DSP engines couple through one or more J/O channels
`
`
`expansion bus do not have the required access to system
`
`
`
`to respective YO ports, including video. audio and commu-
`
`memory and other system resources for proper operation.
`
`
`
`60 nication ports. The multimedia engine includes video ports
`
`
`
`For example, a multimedia hardware card situated on the
`
`
`for coupling to a video monitor. audio ports for coupling to
`
`
`PCI expansion bus must first arbitrate for control of the PCI
`
`an audio DAC or speakers, and one or more communication
`bus before the device can access system memory. In
`ports.
`
`
`
`addition, since the computer system architecture is not
`According to the present invention, the CPU writes video
`
`
`
`
`
`
`optimized for multimedia, multimedia hardware cards gen­
`
`
`
`65 and/or audio instructions and data to the main memory. The
`
`erally do not make efficient use of system resources. As an
`
`
`CPU also preferably writes transfer information on the
`
`
`
`example, multimedia hardware cards typically include their
`
`
`separate command path to the multimedia engine. preferably
`
`own memory in addition to system memory. For example,
`
`Cisco Exhibit 1008
`Cisco et al. v. LS Cloud Storage Technologies
`IPR2023-00733, Page 13 of 22
`
`

`

`5,692,211
`
`4
`3
`to command buffers comprised in the multimedia engine.
`
`including separate command and data paths according to a
`
`
`
`The transfer information includes the main memory address
`third embodiment of the present invention;
`
`
`where the commands and data reside, the number of bytes of
`
`
`F1G. 8 is a block diagram of a computer system including
`
`
`data, and other transfer information. In one embodiment, the
`
`
`
`memory and a multimedia engine and a separate multimedia
`
`CPU writes transfer commands as well as multimedia data
`
`
`5 including a separate command path through a PCI local bus
`
`instructions through the separate command path to the buffer
`
`
`to the multimedia engine according to a third embodiment of
`
`in the multimedia engine.
`the present invention;
`The multimedia engine uses the transfer commands to
`
`
`
`F1G. 9 illustrates the main memory address space of the
`
`
`retrieve the multimedia data into the multimedia memory. In
`
`main memory and the multimedia memory comprised in the
`
`
`
`one embodiment. a DMA engine comprised in the multime­
`10 multimedia engine;
`
`dia engine uses this infonnation to retrieve the commands
`F1G. 10 is a flowchart diagram illustrating operation of the
`
`and data from main memory into the multimedia memory.
`
`
`computer system of the present invention; and
`
`
`
`The DMA engine preferably operates concurrently with the
`
`F1G. 11 is a flowchart diagram illustrating operation of the
`
`
`
`multimedia engine, thus allowing for improved perfor­
`
`
`
`to an 15 computer system of the present invention according
`
`
`
`mance. The multimedia engine then executes the multimedia
`
`alternate embodiment.
`
`
`instructions from the buffer to process the multimedia data.
`
`
`In this embodiment. the CPU feeds multimedia instructions
`DETAil.ED DESCRIPTION OF THE
`
`
`to the multimedia engine concurrently with the transfer of
`PREFERRED
`EMBODIMENT
`
`multimedia data from the main memory to the multimedia
`20 Incorporation by Reference
`
`engine.
`
`
`Therefore, the present invention comprises a novel com­
`by Tom Shanley and Don Ander­
`
`
`PC/ System Architecture
`
`
`puter system architecture and method which increases the
`
`
`son and available from Mindshare Press. 2202 Buttercup
`
`
`
`performance of real-time applications. A dedicated multi­
`
`
`Dr., Richardson, Tex. 75082 (214) 231-2216, is hereby
`
`media engine and multimedia memory are coupled directly
`
`
`incorporated by reference in its entirety.
`25
`
`
`
`to the main memory. The CPU transfers multimedia data and
`
`
`The Intel Peripherals Handbook. 1994 and 1995 editions,
`
`
`instructions to the main memory and provides transfer
`
`
`
`available from Intel Corporation. are hereby incorporated by
`
`
`information and/or multimedia commands over a separate
`
`
`reference in their entirety. Also, data sheets on the Intel
`command path to the multimedia engine or a dedicated
`
`
`82430FX PCiset chipset, also referred to as the Triton
`
`DMA engine. The inclusion of separate data and command
`
`
`chipset, are hereby incorporated by reference in their
`30
`
`
`paths allows for more efficient computer operations. The
`
`entirety, including the 82430 Cache Memory Subsystem
`
`
`
`CPU is no longer required to perform separate transfers over
`
`data sheet (Order No. 290482-004 ), the 82420/82430 PCiset
`
`
`
`
`the memory bus to different devices, i.e., separate transfers
`ISA and EISA bridge data sheet (Order No. 290483-004),
`
`of multimedia data and transfer commands to the main
`and the Intel 82430FX PCiset Product Brief (Order No.
`
`
`
`memory and the multimedia engine, respectively. Rather, the
`
`297559-001), all of which are available from Intel
`
`CPU performs a data transfer over the memory bus to main
`
`
`
`35 Corporation, Literature Sales, P.O. Box 7641, Mt. Prospect.
`
`
`memory and a command transfer directly to the multimedia
`
`ID. 60056-7641 ( l-800-879-4683), and all of which are
`
`
`
`engine. This allows for more efficient transfers of multime­
`
`hereby incorporated by reference in their entirety.
`
`dia data and commands within a computer system.
`
`
`
`U.S. patent application Ser. No. 08/481.705 titled "Com-
`
`
`40 puter System Having a Dedicated Multimedia Engine
`BRJEF DESCRIPTION OF TIIE DRAWINGS
`
`
`Including Multimedia Memory" and filed Jun. 7, 1995,
`
`
`
`A better understanding of the present invention can be
`
`
`
`whose inventors are Dale Gulick. Andy Lembrecht, Mike
`
`
`
`
`obtained when the following detailed description of the
`Webb, Larry Hewitt and Brian Barnes, and which is assigned
`
`
`
`preferred embodiment is considered in conjunction with the
`
`
`is hereby to the same assignee as the present invention,
`
`following drawings, in which:
`
`45 incorporated by reference in its entirety.
`
`F1G. 1 is a block diagram of a computer system including
`
`
`U.S. patent application Ser. No. 08/474,554 titled "Com­
`
`
`a separate command path to a multimedia engine according
`
`
`puter System Having a Dedicated Multimedia Engine and
`
`to the present invention;
`
`Multimedia Memory" and filed Jun. 7, 1995, whose inven­
`FIG. 2 is a block diagram of a computer system including
`
`
`
`
`tors are Dale Gulick. Andy Lembrecht, Mike Webb, Larry
`
`
`a separate command path through a PCI local bus to the
`
`
`Hewitt and Brian Barnes, and which is assigned to the same
`
`multimedia engine according to an alternate embodiment of 50
`
`
`
`
`
`
`assignee as the present invention. is hereby incorporated by
`the present invention;
`
`reference in its entirety.
`
`F1G. 3 is a block diagram of the multimedia engine of
`U.S. patent application Ser. No. 08/479,870 titled "Com­
`
`
`F1GS. 1 and 2;
`
`puter System and Method for Transferring Commands and
`
`F1G. 4 is a block diagram of a computer system including
`
`
`
`55 Data to a Dedicated Multimedia Engine" and filed Jun. 7.
`
`
`
`a multimedia engine and separate multimedia memory and
`
`1995. whose inventors are Dale Gulick, Andy Lembrecht.
`
`
`
`including separate command and data paths according to an
`Mike Webb. Larry Hewitt and Brian Barnes, and which is
`
`alternate embodiment of the present invention;
`
`
`
`
`assigned to the same assignee as the present invention, is
`
`
`F1G. 5 is a block diagram of a computer system having a
`
`
`hereby incorporated by reference in its entirety.
`
`
`
`
`separate multimedia memory and including a separate com­
`60 Computer System Block Diagram
`
`mand path through a PCI local bus to the multimedia
`Referring now to F1G. 1, a block diagram of a computer
`
`
`
`memory according to an alternate embodiment of the present
`
`system according to the present invention is shown. As
`invention;
`
`shown, the computer system includes a central processing
`
`F1G. 6 is a block diagram of the multimedia engine of
`
`unit (CPU) 102 which is coupled through a CPU local bus
`F1GS. 4 and 5;
`
`
`65 104 to a host/PCUcache bridge or chipset 106. The chipset
`
`
`
`106 includes arbitration logic 107 as shown. The chipset 106
`
`F1G. 7 is a block diagram of a computer system including
`
`
`
`is preferably similar to the Triton chipset available from
`
`
`
`a multimedia engine and separate multimedia memory and
`
`Cisco Exhibit 1008
`Cisco et al. v. LS Cloud Storage Technologies
`IPR2023-00733, Page 14 of 22
`
`

`

`5,692,211
`
`6
`
`5
`Referring now to FIG. 2, an alternate embodiment of the
`
`
`Intel Corporation, including certain arbiter modifications to
`
`
`
`
`computer system of FIG. 1 is shown. In the embodiment of
`
`
`accommodate the multimedia engine of the present inven­
`
`
`FIG. 2. the multimedia engine 112 is coupled to the PCI bus
`tion. A second level or L2 cache memory (not shown) may
`120 as well as to the memory bus 108, and the chip set 106
`
`as desired. be coupled to a cache controller in the chipset,
`
`
`
`
`the PCT bus 120 to the multi­5 provides commands through
`
`The bridge or chipset 106 couples through a memory bus
`
`
`media engine 112. More specifically, the chipset 106 pro­
`108 to main memory 110. The main memory 110 is prefer­
`vides commands through the PCI bus to the command
`ably DRAM ( dynamic random access memory) or BOO
`
`
`buffers 166 in the multimedia engine 112. Thus, in this
`
`(extended data out) memory, or other types of memory, as
`
`
`
`embodiment, the CPU 102 provides data through the
`desired.
`10 memory bus 108 to the main memory 110 and provides
`
`The host/PCI/cache bridge 106 and the main memory 110
`
`commands through the PCI bus 120 to the multimedia
`
`
`also couple through the memory bus 108 to the multimedia
`engine 112.
`
`
`
`engine 112 according to the present invention. The multi­
`
`Arbitration Logic
`media engine 112 performs video and audio processing
`The chipset 106 preferably includes the arbitration logic
`
`
`
`
`
`
`functions. As shown, the multimedia engine 112 preferably
`
`
`107 which determines access to the main memory 110. The
`
`
`includes a video port 172 for coupling to a video monitor
`
`15 arbitration logic 107 is coupled to the CPU 102, the main
`
`114 and an audio port 174 which couples through an audio
`
`
`memory 110 and the multimedia engine 112. The arbitration
`
`
`digital to analog converter ( audio DAC) 115 to speakers 116.
`
`
`logic 107 receives bus requests from each of the CPU 102
`
`
`The audio DAC 115 includes a D/ A converter. such as those
`
`
`and the multimedia engine 112 and grants main memory
`
`
`available from Crystal Semiconductor of Austin, Tex. The
`
`
`
`access to either of the CPU 102 or the multimedia engine
`
`
`
`multimedia engine 112 may also include a communications
`
`20 112. In the preferred embodiment, the CPU 102 has priority
`
`port. In the embodiment shown in FIG. l, the multimedia
`
`
`access to the main memory 110. Alternatively, the memory
`
`
`engine 112 also includes multimedia memory 160. In the
`
`bus 108 is an isochronous bus where each of the CPU 102
`embodiments
`shown in FIGS. 4. 5. 7, and 8, the multimedia
`
`
`and the multimedia engine 112 have guaranteed bandwidth
`
`
`memory 160 is separate from the multimedia engine 112.
`
`and latency on the bus 108 to the main memory 110.
`
`
`The multimedia engine 112 also includes command buffers
`
`
`
`25 Alternative arbitration schemes such as a round robin or
`166 as shown.
`priority based scheme may be used as desired.
`
`
`In the various embodiments of the present invention, the
`
`As mentioned above, the main memory 110 and the
`
`multimedia memory 160 is mapped to the main memory
`
`
`multimedia memory 160 preferably share a common address
`
`address space and thus comprises a portion of the main
`
`
`space. FIG. 9 illustrates the main memory address space,
`
`
`memory address space, as shown in FIG. 9. Thus the
`
`
`
`
`30 wherein the multimedia memory 160 comprises part of the
`
`multimedia memory 160 is available to store non­
`
`
`main memory address space. Thus the multimedia memory
`
`multimedia data as needed. In other words, if the main
`
`
`160 is available to store non-multimedia data as needed. In
`
`memory 110 becomes full and additional memory is needed,
`
`
`this embodiment, the multimedia engine 112 and CPU 102
`the CPU 102 can store code and data in the multimedia
`
`
`must also arbitrate for access to the multimedia memory
`
`memory 160. Thus, the multimedia memory 160 is used for
`
`
`35 160. The multimedia engine 112 preferably has priority
`
`real-time or multimedia data and is also used by the CPU
`
`access to the multimedia memory 160. In one embodiment,
`102 as overflow memory space.
`
`
`
`
`the multimedia engine 112 simply writes one or more bits to
`
`The host/PCI/cache bridge or chipset 106 also interfaces
`
`
`a register in the arbitration logic 107 to gain control of the
`
`
`
`
`to a peripheral expansion bus, preferably a peripheral com­
`
`multimedia memory 160. and the CPU 102 is only granted
`ponent interconnect (PCI) bus 120. In the preferred
`
`
`40 access to the multimedia memory 160 after a certain star­
`embodiment, a PCI local bus is used However. it is noted
`
`
`vation period.
`that other local buses may be used. such as the VESA (Video
`
`Multimedia Engine Block Diagram-FIG. 3
`
`
`
`Electronics Standards Association) VL bus. Various types of
`
`
`Referring now to FIG. 3, a more detailed block diagram
`
`
`devices may be connected to the PCI bus 120. In the
`
`
`illustrating the multimedia engine 112 is shown. In the
`
`embodiment shown in FIG. 1, a hard disk 122 and a network
`
`
`embodiment shown in FIG. 3, the multimedia engine 112
`
`
`
`interface controller 124 are coupled to the PCI bus 120. A 45
`
`
`includes multimedia memory 160. In the embodiment
`
`
`
`SCSI (small computer systems interface) adapter 126 may
`
`shown in FIG. 6, the multimedia engine 112 does not include
`
`also be coupled to the PCI bus 120, as shown. The SCSI
`
`the multimedia memory 160, but rather the multimedia
`
`
`adapter 126 may couple to various SCSI devices, such as a
`
`
`memory 160 is separate from the multimedia engine 112.
`
`CD-ROM drive and a tape drive (both not shown), as
`
`50 In the embodiment of FIG. 3, the multimedia memory 160
`
`
`
`desired. Various other devices may be connected to the PCI
`
`
`is dual ported memory. In this embodiment, a fust port of the
`bus 120. as is well known in the art.
`
`memory 160 couples through the local bus 108 to the main
`
`
`Expansion bus bridge logic 150 may also be coupled to
`
`memory 110. The second port of the multimedia memory
`the PCI bus 120. The expansion bus bridge logic 150
`
`
`
`
`160 couples to one or more DSP engines 210. The multi-
`
`interfaces to an expansion bus 152. The expansion bus 152
`
`
`
`
`
`55 media memory 160 preferably comprises high speed dual
`may be any of varying types, including the industry standard
`
`
`
`
`
`ported VRAM (video random access memory), or dual
`
`architecture (ISA) bus, also referred to as the AT bus, the
`
`
`
`
`
`
`extended industry standard architecture (EISA) bus, or the ported DRAM ( dynamic random access memory). The mul­
`
`timedia memory 160 may also comprise SRAM ( static
`
`
`
`
`microchannel architecture (MCA) bus. Various devices may
`
`random access memory) or EDO (extended data out)
`
`
`be coupled to the expansion bus 152, such as expansion bus
`
`
`
`
`
`60 DRAM. The multimedia engine 112 preferably includes a
`
`memory or a modem (both not shown). The expansion bus
`
`
`dual port DRAM memory controller 162 for controlling the
`
`
`bridge logic 150 may also connect to various peripherals,
`
`
`
`including an interrupt system, a real time clock (RfC) and
`
`
`memory 160. dual port memory functions of the multimedia
`For more information on the operation of a dual port
`
`
`timers. a direct memory access (DMA) system. and ROM/
`
`memory controller, please see the Intel 8207 Dual-Port
`
`
`Hash memory ( all not shown). Alternatively. the above logic
`
`65 Dynamic RAM Controller Data Sheet (Order No. 210463-
`
`
`
`
`is comprised in the chipset 106. In an alternate embodiment,
`
`
`
`
`expansion bus 150, as the computer system does not include
`
`
`007), available from Intel Corporation, which is hereby
`
`incorporated by reference.
`desired.
`
`Cisco Exhibit 1008
`Cisco et al. v. LS Cloud Storage Technologies
`IPR2023-00733, Page 15 of 22
`
`

`

`5,692,211
`
`7
`8
`Io the embodiment shown in FIG. 3. th