UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`GOOGLE LLC,
`Petitioner,
`
`v.
`
`LS CLOUD STORAGE TECHNOLOGIES LLC,
`Patent Owner.
`
`IPR2023-00120
`Patent 10,154,092
`
`PATENT OWNER’S PRELIMINARY RESPONSE TO
`PETITION FOR INTER PARTES REVIEW
`
`Amazon et al. Exhibit 1023 Page 1
`Amazon et al. v. LS Cloud Storage Technologies LLC IPR2023-00733
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`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`GOOGLE LLC,
`Petitioner,
`
`v.
`
`LS CLOUD STORAGE TECHNOLOGIES LLC,
`Patent Owner.
`
`IPR2023-00120
`Patent 10,154,092
`
`PATENT OWNER’S PRELIMINARY RESPONSE TO
`PETITION FOR INTER PARTES REVIEW
`
`Amazon et al. Exhibit 1023 Page 1
`Amazon et al. v. LS Cloud Storage Technologies LLC IPR2023-00733
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`
`
`TABLE OF CONTENTS
`
`1
`I. INTRODUCTION
`1
`II. THE ‘’092 PATENT (EXH1001)
`1
`A. Overview
`4
`B. Claim Construction
`65
`III. THE ASSERTED PRIOR ART
`65
`A. Heil (EX1006)
`7
`B. Nakayama (EX1007)
`8
`C. Gulick (EX1008)
`10
`D. Berman (EXH1009)
`11
`IV. LEVEL OF ORDINARY SKILL IN THE ART
`V. THE PETITION FAILS TO DEMONSTRATE THE CHALLENGED
`CLAIMS ARE UNPATENTABLE
`11
`VA. The PetitionPetitioner Fails to Demonstrate That There Is a Reasonable
`LikelihoodEstablish in Ground 1 that Challenged Claims 1-3,
`11
`That Any Challenged Claim is Unpatentable
`11
`7-12, and 19-23 are Anticipated by Heil under 35 U.S.C. § 102(e)
`1211
`1. Claim 1
`1819
`2. Claims 2-3 and 7-12
`1819
`3. Claim 19
`1920
`34. Claims 20-23
`B. Petitioner Fails to Establish in Ground 2 that Challenged Claims 10 and
`11 are Anticipated by Heil under 35 U.S.C. § 102(b)
`1920
`C. Petitioner Fails to Establish in Ground 3 that Challenged Claims 1-3 and
`6-24 are Obvious over Heil and Nakayama under 35 U.S.C. § 103(a) 20
`1. Claim 1
`20
`2. Claims 2-3 and 6-12
`2021
`3. Claim 13
`2021
`4. Claims 14-18
`2122
`5. Claim 19
`2122
`6. Claims 20-23
`23
`23
`7. Claim 24
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`D. Petitioner Fails to Establish in Ground 4 that Challenged Claim 4 is
`Obvious over Heil, Nakayama, and Gulick under 35 U.S.C. § 103(a) 24 25
`E.. Petitioner Fails to Establish in Ground 5 that Challenged Claim 5
`Obvious over Heil, Nakayama, and Berman under 35 U.S.C. § 103(a) 2425
`VI.I. CONCLUS
`2526
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`TABLE OF AUTHORITIES
`
`Cases
`In re Zletz, 893 F.2d 319, 321, 13USPQ2d 1320, 1322 (Fed. Cir. 1989)
`
`5
`
`Chef America, Inc. v. Lamb-Weston, Inc.,358 F.3d 1371, 1372, 69 USPQ2d 1857
`(Fed. Cir. 2004)
`
`5
`
`Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966)
`
`Statutes
`35 U.S.C. 282(b)
`
`Rules
`37 C.F.R. § 42.100(b)
`
`11
`
`4
`
`4
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`EXHIBIT LIST
`
`Exhibit
`1001
`1006
`1007
`1008
`1009
`2001
`
`Exhibit Title
`ReedGertner (U.S. Pat. No. 10,154,092)
`Heil (U.S. Pat. No. 6,173,374)
`Nakayama (U.S. Pat. No. 5,920,893)
`Gulick (U.S. Pat. No. 5,692,211)
`Berman (U.S. Pat. No. 6,118,776)
`Declaration of Dr. Hassan Zeino, Ph.D.
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`I. INTRODUCTION
`The Board should decline to institute IPR proceedings as to any
`
`Challengeddetermine that Petitioner has not demonstrated that any of challenged
`
`claims 1-24 of U.S. Patent No. 10,154,092 (“the ’092 Patent”) because Petitioner
`
`has not demonstrated that any claim is likely to be foundis unpatentable.
`
`Petitioner has not adequately explained how a person of ordinary skill in the
`
`art (“POSITA”) would approach the problems in the art solved by the ’092 Patent.
`
`Additionally, Petitioner has failed to, for the reasons provided herein, failed to
`
`demonstrate that the cited references anticipate or render obvious every element of
`
`any of the Challenged Claims. More specifically, the Petitioner has failed to cite a
`
`reference that teaches or suggest (and the primary reference teaches away
`
`fromsuggests the element of “a first interface configured to receive input/output
`
`(I/O) traffic from a first host device via a dedicated I/O channel, the I/O traffic
`
`comprising a read command” and “a processor coupled to [a] cache memory, the
`
`processor coupled to [a] storage device via a communication path that is distinct
`
`from the dedicated I/O channel, the processor configured to access the cache
`
`memory during processing of the I/O traffic.”
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`Accordingly, Patent Owner requests that the Board deny the petition for
`
`inter partes reviewhold that the challenged claims are patentable over the art cited
`
`by the Petitioner.
`II.
`THE ‘’092 PATENT (EXH1001)
`
`A.. Overvi
`
`As noted by the Board, (see Paper 7, page 3), the application that issued as
`
`The application that issued as the ’092 Patent is a continuation of application No.
`13/527,126, filed on Jun. 19,
`
`2012, which is a continuation of application No. 10/382,016, filed on Mar. 5,
`2003,
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`which is a divisional of application No. 09/236,409, filed on Jan. 22, 1999.
`The ‘092 Patent is titled “Data Sharing Using Distributed Cache in a
`
`Network of Heterogeneous Computers” and discloses a network of PCs that
`
`includes an I/O channel adapter and network adapter and is configured for
`
`management of a distributed cache memory stored in the plurality of PCs
`
`interconnected by the network. EXH1001, Abstract.
`
`The ’092 Patent discloses a network of PCs including an I/O channel adapter
`
`and network adapter configured for management of a distributed cache memory
`
`stored in the plurality of PCs interconnected by the network. The use of standard
`
`PCs reduces the cost of the data storage system. The use of the network of PCs
`
`permits building large, high-performance, data storage systems. EXH1001,
`
`Abstract.
`
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`Figure 1 – ’092 Patent
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`FIG. 1 of the ’092 Patent, reproduced above, illustrates a network of data
`
`storage systems (131, 132, 133). The PC data storage system 131 services a
`
`plurality of channel attached host processors 111, 112 using dedicated I/O
`
`channels 121, 122, and a plurality of network attached host processors 106, 107
`
`using network link 151, and a plurality of network attached data storage systems
`
`132, 133 using
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` network links 152, 153. PC storage system 132 services channel attached
`
`hosts 157, 158. The ’092 Patent describes a node-based approach using an
`
`exclusive communication channel dedicated between two components, e.g., Host 1
`
`(111) communicates with storage system 131 a central processing unit (CPU) and
`
`a peripheral I/O device, over which dedicated input/output requests are
`
`transmitted, thus precluding sharing of the channel with other CPUs and
`
`peripheral I/O devices. Host 1 is dedicated to using channel 121, while Host 2 is
`
`dedicated to using channel 122; Host 1 cannot communicate through channel 122,
`
`and Host 2 cannot communicate using channel 121. See EXH1001, col. 5, lines
`
`9-16 and FIG. 1 generally.; see also EXH 2001, ¶ [0027].
`
`Hosts 157 and 158 access data storage system 131 indirectly via network
`
`attached data storage system 132, thereby offloading communications protocol
`
`overhead from remote hosts 157, 158. Hosts 106 and 107, without a data storage
`
`system, directly access storage system 131 via network link 151 thereby incurring
`
`communications protocol overhead on hosts 106, 107 and therefore decreasing
`
`performance of applications running on those hosts. See EXH1001, col. 5, 17-24;
`
`see also EXH 2001, ¶1 [0028].
`
`Host 111 accesses remote disk 181 via local data storage system 131, network
`
`link 153, and remote data storage system 133 without incurring protocol overhead on
`
`host 111. Host 157 accesses disk 161 via data storage system 133, network link 152,
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`and data storage system 131 without incurring protocol overhead on host 157. Host
`
`106 directly 30 accesses local disk 161 via network link 151 thereby incurring
`
`protocol overhead. See EXH1001, col. 5, 25-34; see also EXH 2001, ¶1 [0028].
`
`B. Claim Construction
`According to 37 C.F.R. §42.100(b), in an inter partes review, claim terms
`
`are construed using the same standard used in a civil action under 35 U.S.C. §
`
`282(b), including construing the claim in accordance with the ordinary and
`
`customary meaning of such claim as understood by one of ordinary skill in the art
`
`and the
` prosecution history pertaining to the patent. A person of ordinary skill in the
`
`art is defined as having a bachelor's degree in Computer Science, electrical
`
`engineering, or highly related field, and would have had at least two years’
`
`experience in cyber-security systems.
`
`The ordinary and customary meaning of a term may be evidenced by a
`
`variety of sources, including the words of the claims themselves, the specification,
`
`drawings, and prior art. However, the best source for determining the meaning of a
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`claim term is the specification – the greatest clarity is obtained when the
`
`specification serves as a glossary for the claim terms. The words of the claim must
`
`be given their plain meaning unless the plain meaning is inconsistent with the
`
`specification. In re Zletz, 893 F.2d 319, 321, 13USPQ2d 1320, 1322 (Fed. Cir.
`
`1989); Chef America, Inc. v. Lamb-Weston, Inc.,358 F.3d 1371, 1372, 69 USPQ2d
`
`1857 (Fed. Cir.2004).
`
`In accordance with these principles, Patent Owner submits that the terms of
`
`claims 1-4 (and all other challenged claims) of the ’092 Patent are clear on their
`
`face. Patent Owner reserves the right to propose further constructions if necessary.
`
`The Board has, however, and not without justification, inferred a
`
`discrepancy between Patent Owner’s view of the term dedicated channel and the
`
`position of the Petitioner. Patent Owner has, with respect, attempted herein to
`
`address this discrepancy.
`
`III. THE ASSERTED PRIOR ART
`
`A. Heil (EX1006)
`
`Heil, which Petitioner relies on as its Primary reference, describes a system
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` that retrieves data across independent computer nodes of a server cluster by
`
`providing for “I/0 shipping of block” level requests to peer intelligent host-bus
`
`adapters (hereinafter referred to as HBA). EXH1006, Abstract. FIG. 1 of Heil is
`
`reproduced below:
`
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`Heil - Figure 1
`
`According to Heil, Host bus adapter (HBA) 117 has “embedded intelligence”
`
`that allows it to function as an intelligent PCI-to-PCI bridge and as a disk drive
`
`controller for local disks 118. The front-end interface 102 is a PCI-to-PCI Bus bridge
`
`that connects, via PCI bus 117.6, various peripheral 1/0 devices, such as the local
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`drives 118 and Fibre Channel Chip 120, to a centralized system PCI bus 116.5.
`
`Front-end interface 102 is connected to embedded Host-to-PCI Bus bridge 101 via
`
`PCI bus 117.6. The Host-to-PCI Bus bridge 101 adapts the PCI bus 117.6 signals
`
`and internal bus 117.3 signals to allow communications with the embedded HBA
`
`intelligence. See EXH1006, Col. 6-7.
`
`B.. Nakayama (EX100
`Nakayama (EXH1007) describes data storage control that enables data on
`
`various storage media to be shared among host computers having different host
`
`computer input/output interfaces. A control processor checks a host computer
`
`interface management table when a write operation is requested by a host
`
`computer. See EXH1007, Abstract. FIG. 3 of Nakayama is shown below.
`
`FIG. 3 is a block diagram showing the configuration of a disk subsystem
`
`having a cache memory. A disk control 302 is connected to a host computer 300
`
`via a channel control 301 on the host side and is also connected to a host computer
`
`303 via a small computer system interface (SCSI) bus control 304.
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`UNITED STATES PATENT AND TRADEMARK OFFICEUNITED STATES PATENT AND TRADEMARK OFFICEUNITED STATES PATENT AND TRADEMARK OFFICE
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`
`FIG. 3
`300
`-300
`
`HOST
`COMPUTER
`I $
`CHANNEL
`CONTROL
`
`y307
`
`g.qC- 301
`? O r 1-302
`
`COMMON
`
`CONTR
`
`314
`
`13°5
`318-
`
`c
`
`DRIVE
`
`HOST
`
`303
`
`--301 COMPUTERI
`SCSI BUS ,-304
`CONTROL
`Mk
`
`[ CO
`MCP)I7
`
`SCSI I
`
`(317
`
`I I
`
`ac
`O.o
`0 0
`0 cc
`
`cc
`
`c c w
`w
`6 8
`
`306-1
`500
`
`I D
`
`RV
`
`PRI
`
`'
`
`INTER
`
`41)
`
`0 0
`
`0c
`
`1
`
`cc
`
`DRIV
`
`0_JO
`occn
`
`0 O
`
`0 3
`
`CACHE MEMORY
`
`j 309
`
`CACHE
`SLOT
`
`310
`
`316312
`
`311
`
`F i g u r e 3 314- N a k a y a m a I INTERFACE
`
`315
`
`316
`
`DRIVE
`
`DRIVE
`
`Figure 3 - Nakayama
`
`DRIVE
`INTERFACE
`
`C. Gulick (EX1008)
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`which provides “increased performance over [earlier] computer architectures.” See
`
`EXH1008, Abstract. FIG. 1 of Gulick is reproduced below:
`
`Gulick - Figure 1
`
`Figure 1 shows a block diagram of a computer system. The computer system
`
`includes a central processing unit (CPU) cache 102 which is coupled through a CPU
`
`local bus 104 to a host/PCI/cache bridge or chipset 106. See EXH1008, col. 4,
`lines
`
`61-65. The host/PCI/cache bridge 106 and the main memory 110 are coupled via the
`memory bus 108 to the multimedia engine 112. See EXH1008, col. 5, lines 9-11.
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`D. Berman (EXH1009)
`Berman (EXH1009) is directed to a personalized marketing architecture that
`
`uses real-time data and explicit customer
`
`input
`
`to augment marketing
`
`segmentation, analysis and video advertisement delivery. Customer behavior,
`
`preferences, and intentions are monitored and identified to present real-time video
`
`messages. See Ex.1007, Abstract.
`
`Figure 14 - Berman
`FIG. 14 of Berman is reproduced above. FIG. 14 shows a block diagram of the
`
`Berman “fabric.” The fabric is composed of a fabric control module 454, a fabric
`
`router 452, multiple port control modules 451, 474, 475, a switch core module 453,
`
`and optionally one or more bridge modules 455. The Fabric Control module 454
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`controls and configures the rest of the fabric but is not usually involved in the normal
`
`routing of frames. See EXH 1009, col. 11, lines 30-36.
`
`IV. LEVEL OF ORDINARY SKILL IN THE ART
`
`For purposes of this Response, Patent Owner agrees to Petitioner’s
`proffered
`
`level of ordinary skill in the art because it comports with the technology and claims
`
`of the ’092 Patent as well as the asserted prior art.
`
`V. THE PETITION FAILS TO DEMONSTRATE THE CHALLENGED
`CLAIMS ARE UNPATENTABLE
`V. The Petition Fails to Demonstrate That There Is a Reasonable Likelihood
`
`That Any Challenged Claim is Unpatentable
`
`Petitioner has failed to carry its burden to show a prima facie case of
`
`anticipation under 35 U.S.C. § 102 and obviousness under 35 U.S.C. § 103. See
`
`Graham v. Deere Co., 383 U.S. 1, 17–18 (1966). The Board has held that a failure
`
`to adequately identify the differences between the claimed subject matter and the
`
`prior art is fatal to validity challenge. See, Apple, Inc. v. Contentguard Holdings,
`
`Inc., IPR2015-00355, Decision Denying Institution of Inter Partes Review, Paper
`
`9 at 9-10 (P.T.A.B. June 26, 2015 (denying institution for failure to identify the
`
`differences between the claimed subject matter and the prior art).
`
`Petitioner Fails to Establish in Ground 1 that Challenged Claims 1-
`A.
`1-33, 7-12, and 19-23 are Anticipated by Heil under 35 U.S.C. § 102(e)
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`1.. Claim
`
`1.
`Independent claim 1 has been divided into elements for consideration
`by the Petitioner as follows:
`
`[1.pre] An apparatus comprising:
`
`[1.a] a first interface configured to receive input/output (I/O) traffic from a
`
`first host device via a dedicated I/O channel, the I/O traffic comprising a read
`
`command;
`
`[1.b] a second interface configured to receive first data via a network;
`
`[1.c] a cache memory configured to store second data;
`
`[1.d] a storage device configured to store third data; and
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`[1.e] a processor coupled to the cache memory, the processor coupled to the
` storage device via a communication path that is distinct from the dedicated
`
`I/O channel, the processor configured to access the cache memory during
`
`processing of the I/O traffic,
`
`[1.f] the processor further configured to perform an access operation at the
` storage device based on the I/O traffic.
`
`a.
`
`Element [1.A]
`
`Heil does not disclose or suggest element [1.a].
`
`Claim 1 of the ʼ092 Patent recites “a first interface configured to receive
` input/output (I/O) traffic from a first host device via a dedicated I/O
`
`channel, the I/O traffic comprising a read command[.]” (emphasis added).
`
`Petitioner argues that Heil describes a first interface that receives I/O traffic
`As illustrated throughout the ’092 Patent, “dedicated I/O channel” refers to
`
`an exclusive communication channel dedicated between two components, over
`
`which dedicated input/output requests are transmitted, thus precluding sharing of
`
`the channel with other CPUs and peripheral I/O devices. There is a 1 to 1
`correspondence between each Host (e.g., 112) and each channel (e.g., 122) as
`
`illustrated in FIG. 3 of the ’092 Patent below.
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`Figure 3 – ’092 Patent
`There is no sharing of a channel (e.g., Host 1 does not share a channel with
`
`Host 2). There is no instance in which a host element shares a communication
`
`channel with any other host or other component, save the component with which
`
`the host element communicates. Local Host 1 in FIG. 3 physically cannot use
`
`channel 122, just as Local Host 2 cannot use channel 121.
`
`Petitioner argues that Heil teaches element [1.a]. In particular, Petitioner
`
`argues that Heil describes a first interface that receives I/O traffic from a host device
`
`in the form of an interface for a PCI bus bridge 115, PCI bus 116.5, or Front End I/F
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`102 for receiving input from a host system (CPU 100). See excerpt from FIG. 1 of
`
`Heil belowon the next page.
`
`Heil – Figure 1 (excerpt)
`
`Petitioner maps Node 1's Host system to Patent Owner’s claimed “first host”
`
` and elements 115, 116. 5 or 102 to “a first interface” to HBA 117. See EXH2001
`¶
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`[0046]. Petitioner thus maps path 115 to 116.5 to 102 as the dedicated I/O
`
`channel of element [1.a]. See EXH2001 ¶ [0046]. This mapping is not correct.
`
`Indeed, Heil specifically notes that the indicated path (i.e.,
`
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`the path including elements 115, 116.5 and 102) is not dedicated, to-wit: “As
`
`shown in FIG. 1, one HBA services the I/O requests from CPU 1 and CPU2 100.
`
`See EXH2001 ¶ [0046]. One skilled in the art, however, will recognize the load
`
`sharing benefits of allowing a plurality of HBAs to service the local and remote I/O
`
`requests of CPU 1 and CPU 2 100.” Col. 7, lines 36-40. (Emphasis added). See
`
`EXH2001 ¶ [0046]. Heil thus teaches that the identified path is a shared path and
`
`that load balancing and sharing is advantageous over a dedicated path, and hence
`
`teaches away from Patent Owner’s claimed invention. In particular, Heil teaches
`
`use of a shared path and teaches away from a dedicated I/O channel, as recited in
`
`each of the independent claims of the ‘092 patent. (See claim 1 element 1.A as an
`
`example). Heil does not simply offer an alternative or “preferred” solution, but
`
`expressly cautions against the very solution of the claimed invention. See EXH2001
`
`¶ [0046]. Heil’s teaching of a shared path is in direct contradiction to a “dedicated”
`
`I/O channel.
`
`It can be seen that in this indicated path of Heil: element 115 is a PCI bridge
`
`that shares the traffic of and between multiple CPUs 100. This shared
`
`communication path cannot in any sense be reasonably characterized as “dedicated.”
`
`See EXH2001 ¶ [0047].
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`Petitioner asserts “The channel used by the PCI bus bridge 115 and PCI bus
` 116.5 is a dedicated I/O channel because it is a direct, dedicated connection
`
`between the host and the HBA that carries I/O traffic between them. Ex.1006,
`
`6:35-40, 7:36-363737; Ex.1004, ¶72.”
`
`Dr. Franzon declares, “...it is my opinion that a POSITA would understand
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`that the channel used by the PCI bus bridge 115 and PCI bus 116.5 is a dedicated
`
`I/O channel because Heil discloses that I/O traffic between HBA 117 and the
`Node
`
`1 host system utilizes this communication path and it is a direct, dedicated
`
`connection between the host and the HBA that carries I/O traffic between them. (Ex.
`
`1006, 6:35-40, 7:36-37.)” (EXH 1004, paragraph [0072])
`
`Patent Owner respectfully disagrees with Petitioner and Dr. Franzon. Heil
`
`does not disclose “a first interface configured to receive input/output (I/O) traffic
`
`from a first host device via a dedicated I/O channel.” The channel used by the PCI
`
`bus bridge 115 and PCI bus 116.5 is used for other communications besides I/O
`
`requests, for example arbitrary communications among peer CPUs (Heil, Col. 8,
`lines
`
`lines 8-18) and thus the PCI bus bridge 115 and PCI bus 116.5 simply cannot be
`and
`
`and cannot serve as a dedicated I/O channel. Heil, at Col 8, lines 8-18 states:
`
`In the present invention, each CPU within Node 150, Nodes 152, and Node N
`151 does not have direct connectivity to a peer CPU within another node.
`For example, CPU 1 100 does not communicate directly with CPU N+1 135 in
`Node N 151. Instead, Node 150, Nodes 152, and Node N 151 are connected
`via a network communications medium. In the preferred embodiment, a
` Fibre Channel backbone 121 allows each CPU to be connected to peer
`CPU's. One skilled in the art will recognize all node-to-node inter-processor
`communication can occur on this Fibre Channel backbone. 121
`However, the only path to the Fibre Channel backbone 121 from the host
`
`system CPUs 100 and remote system CPUs 135 is over PCI bus bridge 115 and
`PCI
`
`Amazon et al. Exhibit 1023 Page 28
`Amazon et al. v. LS Cloud Storage Technologies LLC IPR2023-00733
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`
`
`bus 116.5, so PCI bus bridge 115 and PCI bus 116.5 are also used to allow a
`channel
` or path for each CPU to be connected to peer CPU’s.
`
`Furthermore, at no point does Heil provide any teaching or suggestion of
`any
` channel in view of the PCI bus bridge 115 and PCI bus 116.5 as taught by
`
`Heil that is dedicated solely to receiving input/output (I/O) traffic from a host
`
`device. Heil teaches away from a dedicated I/O channel as claimed.
`
`b.
`
`Element [1.E]
`
`Heil does not disclose or suggest element [1.e].
`
`Claim 1 of the ’092 Patent recites, “a processor coupled to the cache
`memory,
`the processor coupled to the storage device via a communication path that
`
`is distinct from the dedicated I/O channel, the processor configured to access the
`
`cache memory during processing of the I/O traffic.” See EXH2001, ¶ [0049].
`
`Petitioner’s expert recites, at paragraph 89: “Heil’s Figure 1 shows that the
` communication path from the processor to the storage device—i.e., from
`
`the CPU 117.1 to the local drives 118 via a SCSI interface, annotated below in
`
`red—is distinct from the dedicated I/O channel[.]”
`
`Amazon et al. Exhibit 1023 Page 29
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`
`
`However, in reference to FIG. 1, Heil indicates, “The front-end interface
`
`102 is a PCI-to-PCI Bus bridge that connects, via PCI bus 117.6, various
`
`peripheral I/O devices, such as the local drives 118 and Fibre Channel Chip 120,
`
`to a centralized system PCI bus 116.5.” See EXH1006, Col. 7, lines 1-4; see also
`
`EXH2001, ¶ [0059].
`
`It is clear that front-end interface 102 of Heil cannot be described as
`
`dedicated. Instead, front-end interface 102 connects to and is shared by various
`
`peripheral I/O devices, such as the local drives 118 and Fibre Channel Chip 120,
`
`to PCI bus 116.5. Indeed, front-end interface 102 connects Fibre Channel Chip
`
`120, to PCI bus 116.5, and this connection makes front-end interface 102 part of
`
`the communication path from the processor to storage device. Thus, the
`
`communication path from the processor to the storage device is not distinct in
`
`Heil as stated by the Petitioner’s expert paragraph 89. See EXH2001, ¶ [0052]
`
`(emphasis added).
`
`Heil teaches away fromdoes not teach a dedicated IO channel, because Heil
`
`refers to a load sharing to allow multiple HBA to serve one host, “As shown in
`
`FIG. 1, one HBA services the I/O requests from CPU 1 and CPU2100. One skilled
`
`in the art, however, will recognize, and would recognize, the load sharing benefits
`
`of allowing a plurality of HBAs to service the local and remote I/O requests of
`
`CPU 1 and CPU 2 100. As a node expands its processing power by adding CPUs,
`
`Amazon et al. Exhibit 1023 Page 30
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`
`
`
`additional HBAs may be required to service the additional local and remote I/O
`
`requests.” See EXH1006 Col. 7, lines 36-43.
`
`7, lines 36-43; see also EXH2001, ¶ [0053].
`Thus, one of ordinary skill in the art relying on Heil would have gone in a
`
`different direction than the claimed invention and would not have reasonably
`
`expected success to proceed on the path resulting in the claimed invention. See
`
`EXH2001, ¶ [0054].
`
`None of the other references provided by Petitioner teaches a dedicated I/O
`
`channel, as claimed. See EXH2001, ¶ [0055]. Each of the other cited
`references fails to remedy the
`
`shortcomings of Heil in this regard. See EXH2001, ¶ [0055].
`
`2. Claims 2-3 and 7-12
`
`Heil does not anticipate claims 2-3 and 7-12. Claims 2-3 and 7-12 depend
`
`from claim 1. These claims are valid because each depends from valid claim 1 and
`
`recites additional subject matter.
`
`3. Claim 19
`
`a.
`
`Element [19.A]
`Independent claim 19 of the ’092 Patent recites “a first interface configured
`
`to receive input/output (I/O) traffic from a host computer via a dedicated I/O
`
`channel, the I/O traffic comprising one or more read commands, one or more
`
`write commands, or a combination thereof[.]” (emphasis added). Petitioner alleges
`
`Amazon et al. Exhibit 1023 Page 31
`Amazon et al. v. LS Cloud Storage Technologies LLC IPR2023-00733
`
`
`
`that Heil teaches this element for the same reason that Petitioner alleges that Heil
`
`teaches element [1.a] of claim 1. See Paper 2, page 41. As demonstrated above
`
`however,
` Heil does not teach element [1.a]. See EXH2001, ¶ [0057]. Therefore, Heil
`
`does not teach element [19.a].
`
`b.
`
`Element [19.f]
`Independent claim 19 of the ’092 patent also recites “the processor further
`
`configured to perform one or more access operations at the storage device based on
`
`the I/O traffic, wherein the communication path is distinct from the dedicated I/O
`
`Amazon et al. Exhibit 1023 Page 32
`Amazon et al. v. LS Cloud Storage Technologies LLC IPR2023-00733
`
`
`
`channel[.]” Petitioner alleges that Heil teaches this element for the same reason
`that
`
`Petitioner alleges that Heil teaches element [1.e] of claim 1. See Paper 2, page 42.
`
`As shown above, Heil does not teach or disclose element [1.e]. See EXH2001, ¶
`
`[0058]. Thus, Heil does not teach element [19.f].
`
`34. Claims 20-23
`
`Heil does not anticipate claims 20-23. Claims 20-23 depend from claim 19.
`
`Claims 20-23 are valid at least for the reason that each depends from valid claim
`19
`
`and recites additional subject matter.
`
`B. Petitioner Fails to Establish in Ground 2 that Challenged Claims 10 and
`11 are Anticipated by Heil under 35 U.S.C. § 102(b)
`
`Heil does not anticipate claims 10-11. Claims 10-11 depend from claim 1.
`
`Claims 10-11 are valid because each depends from valid claim 1 and recites
`
`additional subject matter.
`
`Amazon et al. Exhibit 1023 Page 33
`Amazon et al. v. LS Cloud Storage Technologies LLC IPR2023-00733
`
`
`
`C. Petitioner Fails to Establish in Ground 3 that Challenged Claims 1-3 and 6-
`24 are Obvious over Heil and Nakayama under 35 U.S.C. § 103(a)
`1. Claim 1
`
`As shown above, Heil does not teach or suggest elements [1.a] or [1.e]
`
`Nakayama does not cure the deficiencies of Heil with regard to these elements. See
`
`EXH2001, ¶ [0061]. Petitioner does not argue that Nakayama teaches or suggests a
`
`dedicated I/O channel. As noted, Heil affirmatively teaches away from a dedicated
`
`I/O channel as claimed by Patent Owner. See EXH2001, ¶ [0061]. It is improper to
`
`Amazon et al. Exhibit 1023 Page 34
`Amazon et al. v. LS Cloud Storage Technologies LLC IPR2023-00733
`
`
`
`combine references where the references teach away from their combination.
`
`Thus, the Petitioner’s asserted combination of Heil and Nakayama is not proper.
`
`Claim 1 is therefore not obvious, under section 103, in view of Heil and
`
`Nakayama.
`
`2. Claims 2-3 and 6-12
`Heil and Nakayama do not render claims 2-3 and 6-12 obvious. Claims 2-3
`
`and 6-12 depend from claim 1. Claims 2-3 and 6-12 are valid because each
`
`depends from valid claim 1 and recites additional subject matter.
`
`3. Claim 13
`Claim 13 of the ’092 Patent recites, “receiving input/output (I/O) traffic
`
`from a host device via a dedicated I/O channel at a first interface, the I/O traffic
`
`comprising a write command[.]” (element [13.a]) Petitioner argues that Heil
`
`discloses “receiving input/output (I/O) traffic from a host device via a dedicated
`
`I/O
`
`Amazon et al. Exhibit 1023 Page 35
`Amazon et al. v. LS Cloud Storage Technologies LLC IPR2023-00733
`
`
`
` channel at a first interface”. As explained above, this assertion is not
`
`correct. Heil fails to disclose or suggest the above feature.
`
`Claim 13 of the ’092 Patent further recites, “performing one or more access
`
`operations at the storage device based on the I/O traffic, the one or more access
`
`operations utilizing a communication path between a processor and the storage
`
`device, the communication path distinct from the dedicated I/O channel.”
`
`(Element [13.f]). Petitioner argues that Heil discloses this element [13.f] and
`
`refers back to Petitioner’s arguments regarding element [1.e].
`
`Heil does not teach or suggest elements [1.a] or [1.e], for the reasons
`
`provided above. In fact, Heil teaches away from these claimed features. Nakayama
`
`does not cure the deficiencies of Heil with regard to these elements. See EXH2001,
`
`¶1 [0065].
`
`Heil and Nakayama do not and cannot render [13.a] and [13.f] obvious for
`
`at least the same reasons that Heil and Nakayama do not render elements [1.a] or
`
`[1.e] obvious. The asserted combination of Heil and Nakayam is not proper and
`
`cannot be relied on by Petittioner.
`
`4. Claims 14-18
`Heil and Nakayama do not render claims 14-18 obvious. Claims 14-18
`
`depend from claim 13. Claims 14-18 are valid because each depends from valid
`
`claim 13 and recites additional subject matter.
`
`Amazon et al. Exhibit 1023 Page 36
`Amazon et al. v. LS Cloud Storage Technologies LLC IPR2023-00733
`
`
`
`5. Claim 19
`Independent claim 19 of the ’092 Patent recites “a first interface configured
`
`to receive input/output (I/O) traffic from a host computer via a dedicated I/O
`
`channel, the I/O traffic comprising one or more read commands, one or more write
`
`commands, or a combination thereof[.]” (element [19.a]). Petitioner alleges that
`
`Heil teaches this element for the same reason that Petitioner alleges that Heil
`
`teaches element [1.a] of claim 1. See Paper 2, page 41. As explained, however, Heil
`
`does not teach or suggest element [1.a]. See EXH2001, ¶1 [
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