IIII
`
`US005784291A
`Patent Number:
`Date of Patent:
`
`5,784,291
`Jul. 21, 1998
`
`United States Patent (19)
`Chen et al.
`
`11
`45
`
`(54)
`
`75
`
`73
`
`21
`22
`
`63
`
`51
`52
`
`58)
`
`CPU, MEMORY CONTROLLER, BUS
`BRIDGE INTEGRATED CIRCUITS, LAYOUT
`STRUCTURES, SYSTEMAND METHODS
`Inventors: Ian Chen, Houston; Uming Ko, Plano,
`both of Tex.
`Assignee: Texas Instruments, Incorporated.
`Dallas. Tex.
`
`Appl. No.: 705,034
`Filed:
`Aug. 29, 1996
`Related U.S. Application Data
`Continuation of Ser. No. 362,351, Dec. 22, 1994, aban
`doned.
`Int. Cl. ...................... G06F 1700: G06F 9/00
`U.S. Cl. ................. 364/491; 395/800.32: 364/232.8;
`364/732.93: 364/925.5; 364/925.6; 364/927.8
`Field of Search ............................... 395/800, 800.32;
`364/232.8, 232.93, 925.5, 925.6, 927.8.
`491
`
`56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`3,987,418 10/1976 Buchanan ................................ 395/800
`4,144,561
`3/1979 Tu et al. ................................ 395/800
`4,393,464 7/1983 Knapp et al. ........................... 395/800
`4,402,044 8/1983 McDonough et al. .................. 395/800
`4,433,378 2/1984 Leger ...................................... 395/800
`4,527,234 7/1985 Bellay ...
`395/800
`4,626,985 12/1986 Briggs .....
`395/800
`4,649,474 3/1987 Ambrosius, III et al. .............. 395/800
`4,718,037
`1/1988 Thaden .................................... 395/800
`5,123,107 6/1992 Mensch, Jr. ............................. 395/800
`
`5,438,681
`
`8/1995 Mensch, Jr. ............................. 395/800
`OTHER PUBLICATIONS
`Texas Instruments. TI486 Microprocessor Reference Guide,
`PC Systems Logic. 1993.
`Linley Gwennap, Microprocessor Report, "TI Shows Inte
`grated x86 CPU for Notebooks", vol.8, No.2. Feb. 14, 1994.
`pp. 5-7.
`Intel386, SL Microprocessor SuperSet System Design
`Guide. Chapter 2, 1992, pp.2-1-2-10.
`NEC.Preliminary Information, uPD70731 (V805) Oct.
`1993.
`NEC Preliminary Information, uPD70732 (V810) Oct.
`1993.
`NEC.Preliminary Information, uPD70742 (V820) Oct.
`1993.
`NEC, ARC Chip Set c/o MCT-ADR. Address Path Control
`ler and MCT-DP Data Path Controller. Jul. 1993, pp. 1-7.
`TI486 Microprocessor. Reference Guide. 1993.
`Primary Examiner-Meng-Ai T. An
`Attorney, Agent, or Firm-Rebecca Mapstone-Lake; James
`F. Hollander; Richard L. Donaldson
`57
`ABSTRACT
`An integrated circuit includes a single chip (102) that has a
`microprocessor (702), a memory controller unit (718), an
`internal bus (714) connecting the microprocessor (702) and
`the memory controller unit (718), and an external bus to
`internal bus interface circuit (716). The microprocessor
`(102) occupies a substantially rectangular region on a sub
`strate (802). The memory controller unit (718) occupies a
`first strip along one side of the microprocessor unit (702)
`accessible via the bond pads broadside to the first strip.
`Other circuits, systems, and methods are disclosed.
`17 Claims, 52 Drawing Sheets
`
`9
`
`CONFIGURATION
`:
`
`
`
`
`
`
`
`i85 CPU
`CORE
`5-xsie
`*NSTRUTION
`DAiA CACHE
`CLOCK, P.
`AN CONTRO
`
`BUS
`
`ATA ROUTER
`ANC
`
`BRIDGE E. AA BUFFERS
`' is
`
`CRAA
`ARESS
`
`DR
`cCNTROL
`
`AA
`
`
`
`
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 1
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 1 of 52
`
`5,784,291
`
`
`
`N.
`
`S
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 2
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 2 of 52
`
`5,784,291
`
`DOCKING
`PCB
`
`-
`- -
`55 55 55 55
`FIC. 2B
`
`46
`
`
`
`VGA
`PRINTER
`GAME
`LAN
`
`
`
`FIC. 2C
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 3
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 3 of 52
`
`
`
`
`
`
`
`[N] 80d 0NI}{000
`
`5,784,291
`
`æ{ENRE
`
`W31SÅS
`/S'd
`
`TONINO0
`
`
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 4
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 4 of 52
`
`5,784,291
`
`f s
`
`
`
`HSAA 4-H 3
`-o-o-S2------
`t
`HO
`u?)
`cas Li
`
`cy
`
`d
`
`Y
`
`o Co
`o, e
`re
`
`C
`n
`l
`
`
`
`
`
`
`
`s
`
`
`
`
`
`
`
`
`
`
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 5
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet S of 52
`
`5,784,291
`
`
`
`MICROPROCESSOR
`UNIT (MPU)
`102
`
`
`
`CLK
`C/BE
`
`4.
`; : 32
`
`C/BE
`
`SM
`NTR
`MSKCLK
`RQ
`CRDSM
`SPKROUT
`
`PPU
`110
`
`(SOUND)
`
`FIC 6
`
`CARD CONTROL
`UNIT (PCU)
`
`26, 1626 16
`
`s s
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 6
`
`

`

`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 7
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 7 of 52
`
`5,784,291
`
`CLK
`C/BE
`4
`32 AD
`CTRL
`
`32KHZ
`14MHZ
`
`FROM
`PPU
`110 SUSPEND
`SHFCLK
`
`
`
`--
`
`-104T
`
`---
`
`104
`
`E
`
`CLK
`C/BE
`4
`32, AD
`,
`CTRL
`
`t|
`
`d
`
`g
`32-4
`BUS MASTER
`DEVICE(S)
`
`s
`52-4
`SLAVE
`DEVICE(S)
`
`210
`ly
`uj
`f
`
`Q 220
`
`196
`
`52 4
`
`DISPLAY
`CONTROLLER
`14
`
`d
`
`s
`
`- al
`
`s
`
`oted
`
`n
`
`ADJUST
`
`BL
`ADJ
`
`9
`
`16
`
`6
`
`16
`
`16
`
`6
`
`LCD
`
`FRAME
`
`RAM
`
`CRT
`/f N192
`OJ15
`- --
`
`f 190
`21
`
`202
`
`DISPLAY
`204 DRAM 206
`
`.........
`
`FIG.
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 8
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 8 of 52
`
`5,784,291
`
`
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 9
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 9 of 52
`
`5,784,291
`
`FPU /F
`U /
`
`
`
`
`
`
`
`PM I/F
`
`7 O 8
`
`104
`
`
`
`BUS
`BRIDGE
`71
`
`aca-
`
`726
`727
`
`738
`
`BUS
`
`FPU /F
`SYSTEM
`LOGIC
`701 CONFIGURATION
`702
`REGISTERS
`A1
`MISC-- ", k
`722
`8-KBYTE
`7041 (NSTRUCTION/
`DATA CACHE
`CLOCK, PLL
`706 IAND.CONTROL
`728
`POWER
`MANAGEMENT
`
`72
`
`DRAM
`DRAM
`MEMORY
`RC
`ADDRESS
`CONTROLLER
`
`DRAM
`CONTROL
`
`(DATAROUTER
`A
`DRAM
`ND
`(RC
`Y DATA
`DATA BUFFERS
`734
`
`736
`
`818
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 10
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 10 of 52
`
`5,784,291
`
`
`
`or
`
`FLOPPY CTL
`
`DIGITAL FDC
`
`FDD
`
`126.0
`
`EXTERNAL BUS
`TO INTERNAL
`BUS: INTERFACE
`
`TIMER/CNTR
`NTR CNTL
`
`914
`
`.
`
`les. R SERIAL PORT
`
`SERIA PORT
`
`a legs
`936B
`
`SERAL PORT
`
`PFFDC
`
`FIG. 1 1
`
`126.1
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 11
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 11 of 52
`
`5,784,291
`
`1010
`
`156
`
`145 144
`
`11
`
`RTC WELL
`104
`
`901 N
`
`
`
`
`
`BATTERY
`
`O5W
`
`CTL
`
`1012
`
`182
`
`
`
`
`
`
`
`DMA, INTERRUPT,
`|COUNTERS, CLOCKING
`1008-1 PARALLEL
`
`1006
`
`1 6
`
`PC/AT
`26
`
`52
`
`
`
`ROUTER/
`1227 NAe BUFFER
`
`IDE/NON-DE
`
`CONTROL LOGIC
`DYNAMIC
`CLOCK
`DIVIDER
`
`SYSCLK
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 12
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 12 of 52
`
`5,784,291
`
`
`
`
`
`
`
`8 / '01, H.
`
`Z
`|
`
`?a||G)
`
`003 || OCH
`
`ZZ |
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 13
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 13 of 52
`
`5,784,291
`
`104
`
`1203
`
`to
`REOX
`Aeter
`
`CNT2 to
`
`-------------- -
`
`9
`
`HOLD/MPUGNT
`HLDA/MPUREQ
`
`
`
`
`
`
`
`1229
`
`
`
`th' own . .DMAG - pc.
`
`BUS
`1204 - SAVE
`CONTROL
`
`206-1
`
`
`
`- 902
`
`
`
`DREO2
`
`DMA
`DEVICE
`
`1312
`
`
`
`
`
`
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 14
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 14 of 52
`
`5,784,291
`
`PPU
`
`16 - - - - - - - - -
`
`1502
`
`IDEOR
`
`BER,
`
`
`
`,
`BUFFER
`
`8
`
`-
`
`PWRGD5 - N
`
`YES D
`DE DRIVE
`DD(15:0)
`RDWR
`CS
`
`16
`
`
`
`
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 15
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 15 of 52
`
`602A
`
`1602
`
`CONFIG
`
`
`
`
`
`
`
`26
`
`6
`
`PCMCIA PC
`CARD
`INTERFACE
`CONTROLLER
`
`ADDRESS
`
`CONIRO.
`
`1.
`> PC SYSTEM
`NPUTS C 1602B
`PC
`INTERFACE
`CONTROL
`INPUTS/
`OUTPUTS
`
`PCLK
`RSTIN
`FRAME
`TRDY
`IDSEL
`TRDY
`a-
`STOP
`DEVSE
`C/BE3-0
`AD31-0 32
`PAR
`
`
`
`
`
`Pct ADDRESS
`AND DATA
`INPUTS
`
`
`
`1602C
`
`w
`
`1618
`
`FC
`CONF
`
`isis - c. It
`
`ROn 3 or 10
`CRDSM
`TEST
`FDCD7
`SPKROUT
`
`PCU
`112
`
`FIG. 18
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`1615
`
`. POWER MANAGEMENT,
`
`INTERRUPT,
`
`LOGIC
`
`26
`16
`
`PCMCIA PC
`CARD
`NTERFACE
`CONTROLLER
`SLOT B
`
`ADDRESS
`
`CONTROL
`
`5,784,291
`A CA25-0
`A CDATA 5-0
`ABVD/(STSCHG)(RI)
`ABVD2(SPKR)
`ARDY/BSY(IREO)
`A WAT
`A CIS5W
`AWP(OIS16)
`CD-2
`
`ARESET
`ACE-2
`AGP
`A VPPPGM
`AVPP VCC
`AVCC 5
`A VCC-5
`
`1620
`
`BCA25-0
`B CDATA15-0
`BBVD/(STSCHG)(RI)
`B BVD2(SPKR)
`BRDY/BSYOREO)
`WA
`IS 3
`B P O S 6 )
`C D1 as
`O R D
`
`: " R
`
`B R E G
`
`.
`/PRCM R G M
`S E T
`B CE1 re 2
`p
`OX s P
`E W C :
`
`W
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 16
`
`

`

`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 17
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 17 of 52
`
`5,784,291
`
`c
`
`-192,194,196
`
`14
`
`DISPLAY F.
`
`VEEON
`5V ON
`VDC
`
`
`
`BL
`NVERTER
`
`POWER SUPPLY
`
`172
`
`VEE
`
`FDD
`
`126
`
`SERAL PT-130
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 18
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 18 of 52
`
`5,784,291
`
`
`
`
`
`
`
`
`
`
`
`
`
`n?, - Ç00
`- AG=00A00A
`
`
`
`QW30 N000ATO HINOO
`
`
`
`(#NOHS) NOTAG
`
`9008Md
`
`WOZ6
`
`MOTIV8(~~80Z6
`
`MOTIV8
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 19
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 19 of 52
`
`5,784,291
`
`BUTTON
`RESPONSE
`CIRCUIT
`
`ONBTN
`
`SRBTN
`
`BATLOW
`PWRGD5
`RTCRCLR
`
`WCCON
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`DATA ADR
`
`
`
`52 52
`
`
`
`
`
`WS
`OO 0 1 1 0 1 1
`
`STATE
`MACHINE
`2030
`
`WRDATAX
`
`O
`7
`REGISTERS
`
`WREGAXH
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 20
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 20 of 52
`
`5,784,291
`
`2030
`
`
`
`
`
`(0,1)
`STANDBY
`
`
`
`
`
`BATLOW
`INBLRES-P
`SUSPEND
`SRBTNTGR
`OBTNTCR
`XOFF
`RMSKALARM
`
`SIAE
`MACHINE
`CONTROL
`LOGIC
`2035
`
`STOBYTO TEMPTO
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 21
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 21 of 52
`
`5,784,291
`
`2316 29 2312
`3.75
`CLOCK
`SEC.
`DIVIDER
`14 STAGES
`
`920A
`
`.
`
`110
`
`PWRCD5
`
`1 2 4 816
`
`32KH
`
`--
`: 4
`
`2314
`
`2320 'SUSPEND - 14
`R
`430 usec
`P
`OSC
`3, confo
`3.75 sec
`PWGEN
`PWM GEN
`(t
`2332
`2334
`
`
`
`23 18
`
`|
`
`|
`
`|
`
`4KHZ
`
`512Hz/
`3.75sec/
`32KHZ
`4KHZ H
`32KHZ
`
`25.30
`
`BACK
`B:
`LIGHT
`
`MSKCLK
`
`OSC
`OFF
`
`OSC
`STABLE
`OSC
`4M
`STABLE
`
`MASK CLOCK
`GENERATOR
`
`2540
`
`SMI, SYSTEM
`PRD. MANAGEMENT
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`RTCRCLR
`PWRGD5
`
`RESET
`GENERATOR
`
`SWCNTLx
`
`2384.x
`
`DERST
`FDDRST
`CPURST
`XDRST
`
`DEPWR
`FDDPWR
`SUPWR
`PCSPWR
`
`.
`
`4
`
`STDBY TEMP
`TO
`TO
`
`52KHZ
`
`920B
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 22
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 22 of 52
`
`5,784,291
`
`2430
`as F/sa
`D
`2432.1
`2440
`PCS
`ED-R 8 BIT
`>
`CTR D TO
`
`PMU RST
`PCSOTGR
`PCSTCR
`
`FIC 25
`
`
`
`
`
`LicC
`
`9
`
`PMUTIMERS
`REGISTER
`PCs C S
`
`SI U
`
`TIMERS 2550 N 920A
`
`COMTGR
`MASKPCOM
`PTTCR
`MASKPT
`WGATGR
`MASKPVGA
`KBMSTGR
`MASKPKBMS
`
`FDDTCR
`
`DETCR
`
`
`
`
`
`
`
`
`
`
`
`
`
`WSO
`SUSPTGR
`3.75Sec. CLOCK
`
`
`
`HDA
`KBMSTGR
`
`
`
`
`
`
`
`
`
`MASK LOGC
`
`
`
`MASK SYSTEM REG.
`
`
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 23
`
`

`

`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 24
`
`

`

`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 25
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 25 of 52
`
`900}}Md
`
`5,784,291
`NIX10d
`(8XTO)
`
`(VOZ6 u)
`01
`
`Z
`
`
`
`
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 26
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 26 of 52
`
`5,784,291
`
`A
`
`PCLKBJ L L L L L L L L
`B SMTCR
`-1RAP-IGNORE wiNDow
`
`D
`
`Q2
`
`Eos
`(SMIOEZ)
`F Q4
`C
`O5 -
`:
`" *-
`I SMIOUTHE PPU DRIVE
`J SMIN
`--
`
`ill
`ill
`- PPU DRIVE -
`MPU DRIVE-F
`
`FIC. 29
`
`-
`II it
`A switcR
`B
`o, -i- -
`C
`o, --, -
`D
`os -- -
`E.
`Q4
`F
`Q5-
`C
`Q6
`H
`
`LJ
`
`I
`
`K
`
`FIG. 3O
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 27
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 27 of 52
`
`5,784,291
`
`PCU 12
`N 1620
`y
`
`
`
`AREQ l
`TO CRDAORQ,
`AREQLM Dios
`2694
`l
`TO CRDBIORO,
`D RO4
`2696
`D;
`2692
`
`CSC REGA
`7-5-
`
`67
`
`cock, ) as HD
`an
`
`2676
`
`2690
`
`CSC REG B
`7-5-
`
`2674 cL
`2678
`foci) > -ese
`2684.
`T1 " - 53's
`BWARN
`D-I-DO-EP
`BDEAD T
`D SM
`TESTZ
`D. SMENZ
`
`A
`
`2688
`
`B
`
`SMEN
`
`A
`NT AND GEN
`CTRL REGS
`
`REGS
`
`FIG. 31
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 28
`
`

`

`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 29
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 29 of 52
`
`5,784,291
`
`[]OW
`
`[10W01d01SH
`
`[10WW.Hd01SH
`
`8 | |
`
`90/
`
`Ç00000}}Md
`
`- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -)
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 30
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 30 of 52
`
`5,784,291
`
`O 3002
`
`A REG6H
`
`B SUSPX
`C CLOCK
`D MASKCLK
`
`E
`
`284
`
`(2)
`
`G5)
`
`FIC 36
`
`
`
`
`
`FPUCLK
`PCLK
`HDROSCOUT SUSPEND
`X
`32KHZ
`
`
`
`MSKCLK
`
`PCCLK
`|SUSPEND
`32KH:
`MSKCLK
`
`110
`
`FIC 37
`
`
`
`
`
`
`
`KBC CLK
`(16/12/8/4MHz)
`HOHOSC 48M_OUT
`X2
`OSCCLK
`(14.318MHz)
`HOSC 14M OUT
`
`118
`
`114
`
`FIG. 39
`CRDAIORQ
`A CRDBIORQ
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 31
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 31 of 52
`
`5,784,291
`
`52KHZ
`
`
`
`SUSPENDx
`
`70
`------
`702
`
`• • • •
`
`= - • • • • • • • • • • • • •=. - - - - - - No.•* -
`
`FIC 36
`
`le
`- - - - - - - -
`
`m is
`
`won
`
`p is a
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 32
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 32 of 52
`
`5,784,291
`
`
`
`13.SdIHO.
`
`88 'f)I, H.
`
`| x :
`
`300030 80W
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 33
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 33 of 52
`
`5,784,291
`
`HOST DEVICES
`
`
`
`
`
`PCI REQUESTS
`
`
`
`PARKED AGENTS
`
`NO PCI REQUESTS
`
`
`
`PC DEVICES 3 FAIR ROTATION
`
`FIC. 4 O
`
`
`
`PC REQUESTS
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`PARKED
`LOWEST PRIORITY
`
`
`
`
`
`
`
`
`
`
`
`
`
`FIC 41
`
`906
`
`ARBER
`PCI DEVICE
`
`PCI DEVICE
`O
`
`SUPER
`AGENT
`REQUEST
`
`
`
`NO
`SUPER
`AGENT
`REQUEST
`
`SUPER ACENT
`HIGHEST PRIORITY
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 34
`
`

`

`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 35
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 35 of 52
`
`5,784,291
`
`N PPU
`110
`
`914
`4.
`
`INTR
`
`TIMER/COUNTER O
`KEYBOARD CONTROLLER
`
`90
`
`
`
`
`
`CONTROL
`REGISTER
`
`
`
`CREARQ
`CRDBIORO
`CRDSRVRORO
`
`Ross INTERRUPI. von
`CONTROLLER 1
`4
`(MASTER)
`Ros I
`FDC 6 re
`
`CAS 2:0
`
`
`
`IRQ12
`
`
`
`INTERRUPT
`CONTROLLER 2
`
`RQ.
`
`FPUERR13
`RQ14
`RQ15
`
`904
`
`902
`
`B y s
`
`104
`|MPU
`
`102
`
`INTERRUPT
`ROUTER
`3820,3830
`
`IRO
`
`- - - - - - - - - - - - - - - - - - -J
`- - - - - - - - - - - -
`
`7010
`SEN,
`PORT
`hN
`N110
`
`m
`
`is a
`
`N
`
`6N 1-7
`DOCKING
`STATION
`
`6520
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 36
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 36 of 52
`
`5,784,291
`
`--
`INTA
`
`N-SERVICE
`REGISTER
`
`RO-R7
`
`NTERRUPT
`REQUEST
`REGISTER
`
`RESER
`
`INTERRUPT
`MASK
`REGISTER
`
`
`
`
`
`
`
`
`
`PRIORITY
`RESOLVER
`
`NTR
`
`
`
`CASO-CAS2
`
`
`
`CASCADE
`VECTOR
`COMPARATOR
`REGISTER
`FIC 44
`
`I/O ENABLE
`DATA BUS
`
`45.50
`
`APPLICATIONS
`
`
`
`
`
`
`
`
`
`
`
`EVENTS
`NOTIFICATION
`
`APM OS
`(DOS OR WINDOWS)
`
`EVENTS
`
`
`
`CPU DLE
`NOTIFICATION
`
`JNTERRUPTS
`
`EVENTS
`NOTIFICATION
`(SMI)
`
`
`
`COMMANDS
`(BY PROGRAMMING
`CONFIG REGS)
`
`920
`
`PMU
`HARDWARE
`
`
`
`T(ON)/T(OFF) ADJUSTMENT
`(IN STANDBY MODE)
`FIC. 45
`
`4540
`
`POWER MGT
`SOFTWARE
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 37
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 37 of 52
`
`5,784,291
`
`BEGIN
`
`4605 NSET TON TOFF = 50%
`
`4540
`
`
`
`YES
`
`-3 55 MSEC
`
`YES
`4620
`MONITOR KB, MS,
`4650- WGA, HDD, TIMERS AND
`STATUS COUNTERS
`
`4640
`
`
`
`COMPUTE CRITERION
`FUNCTON OF
`TIMERS AND COUNTERS
`
`4675
`
`FIC 46
`
`
`
`
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 38
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 38 of 52
`
`5,784,291
`
`PC (FROM DEVSEL)
`VGA (FROM VGA DEVSEL)
`KBCS+KBNT-MSNT
`DMA REQUEST
`IDE WRITE
`IDE READ
`FDC WRITE
`FDC READ
`PROGRAMMABLE I/O CS
`PROG, MEM. OR /O CS
`COM NT AND CS
`COM2 NT AND CS
`LPT INT AND CS
`RO 10
`IRQ1
`RO15
`
`FIG. 47
`
`DATA BUS
`904
`TIMEOUT PERIOD ADJ
`
`TMEOUT
`TRIGGER
`4720
`
`CLOCK RESETB
`
`
`
`READKPM
`4820
`
`2370
`
`MASK BET AND
`"OR" WITH OTHER
`SM SOURCES
`
`SM
`
`
`
`
`
`XDn
`(OBF FROM KBC)
`
`
`
`TON TOFF
`OF CPU CLK
`
`FIC. 49
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 39
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 39 of 52
`
`5,784,291
`
`3412
`
`sts
`
`f
`
`172
`
`3400
`
`
`
`PWRCD5
`
`MPU
`102 (3475
`
`302 7. / / / / /
`
`140
`
`
`
`ATP/S
`174 FC on
`
`5110
`
`170
`5140
`
`WCC
`SWITCH
`
`W
`CC
`
`BATT P/S
`B1 172FdoNN
`5130
`
`5V, 3.3, 12V LCD CTRL
`WBAT FOR INVERTER
`FIC 51
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 40
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 40 of 52
`
`5,784,291
`
`306
`
`+3.3V +5W
`
`JP5 El -o-
`
`HDR3X1
`
`POWER
`
`C
`
`VCCE
`
`AVPP
`
`AVCC
`
`BWPP
`
`BVCC
`
`A VPPPCM
`
`A VCC-5
`
`WPPN
`HYCC Ipsos
`:
`|AE
`T
`
`+ 12V
`
`+5W
`+3.5W
`
`C
`
`PCU b
`
`agaw---
`
`IN 172
`
`
`
`-
`BWPP PCM
`
`WPP GOODA
`
`PCU
`112
`
`WCCB
`
`A GPI.
`
`B GP1|
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 41
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 41 of 52
`
`5,784,291
`
`
`
`714.
`
`
`
`
`
`32KHZ
`
`5360
`714.
`COOLED DOWN
`
`714
`
`5355
`
`5345
`FIC. 63
`
`
`
`400
`
`5350
`
`
`
`540
`CPuck- COUNTER
`LOAD
`
`
`
`
`
`COOLED
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 42
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 42 of 52
`
`5,784,291
`
`
`
`N PPU 110
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 43
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 43 of 52
`
`5,784,291
`
`102 (110 SAME #)
`
`2
`
`
`
`156 150 136155 105
`157
`CTRL
`104
`A
`
`I/F
`
`CORE
`
`208
`
`
`
`
`
`FIG. 66
`
`FIG. 57
`
`
`
`110
`
`KBCSNPEN
`
`SPKDATA
`
`
`
`TM2GATE
`
`OUT2
`GATE2
`TIMER 2
`
`TO SPKROUT PIN
`
`M
`
`OUT2
`(TO PORT B BIT 5 READ)
`FIG. 60
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 44
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 44 of 52
`
`5,784,291
`
`FIC. 58A
`COST
`FUNCTION
`
`
`
`ZONE OF MINIMUM
`CONSTRAINED COST
`
`5830
`
`f
`
`MERIT FUNCTION: COST (N.N2.N3)
`CONSTRAINT: F (N1,N2,N3)=0
`
`(N1+N2 + N3=CONST)
`
`
`
`ASSEMBLY
`COST
`
`5810
`f
`
`5816
`
`5814
`
`5812
`
`FIC 58B
`
`(PIN NR)
`Ni=1,2,3
`
`FIG. 58C
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 45
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 45 of 52
`
`5,784,291
`
`r
`6110 65 6120
`
`ACTIVITY
`REGISTER
`
`
`
`RTCPWR
`
`1932
`
`VCC
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 46
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 46 of 52
`
`5,784,291
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 47
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 47 of 52
`
`5,784,291
`
`SA
`SA
`SLOT 1 SLOT 2
`
`SA
`SLOT n
`
`
`
`
`
`OTHER OR
`MULTIPLE
`CONNECTORS
`
`SLOT 1
`
`PC
`SLOT m
`
`)
`
`76
`
`FIC. 64
`
`
`
`
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 48
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 48 of 52
`
`5,784,291
`
`
`
`MC
`6720 CAMERA
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 49
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 49 of 52
`
`5,784,291
`
`
`
`X/
`
`s’
`
`
`
`SYSTEM
`CONTROL
`
`WRELESS
`MODEM
`
`ya
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 50
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 50 of 52
`
`5,784,291
`
`WB1SÅS
`/Sd
`
`TOHIN00
`
`
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 51
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 51 of 52
`
`5,784,291
`
`||LEISTNI
`
`/6- - - -nr----
`
`
`
`|| ||
`
`||
`||
`
`
`i SENIT ;BUVOX,
`
`TWNOIS9Ç6
`
`
`H:|}-{DI JOWIN?TEJ
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 52
`
`

`

`U.S. Patent
`
`Jul. 21, 1998
`
`Sheet 52 of 52
`
`5,784,291
`
`CONDITION 12. 1:
`DMADDESS -----C-------
`A
`(DRIVEN BY CHIP 6920)
`B MEMR (PSEUDO TOISA) V-V
`C
`IowR to Isa
`\-/
`DONIS ---------------------------- -C-----------
`(FROM CHIP 6920)
`FIG. 71A
`
`CONDITION 12.2:
`PMAADDRESS -----C-------
`(DRIVEN BY CHIP 6920)
`/
`V
`MEMRf
`low - - -
`
`A
`
`B
`C
`
`D EVSE
`
`FIC. 71 C
`
`CONDITION 2.1.2:
`D'APESS ----C-------
`(DRIVEN BY CHIP 6920)
`MEMWii
`\
`-/
`V-/
`
`D
`(FROM CHIP 6920)
`
`------------------------- KO-------------
`FIC. 71 D
`
`B
`C
`
`D
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 53
`
`

`

`5,784,291
`
`1
`CPU, MEMORY CONTROLLER, BUS
`BRIDGE INTEGRATED CIRCUITS, LAYOUT
`STRUCTURES, SYSTEM AND METHODS
`This application is a Continuation of application Ser. No.
`08/362,351, filed on Dec. 22, 1994, entitled CPU,
`MEMORY CONTROLLER, BUS BRIDGE INTEGRATED
`CIRCUITS, LAYOUT STRUCTURES, SYSTEM AND
`METHODS, now abandoned.
`
`5
`
`10
`
`15
`
`20
`
`2
`high-end desktop computers called workstations based on a
`number of superscalar and other very-high-performance
`microprocessors such as the SuperSPARC microprocessor
`have been introduced.
`In a further development, a notebook-size or palm-top
`computer is optionally battery powered for portable user
`applications. Such notebook and smaller computers chal
`lenge the art in demands for conflicting goals of
`miniaturization, ever higher speed. performance and
`flexibility, and long life between battery recharges. Also, a
`desktop enclosure called a docking station has the portable
`computer fit into the docking station, and improvements in
`such portable-computer/docking-station systems are desir
`able. Improvements in circuits, integrated circuit devices,
`computer systems of all types, and methods to address all the
`just-mentioned challenges, among others, are desirable, as
`described herein.
`
`SUMMARY OF THE INVENTION
`Generally, and in one form of the invention, an integrated
`circuit chip has a microprocessor, a memory controller unit,
`an internal bus connecting the microprocessor and the
`memory controller unit, and an external bus to internal bus
`interface circuit. The microprocessor occupies a substan
`tially rectangular region on the substrate. The memory
`controller unit occupies a first strip along one side of the
`microprocessor unit accessible via the bond pads broadside
`to the first strip.
`Other systems. circuits and methods are also claimed.
`BRIEF DESCRIPTION OF THE DRAWINGS
`In the drawings:
`FIG. 1 is a pictorial diagram of two notebook computer
`embodiments, one of them being inserted into a docking
`station embodiment to provide a combined system embodi
`ment
`FIG. 2A, 2B and 2C are right-side profile view, plan view,
`and rear elevation of the combined system of notebook and
`docking station of FIG. 1;
`FIG. 3 is an electrical block diagram of the FIG. 1
`combined embodiment system of improved notebook com
`puter and docking station system to which the notebook
`computer system connects;
`FIG. 4 is an electrical block diagram of another embodi
`ment of an improved computer system for desktop. note
`book computer and docking station applications;
`FIGS. 5, 6 and 7 are three parts of a more detailed
`electrical diagram (partially schematic, partially block) of a
`preferred embodiment electronic computer system for use in
`embodiments including those of FIGS. 3 and 4, wherein
`FIG. S shows MPU and PCU, F.G. 6 shows PPU and
`peripherals, and FIG. 7 shows display controller and other
`elements;
`FIG. 8 is a plan view of a preferred embodiment apparatus
`having a printed wiring board and electronic components of
`the computer system of FIGS. 5-7:
`FIG. 9 is a block diagram of a microprocessor unit (MPU)
`device embodiment for the system of FIGS. 5-7;
`FIG. 10 is a plan view of an integrated circuit with
`improved topography for implementing the microprocessor
`unit of FIG. 9;
`FIG. 11 is a block diagram of a peripheral processing unit
`(PPU) device embodiment for implementing the PPU in the
`system of FIGS. 5-7;
`
`NOTICE
`(C) Copyright, *M* Texas Instruments Incorporated
`1994. A portion of the disclosure of this patent document
`contains material which is subject to copyright and mask
`work protection. The copyright and mask work owner has no
`objection to the facsimile reproduction by anyone of the
`patent document or the patent disclosure, as it appears in the
`Patent and Trademark Office patent file or records, but
`otherwise reserves all copyright and mask work rights
`whatsoever.
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`The following simultaneously filed. coassigned patent
`applications are hereby incorporated herein by reference:
`
`Ser. No.
`
`FLING DATE TCASE NO.
`
`08/363, 198
`08/363,109
`08/363,673
`08/363,098
`08/362,669
`08/363,325
`08/363,543
`08/363,450
`08/363,459
`08/362,2O1
`08/363,449
`08/362,032
`08/362,351
`08/362,288
`08/362,637
`08/362,033
`08/362,701
`O8/363,661
`08/362,702
`
`12-22-94
`12-22-94
`12-22-94
`12-22-94
`12-22-94
`12-22-94
`12-22-94
`12-22-94
`12-22-94
`12-22-94
`12-22-94
`12-22-94
`12-22-94
`12-22-94
`12-22-94
`12-22-94
`12-22-94
`12-22-94
`12-22-94
`
`T-18329
`TI-18533, abandoned
`T1-18536, abandoned
`TI-18538, abandoned
`TI-18540, abandoned
`TI-18541, abandoned
`TI-18902.
`TI-19880, abandoned
`TI-20173
`TI-20174, U.S. Pat. No. 5,568,589.
`TI-20175, abandoned
`TI-20177
`TI-20178, abandoned
`TI-20180, abandoned
`TI-2018
`T-20182
`T-2O183, abandoned
`T-20185
`T1-20186
`
`25
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`30
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`35
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`Other patent applications and patents are incorporated herein
`by reference by specific statements to that effect elsewhere
`in this application.
`FIELD OF THE INVENTTON
`This invention generally relates to electronic circuits,
`computer systems and methods of operating them.
`BACKGROUND OF THE INVENTION
`Without limiting the scope of the invention, its back
`ground is described in connection with computer systems, as
`an example.
`Early computers required large amounts of space. occu
`pying whole rooms. Since then minicomputers and desktop
`computers entered the marketplace.
`Popular desktop computers have included the "Apple"
`(Motorola 680x0 microprocessor-based) and "IBM
`compatible" (Intel or other x86 microprocessor-based)
`65
`varieties. also known as personal computers (PCs) which
`have become very popular for office and home use. Also,
`
`55
`
`LENNOX EXHIBIT 1027
`Lennox Industries Inc. v. Rosen Technologies LLC, IPR2023-00715, Page 54
`
`

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`5,784,291
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`3
`FIG. 12 is a plan view of an integrated circuit with
`improved topography for implementing the peripheral pro
`cessing unit of FIG. 11;
`FIG. 13 is an electrical block diagram of another embodi
`ment of an improved computer system for desktop and other
`applications;
`FIG. 14 is a more detailed block diagram of a bus
`interface block for the embodiment of FIG. 11;
`FIG. 15 is a more detailed block diagram of DMA (Direct
`Memory Access) circuity relating to the circuitry embodi
`ments of FIGS. 11 and 14;
`FIG. 16 is a block diagram of an improved BIOS address
`ing circuit interconnecting the PPU of FIG. 11 with a BIOS
`flash memory;
`FIG. 17 is a block diagram of interconnection of the PPU
`of FIG. 11 with BIOS ROM, KBC (Keyboard Controller),
`add-on chips and IDE hard disk drive in the system embodi
`ment of FIGS. 5-7:
`FIG. 18 is a block diagram of a peripheral control unit
`(PCU) device embodiment to accept insertable cards for the
`system of FIGS. 5-7;
`FIG. 19 is a plan view of an integrated circuit with
`improved topography for implementing the peripheral con
`trol unit of FIG, 18;
`FIG. 20 is a block diagram of selected power and control
`interconnections between the MPU, PCU. PPU, power
`supply, display circuitry and peripherals in the system
`embodiment of FIGS. S-7:
`FIG. 21 is a partially block, partially schematic diagram
`of a PPU circuit embodiment connecting to ON/OFF and
`SUSPEND/RESUME button circuitry, docking station con
`nector circuitry and a power supply in various circuit
`embodiments;
`FIG. 22 is a block diagram of a part 920B of a power
`management circuit embodiment for use in a PPU of FIG.
`11;
`FIG. 23 is a state transition diagram of power manage
`ment states in a preferred embodiment of the power man
`agement system of FIG. 22. as well as circuitry for same and
`40
`method of operation;
`FIG. 24 is a block diagram of another part 920A of the
`power management circuit embodiment in the PPU of FIG.
`11;
`FIG. 25 is a partially schematic and partially block
`diagram of a timers block 2350 in FIG. 24;
`FIG. 26A-B are partially schematic and partially block
`diagrams of non-linear timer embodiments for use in some
`of the timers of FIG. 25:
`FIG. 27 is a partially schematic and partially block
`diagram of a mask clock generator 2340 embodiment in
`FIG. 23 connected to clock circuitry in the MPU of FIGS. 5,
`9, 33 and 36, together with waveform diagrams;
`FIG. 28 is a partially schematic and partially block
`diagram of a system management interrupt circuitry 2370
`embodiment in FIG. 24;
`FIG. 29A-J are waveform diagram of clock signals and
`control signals showing an improved method of operation
`and further describing the operation of the SMI circuitry of
`FIG. 28:
`FIG. 30A-K are further waveform diagram of clock
`signals and control signals showing an improved method of
`operation and further describing the operation of the SMI
`circuitry of FIG. 28;
`65
`FIG. 31 is a partially schematic and partially block
`diagram of a system management interrupt circuitry 1620
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`55
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`4
`embodiment in the PCU of FIG. 18 which is interconnected
`with the PPU of FIG. 11 and MPU of FIG. 9 to form a
`distributed power management system embodiment of
`FIGS. 31, 28, 33 and 34 interrelated with the computer
`system embodiment of FIGS. 5-7;
`FIG. 32A-L are waveform and process of operation
`diagram of clock signals and control signals in circuitry of
`FIG. 34 in the MPU of FIG. 5:
`FIG. 33 is a schematic diagram of a power management
`circuitry embodiment in the MPU supplied with the signals
`of FIGS. 32 and 34;
`FIG. 34 is a further schematic diagram of a power
`management circuitry embodiment in the MPU for supply
`ing a Resume signal to the circuitry of FIG. 33;
`FIG. 35A-E are waveform and process of operation
`diagram for selected signals in the circuitry of FIG. 33;
`FIG. 36 is a partially block, partially schematic diagram
`of a clocking and control circuitry embodiment of the MPU
`of FIG. 5;
`FIG. 37 is a block diagram of frequency-determining
`crystal connections and clock lines in the system embodi
`ment of FIG. 5-7;
`FIG. 38 is a block diagram showing an interrupt routing
`system using one or more PCUs connected to an interrupt
`routing circuitry embodiment in the PPU. with outputs for
`connection to the MPU, detailing the system embodiment of
`FIGS. 5-7;
`FIG. 39A-B are waveform and process of operation
`diagram for selected signals in the circuitry of FIG. 38;
`FIG. 40 is a process of operation diagram for fair rotation
`in arbitration;
`FIG. 41 is a more detailed process of operation diagram
`for arbitration by the arbiter 906 of the PPU of FIG. 11;
`FIG. 42 is a more detailed block diagram of a fast internal
`PPU bus 904 with parallel port 938 embodiment of the PPU
`of FIG. 11;
`FIG. 43 is a more detailed block diagram of interrupt
`routing circuitry in the PPU of FIG. 38;
`FIG. 44 is a more detailed block diagram each interrupt
`controller block of FIG. 43:
`FIG. 45 is a flow diagram of a process or method of
`operation of the preferred embodiment system of FIGS. 5-7;
`FIG. 46 is a flow diagram of a process or method of
`operation for power management adjustment of a TONT.
`OFF register of FIG. 27 in the preferred embodiment system
`of FIGS. 5-7;
`FIG. 47 is a block diagram of a system activity timer
`e