exhibitsticker.com
`
`Exhibit #
`
`Baker 07
`
`01/10/2024 - JL
`
`IPR2023-00697
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`
`
`Multipliers
`
`[ Name |__Symbol Value
`terra
`T
`10"
`
`
`giga
`G
`-
`10”
`mega
`M (MEG inSPICE)
`10°
`
`kilo
`k
`10°
`|
`
`milli
`|
`m
`10:
`
`micro
`|
`ut (or u)
`10°
`
`nano
`n
`10°
`
`pico
`|
`p
`10°"
`
`femto
`f
`10?
`atto
`a (not used in SPICE)
`“10°8
`
`
`
`
`
`Physical Constants
`
` Symbol = Value/Units
`
`
`Vacuum dielectric
`E,
`8.85 aF/um
`
`
`constant
`
`
`
`Silicon dielectric
`constant
`
`6,
`
`11,7g,
`
`
`
`
`
`SiO, dielectric
`constant
`
`3.97,
`
`16e,
`SIN, dielectric
`constant
` Boltzmann’s constant
`1.38 * 107 J/K
`Electronic charge
`Temperature
`
`Kelvin
`
`16x 10°C
`
`Thermalvoltage
`
`
`
`kT/q = 26 mV @300K|
`
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`CMOS
`
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`IEEE Press
`445 Hoes Lane
`Piscataway, NJ 08854
`
`IEEE Press Editorial Board
`Lajos Hanzo,Editor in Chief
`
`R. Abari
`J. Anderson
`F. Canavero
`T. G. Groda
`
`M. El-Hawary
`B. M. Hammerii
`M. Lanzerotti
`O. Malik
`
`S. Nahavandi
`W. Reeve
`T. Samad
`G. Zobrist
`
`Kenneth Moore, Director of IEEE Book and Information Services (B/S)
`
`IEEE Solid-State Circuits Society, Sponsor
`
`IPR2023-00697
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`

`CMOS
`
`Circuit Design, Layout, and Simulation
`
`Third Edition
`
`R. Jacob Baker
`
`IEEE Press Series on Microelectronic Systems
`
`Stuart K. Tewksbury and Joe E. Brewer, Series Editors
`
`IEEE
`
`IEEE PRESS
`
`@)WILEY
`
`A JOHN WILEY & SONS, INC., PUBLICATION
`
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`Copyright © 2010 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved.
`
`Published by John Wiley & Sons, Inc., Hoboken, New Jersey.
`Published simultaneously in Canada.
`
`Nopart of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or
`by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as
`permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior
`written permission of the Publisher, or authorization through paymentof the appropriate per-copy fee to
`the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, (978) 750-8400, fax
`(978) 750-4470, or on the web at www.copyright.com. Requests to the Publisher for permission should
`be addressed to the Permissions Department, John Wiley & Sons,Inc., 111 River Street, Hoboken, NJ
`07030, (201) 748-601 1, fax (201) 748-6008, or online at http://www.wiley.com/go/permission.
`
`Limit of Liability/Disclaimer of Warranty: While the publisher and author have used their best efforts in
`preparing this book, they make no representations or warranties with respect to the accuracy or
`completeness of the contents of this book andspecifically disclaim any implied warranties of
`merchantability or fitness for a particular purpose, No warranty may he created or extendedby sales
`representatives or written sales materials. The advice and strategies contained herein may not be suitable
`for your situation, You should consult with a professional where appropriate. Neither the publisher nor
`author shall be liable for any loss of profit or any other commercial damages, including but not limited
`to special, incidental, consequential, or other damages.
`
`For general information on our other products and services or for technical support, please contact our
`Customer Care Department within the United States at (800) 762-2974, outside the United States at
`(317) 572-3993 or fax (317) 572-4002.
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`Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may
`notbe available in electronic format. For information about Wiley products, visit our web site at
`www. wiley.com.
`
`Library ofCangress Cataloging-in-Publication Data:
`
`Baker, R. Jacob, 1964-
`CMOS; circuit design, layout, and simulation / Jake Baker. — 3rd ed.
`p. cm.
`Summary: “The third edition of CMOS: Circuit Design, Layout, and Simulation continues to cover the
`practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a
`wide range of analog/digital circuit blocks, the BSIM model, data converter architectures, and much
`more. The 3rd edition completes the revised 2nd edition by adding one more chapter (chapter 30) at the
`end, which describes on implementing the data converter topologies discussed in Chapter 29. This addi-
`tional, practical information should make the book even more useful as an academic text and companion
`for the working design engineer.
`Images, data presented throughout the book were updated, and more
`practical examples, problemsare presented in this new edition to enhancethe practicality of the book”—
`Provided by publisher.
`Summary: “The third edition of CMOS: Circuit Design, Layout, and Simulation continues to cover the
`practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a
`wide range of analog/digital circuit blocks, the BSIM
`model, data converter architectures, and much more"— Provided by publisher.
`ISBN 978-0-470-88 132-3 (hardback)
`|. Metal oxide semiconductors, Complementary—Design and construction. 2. Integrated circuits—
`Design and construction. 3. Metal oxide semiconductor field-effect transistors.
`[. Title.
`TK7871.99.M44B35 2010
`621.39'732—de22
`
`2010016630
`
`Printed in the United States of America.
`
`W998 7654321
`
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`To mywife Julie
`
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`Brief Contents
`
`Chapter1 Introduction to CMOS Design
`Chapter 2 The Well
`Chapter 3 The Metal Layers
`Chapter4 The Active and Poly Layers
`Chapter 5 Resistors, Capacitors, MOSFETs
`Chapter 6 MOSFET Operation
`Chapter 7 CMOS Fabrication by Jeff Jessing
`Chapter 8 Electrical Noise: An Overview
`Chapter 9 Models for Analog Design
`Chapter 10 Models for Digital Design
`Chapter 11 The Inverter
`Chapter 12 Static Logic Gates
`Chapter 13 Clocked Circuits
`Chapter 14 Dynamic Logic Gates
`Chapter 15 VLSI Layout Examples
`Chapter 16 Memory Circuits
`Chapter 17 Sensing Using AZ Modulation
`Chapter 18 Special Purpose CMOSCircuits
`Chapter 19 Digital Phase-Locked Loops
`Chapter 20 Current Mirrors
`Chapter 21 Amplifiers
`Chapter 22 Differential Amplifiers
`Chapter 23 Voltage References
`Chapter 24 Operational Amplifiers |
`Chapter 25 Dynamic Analog Circuits
`Chapter 26 Operational Amplifiers II
`Chapter 27 Nonlinear Analog Circuits
`Chapter 28 Data Converter Fundamentals by Harry Li
`Chapter 29 Data Converter Architectures by Harry Li
`Chapter 30 Implementing Data Converters
`Chapter 31 Feedback Amplifiers with Harry Li
`
`vi
`
`1
`31
`59
`83
`105
`131
`161
`213
`269
`311
`331
`353
`375
`397
`411
`433
`483
`523
`551
`613
`657
`711
`745
`773
`829
`863
`909
`931
`965
`1023
`1099
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`Contents
`
`Preface
`
`XXxi
`
`Chapter 1 Introduction to CMOS Design
`1.1 The CMOSIC Design Process 11... .660scesseee tee ceseeieieeeees
`1.1.1 Fabrication
`
`Layout and Cross-Sectional Views
`Te CMOS Backsraund!
`4 iccsonscicatinge sat cage eae ater ae aeke eel
`The CMOSAcronym
`CMOS Inverter
`
`The First CMOS Circuits
`
`Analog Design in CMOS
`OAM Hioduction to SPICES ©
`
`a. <eae vps wis Waele veo mabey VARY eee ns
`
`Generating a Netlist File
`Operating Point
`Transfer Function Analysis
`The Voltage-Controlled Voltage Source
`An Ideal Op-Amp
`The Subcircuit
`
`DC Analysis
`Plotting IV Curves
`Dual Loop DC Analysis
`Transient Analysis
`The SIN Source
`
`An RC Circuit Example
`Another RC Circuit Example
`AC Analysis
`Decades and Octaves
`
`Decibels
`
`onanom
`
`ooo
`
`10
`
`11
`
`12
`
`13
`
`13
`
`14
`
`15
`
`15
`
`16
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`17
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`18
`
`19
`
`20
`
`20
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`Vill
`
`Contents
`
`Pulse Statement
`
`Finite Pulse Rise time
`
`Step Response
`Delay and Rise time in RC Circuits
`Piece-Wise Linear (PWL) Source
`Simulating Switches
`Initial Conditions on a Capacitor
`Initial Conditions in an Inductor
`
`Q of an LC Tank
`
`Frequency Response of an Ideal Integrator
`Unity-Gain Frequency
`Time-Domain Behaviorof the Integrator
`Convergence
`Some CommonMistakes and Helpful Techniques
`Chapter 2 The Well
`The Substrate (The Unprocessed Wafer)
`A Parasitic Diode
`
`Using the N-well as a Resistor
`2 PASTS: tates ccoactsmiataaaliil dagirbieacacneendce deg aeee een ele
`2.1.1 Patterning the N-well
`2.2 Laying Out the N-well
`..............-2-22-220-005220seeeee
`2.2.1 Design Rules for the N-well
`2.3 Resistance Calculation ................ ccc cece cece nee
`
`Layout of Corners
`2.3.1 The N-well Resistor
`
`2.4 The N-well/Substrate Diode .................00..220 02000
`
`2.4.1 A Brief Introduction to PN Junction Physics
`Carrier Concentrations
`
`Fermi Energy Level
`2.4.2 Depletion Layer Capacitance
`2.4.3 Storage or Diffusion Capacitance
`2.4.4 SPICE Modeling
`2.5 The RC Delay through the N-well
`RC Circuit Review
`
`.............00.eeeeeee
`
`Distributed RC Delay
`Distributed RC Rise Time
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`21
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`52
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`26 TWir Well ProGGSS@S:
`
`cavcansacevyesvece pea stibveearantbracsreerss 52
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`Contents
`
`Design Rules for the Well
`SEM Viewsof Wells
`
`53
`55
`
`59
`Chapter 3 The Metal Layers
`S21 Fhe: Banding) Pad ccdccss se csk ioc detep dckaniacaatmncackigedtas 59
`3.1.1 Laying Out the Pad |
`60
`Capacitance of Metal-to-Substrate
`60
`Passivation
`62
`
`62
`An Important Note
`3.2 Design and Layout Using the Metal Layers ................00005 63
`3.2.1 Metal1 and Via
`63
`
`An Example Layout
`3.2.2 Parasitics Associated with the Metal Layers
`Intrinsic Propagation Delay
`3.2.3 Current-Carrying Limitations
`3.2.4 Design Rules for the Metal Layers
`Layout of Two Shapesor a Single Shape
`A Layout Trick for the Metal Layers
`3.2.5 Contact Resistance
`
`63
`64
`65
`68
`69
`69
`69
`70
`
`3.3 Crosstalk and Ground Bounce ....... 200.0 c cece eee eee eee 71
`
`3.3.1 Crosstalk
`
`3.3.2 Ground Bounce
`
`DC Problems
`
`AC Problems
`
`A Final Comment
`
`71
`
`72
`
`72
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`72
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`74
`
`3.4: Layout Examples i020. ccc 5s eect ae cass ene see aes cuacemas cade TS
`3.4.1 Laying Out the PadII
`75
`3.4.2 Laying Out Metal Test Structures
`78
`SEM View of Metal
`79
`
`83
`Chapter 4 The Active and Poly Layers
`4.1 Layout Using the Active and Poly Layers ....... AREAL BAA gle 83
`The Active Layer
`83
`The P- and N-Select Layers
`84
`The Poly Layer
`86
`Self-Aligned Gate
`86
`The Poly Wire
`88
`Silicide Block
`89
`
`4.1.1 Process Flow
`
`89
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`90
`Damascene Process Steps
`4.2 Connecting Wires to Poly and Active .......-......2-2...22.---. 92
`Connecting the P-Substrate to Ground
`93
`Layout of an N-Well Resistor
`94
`Layout of an NMOS Device
`95
`Layout of a PMOSDevice
`96
`A Comment Concerning MOSFET Symbols
`96
`Standard Cell Frame
`97
`
`98
`Design Rules
`4.3 Electrostatic Discharge (ESD) Protection ............. even 100
`Layout of the Diodes
`100
`Chapter 5 Resistors, Capacitors, MOSFETs
`105
`BW ReSIStors: 223. ciasaas shad aperteascdede pau ctemtaauwiny cham ebep bas 105
`
`105
`Temperature Coefficient (Temp Co)
`106
`Polarity of the Temp Co
`107
`Voltage Coefficient
`109
`Using Unit Elements
`110
`Guard Rings
`110
`Interdigitated Layout
`114
`Common-Centroid Layout
`113
`Dummy Elements
`Sie CAPACHOND: agieraplaathereinacuns wacy Lasiaaedaneamsmennnieak 113
`Layout of the Poly-Poly Capacitor
`114
`Parasitics
`115
`
`116
`Temperature Coefficient (Temp Co)
`116
`Voltage Coefficient
`Sa MOSRENS 3:02 aghisc chisegsaeecen al aalessadaetdanaieveaaad 116
`
`Lateral Diffusion
`
`Oxide Encroachment
`
`Source/Drain Depletion Capacitance
`Source/Drain Parasitic Resistance
`
`116
`
`116
`
`117
`118
`
`120
`Layout of Long-Length MOSFETs
`121
`Layout of Large-Width MOSFETs
`123
`A Qualitative Description of MOSFET Capacitances
`5.4 Layout Examples .............-...20022-0-eeeeeee cece ee eeeene 125
`Metal Capacitors
`125
`Polysilicon Resistors
`127
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`Contents
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`Xi
`
`131
`Chapter 6 MOSFETOperation
`6.1 MOSFET Capacitance Overview/Review .............0.000005 132
`Case |; Accumulation
`132
`
`CaseII: Depletion
`CaseIII: Strong Inversion
`Summary
`B22 The Threshold Voltage:
`Contact Potentials
`
`133
`133
`135
`':4s)2cs\roseus 2 classlesia: segs clacsaue veces 135
`137
`
`140
`Threshold Voltage Adjust
`6.3 IV Characteristics of MOSFETS ............0.. 20.000 cece eee 140
`
`144
`6.3.1 MOSFET Operation in the Triode Region
`143
`6.3.2 The Saturation Region
`145
`Cgs Calculation in the Saturation Region
`6.4 SPICE Modeling of the MOSFET .........--.--..-.-.-.---.-- 145
`Model Parameters Related to V,,,,
`146
`Long-Channel MOSFET Models
`146
`Model Parameters Related to the Drain Current
`146
`
`SPICE Modeling of the Source and Drain Implants
`Summary
`6.4.1 Some SPICE Simulation Examples
`Threshold Voltage and BodyEffect
`6.4.2 The Subthreshold Current
`
`147
`147
`148
`148
`149
`
`6.5 Short-Channel MOSFETS ........ccccreeeveesneeeee eeeives 151
`
`Hot Carriers
`
`Lightly Doped Drain (LDD)
`6.5.1 MOSFETScaling
`6.5.2 Short-Channel Effects
`
`Negative Bias Temperature Instability (NBT1)
`Oxide Breakdown
`
`Drain-Induced Barrier Lowering
`Gate-Induced Drain Leakage
`Gate Tunnel Current
`
`6.5.3 SPICE Models for Our Short-Channel CMOS
`Process
`
`BSIM4 ModelListing (NMOS)
`BSIM4 ModelListing (PMOS)
`Simulation Results
`
`151
`
`151
`152
`153
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`xil
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`Contents
`
`161
`Chapter 7 CMOSFabrication by Jeff Jessing
`7.1 CMOS Unit Processes oc ancreaseedsdeedidsrataccdpeaWubsiaas 161
`
`7.1.1 Wafer Manufacture
`
`Metallurgical Grade Silicon (MGS)
`Electronic Grade Silicon (EGS)
`Czochralski (CZ) Growth and Wafer Formation
`7.1.2 Thermal Oxidation
`
`7.1.3 Doping Processes
`lon Implantation
`Solid State Diffusion
`
`7.1.4 Photolithography
`Resolution
`
`Depth of Focus
`Aligning Masks
`7.1.5 Thin Film Removal
`
`161
`
`162
`162
`162
`163
`
`165
`165
`166
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`167
`168
`
`168
`170
`170
`
`170
`Thin Film Etching
`171
`WetEtching
`171
`Dry Etching
`173
`Chemical Mechanical Polishing
`173
`7.1.6 Thin Film Deposition
`175
`Physical Vapor Deposition (PVD)
`176
`Chemical Vapor Depositon (CVD)
`7.2 CMOSProcessIntegration ..........-..ccceecu cece sees eee ees 177
`FEOL
`177
`
`BEOL
`
`CMOSProcess Description
`7.2.1 Frontend-of-the-Line Integration
`Shallow Trench Isolation Module
`
`Twin Tub Module
`
`Gate Module
`
`Source/Drain Module
`
`7.2.2 Backend-of-the-Line Integration
`Self-Aligned Silicide (Salicide) Module
`Pre-Metal Dielectric
`
`Contact Module
`
`Metallization 1
`
`Intra-Metal Dielectric 1 Deposition
`
`177
`
`178
`180
`181
`
`187
`
`190
`
`193
`
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`199
`200
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`202
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`203
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`205
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`Contents
`
`xiii
`
`Via 1 Module
`
`Metallization 2
`
`Additional Metal/Dieletric Layers
`Final Passivation
`
`7.3 Backend ProcesseS ...........ccccc cece eee eeeneenneeee
`
`Wafer Probe
`
`Die Separation
`Packaging
`Final Test and Burn-In
`
`TASUIMONY ‘sa ceascccisiea ter dasa ecardah otbinias deen emai ead ihe
`Chapter8 Electrical Noise: An Overview
`Ba Sines Gscésnic teed cheud cape eadeeres sch och ketenes
`8.1.1 Power and Energy
`Comments
`
`8.1.2 Power Spectral Density
`Spectrum Analyzers
`BOCCHIE: ERE (eas ce coc hunter latech acon a parudatsdalibletds flatbed ok
`
`8.2.1 Calculating and Modeling Circuit Noise
`Input-Referred Noise|
`Noise Equivalent Bandwidth
`Input-Referred Noise in Cascaded Amplifiers
`Calculating Vorciserus from a Spectrum: A Summary
`8.2.2 Thermal Noise
`
`8.2.3 Signal-to-Noise Ratio
`Input-Referred Noise||
`Noise Figure
`An Important Limitation of the Noise Figure
`Optimum Source Resistance
`Simulating Noiseless Resistors
`Noise Temperature
`Averaging White Noise
`8.2.4 Shot Noise
`
`8.2.5 Flicker Noise
`
`8.2.6 Other Noise Sources
`
`Random Telegraph Signal Noise
`Excess Noise (Flicker Noise)
`Avalanche Noise
`
`205
`
`207
`
`208
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`208
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`209
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`209
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`211
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`211
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`211
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`213
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`253
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`KiV
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`Contents
`
`BEF EASCUSSION€
`
`dick ch bck peta ds Sa ea edb ylnteldalile
`
`8.3.1 Correlation
`
`Correlation of Input-Referred Noise Sources
`Complex Input Impedance
`8.3.2 Noise and Feedback
`
`Op-Amp Noise Modeling
`8.3.3 Some Final Notes Concerning Notation
`Chapter 9 Models for Analog Design
`9.1 Long-Channel MOSFETs ......... 0.0.0.0. e000:
`9.1.1 The Square-Law Equations
`PMOS Square-Law Equations
`Qualitative Discussion
`
`Threshold Voltage and Body Effect
`Qualitative Discussion
`
`The Triode Region
`The Cutoff and Subthreshold Regions
`9.1.2 Small Signal Models
`Transconductance
`
`AC Analysis
`Transient Analysis
`Body Effect Transconductance,g,,,
`Output Resistance
`MOSFETTransition Frequency,f,
`General Device Sizes for Analog Design
`Subthreshold g,, and V,,,,
`9.1.3 Temperature Effects
`Threshold Variation and Temperature
`Mobility Variation with Temperature
`Drain Current Change with Temperature
`9.2 Short-Channel MOSFETs
`..................0.
`9.2.1 General Design (A Starting Point)
`Output Resistance
`Forward Transconductance
`
`Transition Frequency
`9.2.2 Specific Design (A Discussion)
`9.3 MOSFET Noise Modeling ..........00.....000-
`Drain Current Noise Model
`
`254
`
`256
`
`256
`
`259
`
`259
`
`262
`
`269
`
`WIT ANTS RIM 269
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`271
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`272
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`272
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`276
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`276
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`291
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`295
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`295
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`sie bescula vested 4 ba 297
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`297
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`298
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`298
`
`299
`
`300
`
`cate Emana sue ae 302
`
`302
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`Contents
`
`311
`Chapter 10 Models for Digital Design
`311
`Miller Capacitance
`AO Te Digits| MOSFET MOMS) oa si) 06 aie ert ehaeoeiewena wetdle's 312
`Effective Switching Resistance
`312
`Short-Channe| MOSFETEffective Switching
`314
`Resistance
`
`10.1.1 Capacitive Effects
`10.1.2 Process Characteristic Time Constant
`
`315
`316
`
`317
`10.1.3 Delay and Transition Times
`320
`10.1.4 General Digital Design
`10.2 The MOSFETPass Gate 2.2.02... 0 cc ccc cece eee nee eens 321
`
`The PMOS Pass Gate
`
`322
`
`323
`10.2.1 Delay through a Pass Gate
`324
`The Transmission Gate (The TG)
`325
`10.2.2 Delay through Series-Connected PGs
`10.3 A Final Comment Concerning Measurements ......0.+.0006: 326
`Chapter 11 The Inverter
`331
`11s RE GHEKECIEHISUIGS:
`c aichanietaetQentsissuadarsaaisaiebeerss 331
`
`333
`Noise Margins
`334
`Inverter Switching Point
`334
`Ideal Inverter VTC and Noise Margins
`11.2 Switching Characteristics ............0-2-0--0eceeeeeeeenenes 337
`The Ring Oscillator
`339
`Dynamic PowerDissipation
`339
`VES LAVOUE Of Hie MVERGR vy. a hie dowel veerinveicbieisressseen 341
`Latch-Up
`341
`11.4 Sizing for Large Capacitive Loads ................2-2...202. 344
`Buffer Topology
`344
`Distributed Drivers
`347
`
`348
`Driving Long Lines
`11.5 Other Inverter Configurations ........ 0.2... .c cece eee e eee ee ee 349
`NMOS-Only Output Drivers
`350
`Inverters with Tri-State Outputs
`351
`Additional Examples
`351
`Chapter 12 Static Logic Gates
`353
`12.1 DC Characteristics of the NAND and NOR Gates ........... 353
`
`12.1.1 DC Characteristics of the NAND Gate
`
`353
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`XVI
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`Contents
`
`12.1.2 DC Characteristics of the NOR Gate
`A Practical Note Concerning V., and Pass Gates
`12.2 Layout of the NAND and NOR Gates ..................
`12.3 Switching CharacteristicS 2.0.00... ccc eee eee ener eee
`Parallel Connection of MOSFETs
`
`Series Connection of MOSFETs
`
`12.3.1 NAND Gate
`
`Quick Estimate of Delays
`12.3.2 Numberof Inputs
`12.4 Complex CMOSLogic Gates ............--..2-020.005:
`Cascode Voltage Switch Logic
`Differential Split-Level Logic
`Tri-State Outputs
`Additional Examples
`Chapter 13 Clocked Circuits
`TS ASTHE CMOS TG) wate tena cpu aanead a adawiew aeaninoas
`
`Series Connection of TGs
`
`13.2 Applications of the Transmission Gate .................
`Path Selector
`
`Static Circuits
`
`13.3 Latches and Flip-Flops ........-...0-2:e0 cee eneeeeceee
`Basic Latches
`
`An Arbiter
`
`Flip-Flops and Flow-through Latches
`An Edge-Triggered D-FF
`Flip-Flop Timing
`TA ESROITIBIS cee aiytud angled Bbaaattn cele as AIG6 25 Rae's ia ane
`Chapter 14 Dynamic Logic Gates
`14.1 Fundamentals of Dynamic Logic ....................0..
`14.1.1 Charge Leakage
`14.1.2 Simulating Dynamic Circuits
`14.1.3 Nonoverlapping Clock Generation
`14.1.4 CMOSTGin Dynamic Circuits
`TA:2) GIOGKEC CMDS. LOGIC: wciisin\nccincls's de deca pee ei acineaxe
`Clocked CMOS Latch
`
`An Important Note
`PE Logic
`
`356
`357
`358
`358
`358
`
`359
`
`360
`
`362
`363
`364
`369
`370
`370
`370
`375
`375
`
`377
`
`378
`378
`
`379
`
`380
`380
`
`383
`
`383
`386
`388
`389
`397
`397
`398
`401
`401
`402
`403
`403
`
`403
`404
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`Contents
`
`XVI
`
`Domino Logic
`NP Logic (Zipper Logic)
`Pipelining
`Chapter 15 VLSI Layout Examples
`15.4 Chip Layout occu c ee nena oe ren cP eae nen eee ae
`Regularity
`Standard Cell Examples
`Power and Ground Considerations
`
`An Adder Example
`A 4-to-1 MUX/DEMUX
`
`15.2 Layout Steps by Dean Moriarty ............0.0025-0200-5--
`Planning and Stick Diagrams
`Device Placement
`
`Polish
`
`Standard Cells Versus Full-Custom Layout
`Chapter 16 Memory Circuits
`TE TMAMAY ATCHHECIINSS 4 5c cisdaisrtiaienasaciedicieiianadaaes
`16.1.1 Sensing Basics
`NMOSSense Amplifier (NSA)
`The Open Array Architecture
`PMOSSense Amplifier (PSA)
`Refresh Operation
`16.1.2 The Folded Array
`Layout of the DRAM Memory Bit (Mbit)
`16.1.3 Chip Organization
`18:2 Peripheral Cait: saci larsic ee ats Karstsvelavrstorcl acme Tels ds Bale dete
`16.2.1 Sense Amplifier Design
`Kickback Noise and Clock Feedthrough
`Memory
`Current Draw
`
`Contention Current (Switching Current)
`Removing Sense Amplifier Memory
`Creating an Imbalance and Reducing Kickback Noise
`Increasing the Input Range
`Simulation Examples
`16.2.2 Row/Column Decoders
`
`Global and Local Decoders
`
`405
`407
`407
`411
`412
`412
`413
`417
`
`419
`422
`
`422
`422
`424
`
`427
`
`427
`433
`434
`435
`435
`436
`440
`44)
`441
`443
`447
`448
`448
`449
`450
`450
`
`450
`451
`451
`454
`454
`457
`
`458
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`XViii
`
`Reducing Decoder Layout Area
`16.2.3 Row Drivers
`
`Contents
`
`460
`461
`
`c tes caeasceaneeneee ster eee We co he ae eaee eas A463
`16.8 Memory Caller
`16.3.1 The SRAM Cell
`463
`
`464
`16.3.2 Read-Only Memory (ROM)
`466
`16.3.3 Floating Gate Memory
`467
`The Threshold Voltage
`468
`Erasable Programmable Read-Only Memory
`468
`Two Important Notes
`469
`Flash Memory
`483
`Chapter 17 Sensing Using AZ Modulation
`LET Qualitative DISGUBSION |. 2)55.5:456- 2 ieee ach adAli@eoeaaieeaces 484
`
`17.1.1 Examples of DSM
`The Counter
`
`Cup Size
`Another Example
`17.1.2 Using DSM for Sensing in Flash Memory
`The Basic Idea
`
`484
`485
`
`486
`486
`487
`487
`
`492
`The Feedback Signal
`496
`Incomplete Settling
`17.2 Sensing Resistive Memory ........-....-...-2200eee eee eeees 497
`The Bit Line Voltage
`497
`Adding an Offset to the Comparator
`498
`Schematic and Design Values
`499
`A Couple of Comments
`502
`17.3 Sensing in CMOS Imagers
`.......---2. cece cece e peer en eenee 504
`Resetting the Pixel
`504
`The Intensity Level
`504
`Sampling the Reference and Intensity Signals
`505
`Noise Issues
`506
`
`508
`Subtracting V,. from V,
`517
`Sensing Circuit Mismatches
`523
`Chapter 18 Special Purpose CMOSCircuits
`(E54! THE SER OTETAQGGE, tb ae dedi aw ck agalatate ty dnlaclaleietls Sl chdals 523
`18.1.1 Design of the Schmitt Trigger
`524
`Switching Characteristics
`526
`18.1.2 Applications of the Schmitt Trigger
`527
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`EX
`
`18.2 Multivibrator Circuits .....0... 0. cc cece eee ee een eee ees
`
`18.2.1 The Monostable Multivibrator
`
`18.2.2 The Astable Multivibrator
`
`TES INPUT BORER Sens iciis tasdacis baci aia bicep eeaaia es
`18.3.1 Basic Circuits
`
`Skewin Logic Gates
`18.3.2 Differential Circuits
`
`Transient Response
`18.3.3 DC Reference
`
`18.3.4 Reducing Buffer Input Resistance
`18.4 Charge Pumps(Voltage Generators)
`............0.00.000.
`Negative Voltages
`Using MOSFETsfor the Capacitors
`18.4.1 Increasing the Output Voltage
`18.4.2 Generating Higher Voltages: The Dickson Charge
`Pump
`Clock Driver with a Pumped Output Voltage
`NMOS Clock Driver
`
`18.4.3 Example
`Chapter 19 Digital Phase-Locked Loops
`19.1 The Phase Detector ............... 0202s eee eee eee eee ees
`
`19.1.1 The XOR Phase Detector
`
`19.1.2 The Phase Frequency Detector
`19.2 The Voltage-Controlled Oscillator .......................--
`19.2.1 The Current-Starved VCO
`
`Linearizing the VCO’s Gain
`19.2.2 Source-Coupled VCOs
`19:3: The Loop Fillet 200) anced ten cece Cem nncdviawen sae tects nae
`19.3.1 XOR DPLL
`
`Active-P! Loop Filter
`19.3.2 PFD DPLL
`
`Tri-State Output
`Implementing the PFD in CMOS
`PFD with a Charge Pump Output
`Practical Implementation of the Charge Pump
`Discussion
`
`529
`
`529
`
`530
`
`531
`§31
`
`533
`534
`
`535
`538
`
`541
`542
`543
`544
`544
`544
`
`546
`546
`
`547
`551
`553
`
`553
`
`557
`561
`561
`
`564
`565
`567
`568
`
`573
`575
`
`575
`576
`578
`579
`581
`
`19:4 System CONCEMS ge0ccsecddeectrdeeceeavaenurdeeneereceens 582
`
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`XX
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`19.4.1 Clock Recovery from NRZ Data
`The Hogge Phase Detector
`Jitter
`
`Contents
`
`584
`
`588
`
`591
`
`PSPS LOE 592
`
`595
`
`596
`
`hetaemed asaa ne 596
`
`596
`
`602
`
`613
`
`iinigigemeiane 613
`
`.............cecc see e eens
`
`19.5 Delay-Locked Loops
`Delay Elements
`Practical VCO and VCDL Design
`19.6 Some Examples
`......c.ccccesiesenaneeen ses
`19.6.1 A 2 GHz DLL
`
`19.6.2 A 1 Gbit/s Clock-Recovery Circuit
`Chapter 20 Current Mirrors
`20.1 The Basic Current Mirror ................-..-
`
`20.1.1 Long-Channel Design
`20,1,2 Matching Currentsin the Mirror
`Threshold Voltage Mismatch
`Transconductance Parameter Mismatch
`
`Drain-to-Source Voltage and Lambda
`Layout Techniques to Improve Matching
`Layout of the Mirror with Different Widths
`20.1.3 Biasing the Current Mirror
`Using a MOSFET-Only ReferenceCircuit
`Supply IndependentBiasing
`20.1.4 Short-Channel Design
`An Important Note
`20.1.5 Temperature Behavior
`Resistor-MOSFET ReferenceCircuit
`
`MOSFET-Only Reference Circuit
`Temperature Behavior of the Beta-Multiplier
`Voltage Reference Using the Beta-Multiplier
`20.1.6 Biasing in the Subthreshold Region
`20.2 Cascoding the Current Mirror .............--.-
`20.2.1 The Simple Cascode
`DC Operation
`Cascode Output Resistance
`20.2.2 Low-Voltage (Wide-Swing) Cascode
`An Important Practical Note
`Layout Concerns
`20.2.3 Wide-Swing, Short-Channel Design
`
`614
`
`616
`
`616
`
`616
`
`617
`
`617
`
`620
`
`621
`
`622
`
`624
`
`627
`
`630
`
`631
`
`631
`
`633
`
`634
`
`634
`
`635
`
`jai vin aadstpikis 636
`
`636
`
`637
`
`637
`
`639
`
`641
`
`642
`
`642
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`Contents
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`XXI
`
`645
`20.2.4 Regulated Drain Current Mirror
`20.3 Biasing Circuits
`................ eee ssedatavoaeireaveduers 647
`20.3.1 Long-Channel Biasing Circuits
`647
`Basic CascodeBiasing
`648
`The Folded-Cascode Structure
`648
`
`20.3.2 Short-Channel Biasing Circuits
`Floating Current Sources
`20.3.3 A Final Comment
`Chapter 21 Amplifiers
`21.1 Gate-Drain Connected Loads
`
`..............2...2-.-5-5- ever
`
`21.1.1 Common-Source (CS) Amplifiers
`Miller's Theorem
`
`Frequency Response
`The Right-Hand Plane Zero
`A Common-Source Current Amplifier
`Common-Source Amplifier with Source Degeneration
`Noise Performance of the CS Amplifier with
`Gate-Drain Load
`
`650
`651
`651
`657
`lGor
`
`657
`660
`
`661
`662
`666
`667
`669
`
`670
`21.1.2 The Source Follower (Common-Drain Amplifier)
`671
`21.1.3 Common Gate Amplifier
`212 Current Seurte Lads... screw aereew ete eve yea Sed TE EPS 671
`
`21.2.1 Common-Source Amplifier
`Class A Operation
`Small-Signal Gain
`OpenCircuit Gain
`High-lmpedance and Low-Impedance Nodes
`Frequency Response
`Pole Splitting
`Pole Splitting Summary
`Canceling the RHP Zero
`Noise Performance of the CS Amplifier with Current
`Source Load
`
`21.2.2 The Cascode Amplifier
`Frequency Response
`Class A Operation
`Noise Performance of the Cascode Amplifier
`Operation as a Transimpedance Amplifier
`
`671
`672
`673
`673
`673
`674
`676
`679
`685
`686
`
`686
`687
`688
`688
`688
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`XXIi
`
`Contents
`
`689
`21.2.3 The Common-Gate Amplifier
`690
`21.2.4 The Source Follower (Common-Drain Amplifier)
`691
`Body Effect and Gain
`692
`Level Shifting
`693
`Input Capacitance
`694
`Noise Performance of the SF Amplifier
`694
`Frequency Behavior
`696
`SF as an Output Buffer
`697
`A Class AB Output Buffer Using SFs
`21.3 The Push-Pull Amplifier
`.........0. 06.0 c ccc cece eee eee e eens 698
`21.3.1 DC Operation and Biasing
`699
`Power Conversion Efficiency
`699
`21.3.2 Small-Signal Analysis
`702
`21.3.3 Distortion
`704
`
`705
`Modeling Distortion with SPICE
`7114
`Chapter 22 Differential Amplifiers
`22.1 The Source-Coupled Pair
`..-......2... 2.20.0 ccc cece eee eens 714
`22.1.1 DC Operation
`711
`Maximum and Minimum Differential Input Voltage
`712
`Maximum and Minimum Common-ModeInput
`713
`Voltage
`Current Mirror Load
`
`715
`
`Biasing from the Current Mirror Load
`Minimum Power Supply Voltage
`22.1.2 AC Operation
`AC Gain with a Current Mirror Load
`
`22.1.3 Common-Mode Rejection Ratio
`Input-Referred Offset from Finite CARR
`22.1.4 Matching Considerations
`Input-Referred Offset with a Current Mirror Load
`22.1.5 Noise Performance
`
`22.1.6 Slew-Rate Limitations
`
`717
`717
`718
`719
`
`721
`723
`724
`725
`726
`
`727
`
`22.2 The Source Cross-Coupled Pair ......cccccceecceernnweweuen 727
`Operation of the Diff-Amp
`728
`Input Signal Range
`729
`22.2.1 Current Source Load
`731
`
`Input Signal Range
`
`732
`
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`XXiil
`
`22.3 Cascode Loads (The Telescopic Diff-Amp) ................. 733
`22.4 Wide-SwingDifferential Amplifiers .................0.0.00005 736
`22.4.1 Current Differential Amplifier
`737
`22.4.2 Constant Transconductance Diff-Amp
`738
`Discussion
`740
`
`Chapter 23 Voltage References
`23.1 MOSFET-Resistor Voltage References .........--..-....
`23.1.1 The Resistor-MOSFETDivider
`
`23.1.2 The MOSFET-Only Voltage Divider
`23.1.3 Self-Biased Voltage References
`Forcing the Same Current through Each Side of the
`Reference
`
`An Alternate Topology
`23.2 Parasitic Diode-Based References
`
`................0.0005
`
`Diode Behavior
`
`The Bandgap Energyof Silicon
`Lower Voltage Reference Design
`23.2.1 Long-Channel BGR Design
`Diode-Referenced Self-Biasing (CTAT)
`Thermal Voltage-Referenced Self-Biasing (PTAT)
`Bandgap Reference Design
`Alternative BGR Topologies
`23.2.2 Short-Channel BGR Design
`The Added Amplifier
`Lower Voltage Operation
`Chapter 24 Operational Amplifiers |
`24.1 The Two-Stage Op-Amp ..........2.:00eseceeeeebeeeeeee
`Low-Frequency, Open Loop Gain, Ago.
`Input Common-Mode Range
`PowerDissipation
`Output Swing and Current Source/Sinking Capability
`Offsets
`
`Compensating the Op-Amp
`Gain and Phase Margins
`Removing the Zero
`Compensation for High-Speed Operation
`Slew-Rate Limitations
`
`745
`746
`746
`
`749
`750
`751
`
`756
`757
`
`758
`
`759
`760
`761
`761
`762
`765
`766
`768
`770
`770
`773
`774
`774
`774
`775
`TLS
`775
`
`776
`781
`782
`783
`787
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`XXIV
`
`Contents
`
`789
`Common-Mode Rejection Ratio (CMRR)
`790
`Power Supply Rejection Ratio (PSRR)
`791
`Increasing the Input Common-Made Voltage Range
`792
`Estimating Bandwidth in Op-AmpsCircuits
`24.2 An Op-Amp with Output Buffer
`.-............00cc sees eee ees 793
`Compensating the Op-Amp
`794
`24.3 The Operational Transconductance Amplifier (OTA) ........ 796
`Unity-Gain Frequency,f,,
`197
`Increasing the OTA Output Resistance
`798
`An Important Note
`799
`OTA with an Output Buffer (An Op-Amp)
`800
`The Folded-Cascode OTA and Op-Amp
`803
`24S Kea THENNENCEMISAU cos. ease cory ir ves vi eyed ewe Sy USRRe EVE 808
`
`809
`Bandwidth of the Added GE Amplifiers
`811
`Compensating the Added GE Amplifiers
`24.5 Some Examples and Discussions
`............-+.e0se00e0ee: 812
`A Voltage Regulator
`812
`Bad Output Stage Design
`817
`Three-Stage Op-Amp Design
`820
`Chapter 25 Dynamic Analog Circuits
`B29
`25.4 The MOSFET Sweet n<i5 sc ccgdeidctcer thin arts ciatioee ia 829
`
`ChargeInjection
`Capacitive Feedthrough
`Reduction of ChargeInjection and Clock Feedthrough
`kT/C Noise
`
`830
`831
`832
`833
`
`834
`25.1.1 Sample-and-Hold Circuits
`25.2 Fully-Differential Circuits 00.0.0... 00.0 cece eee eee eee ees 836
`Gain
`836
`
`Common-Mode Feedback
`
`Coupled Noise Rejection
`Other Benefits of Fully-Differential Op-Amps
`25.2.1 A Fully-Differential Sample-and-Hold
`Connecting the Inputs to the Bottom (Poly1) Plate
`Bottom Plate Sampling
`SPICE Simulation
`
`837
`
`838
`838
`838
`840
`B41
`841
`
`25.3 Switched-Capacitor Circuits 2.00.0... cece cece ees 843
`25.3.1 Switched-Capacitor Integrator
`845
`
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`Contents
`
`Parasitic Insensitive
`
`XKV
`
`846
`
`Other Integrator Configurations
`Exact Frequency Responseof a Switched-Capacitor
`Integrator
`851
`Capacitor Layout
`852
`Op-AmpSettling Time
`DO COWCRNTSS
`Lc Chesca Si heed e Sache ieee eb eooadetatavendese 853
`
`846
`849
`
`853
`Reducing Offset Voltage of an Op-Amp
`854
`Dynamic Comparator
`856
`Dynamic Current Mirrors
`858
`Dynamic Amplifiers
`863
`Chapter 26 Operational Amplifiers II
`26.1 Biasing for Power and Speed ....... cc cr eee e reer eee pueeene 863
`26.1.1 Device Characteristics
`864
`
`26.1.2 Biasing Circuit
`Layout of Differential Op-Amps
`Self-Biased Reference
`
`865
`865
`866
`
`26:2 BAsic GONnGeAts: kta i inlaw en andraan canis hensanianayas