Chapter 19 Digital Phase-Locked Loops
`
`571
`
`
`
` ‘
`
`: 4i‘i4i!i'4i
`
`Vinveo
`
`Rlow
`(30k)
`
`M2
`
`
`
`[ v
`
`w
`First stage of VCO
`
`Figure 19.25 Limiting the current in a current-starved VCO,
`
`to calculate the pull-in range since it is greater than the lock-in range, Again, the
`design of the oscillator is important in this DPLL. Thelock time, T, , of the DPLL
`is 40 ns. SPICE simulation results of this DPLL are seen in Fig. 19.27. The top
`waveform is the input control voltage of the VCO. The time thatit takes the loop
`to pull-in the frequency and lock, from this figure,
`is roughly 250 ns. The lock
`time would be the time it takes the loop if the input frequency jumped after the
`loop was locked. Note how, in the bottom traces, the output clock rising edgeis
`centered on the data. Notice that the VCO’s control voltage varies by 200 mV.
`From Fig, 19.26, we can see a 5 MHz variation, Afyco, in the VCO’s output
`frequency. To estimate the jitter, Atjmer, in the output, we can use
`l
`l
`i
`po
`et ee ed) esft
`
`
`Atjiner =F + Afvco 105 MHz~°° 9.43}100 MHz
`
`Tose, MHz
`
`Kyco = 157 x 108 radians/V +s
`
`
`
`0.3 04 05 06 0.7 Vien
`
`Figure 19.26 Gain ofthe VCOin Fig, 19,16 after linearizing and limiting with Fig. 19.25,
`
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`572
`
`CMOSCircuit Design, Layout, and Simulation
`
`av
`
`— vines
`
`
`
`
`
`
`
`Figure 19.27 Simulating the DPLL in Ex. 19.2.
`
`In this simulation (Fig. 19.27), we used the ideal input data, that is, a string of
`alternating ones and zeroes. Figure 19.28 shows what happens when the data is a
`one followed by seven zeroes. The rising edge of the clock is occurring a little
`offset from the center of the data. This error is sometimes called a static phase
`error. As mentioned earlier, when the input data is not changing, the VCO control
`voltage starts to wander back towards VDD/2.
`
`Finally, it's very important to realize that if we were to increase the RC time
`constantofthe filter, as seen above, the damping factor, ¢ , would decrease and
`the loop would never lock. This is counter-intuitive and the reason we should
`always use the design equations when designing DPLLs, &
`
`
`
`Figure 19.28 Showing how the DPLL doesn't lock up to the center of the data
`when the data isn't alternating ones and zeroes.
`
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`Chapter 19 Digital Phase-Locked Loops
`
`573
`
`Adding a zero to the simple passive RC loopfilter, Fig. 19.29 (called a passive lag
`loop filter), the loop-filter pole can be made small (and thus the gain of the VCO can be
`made larger) while at the same time a reasonable damping factor can be achieved. The
`resulf is an increase in the lock range of a DPLL using the XOR PD and a shorter lock
`time see Eqs. (19.37) — (19.40). The passive lag loopfilter is, in most situations preferred
`over the simple RC. Again, as Ex. 19.2 showed, if the center frequency of the VCO
`doesn’t match the input frequency, the clock will not align at 7/2 (in the center of the
`data).
`
`
`Vinveao ____1 +j@R2C
`Vedow
`{
`Vinveo
`Kr= Vpbon V+j0(Ri +RaC
`
`Ry
`
`Lb :
`
`On = aeeae Aa, = 10a,
`On
`N
`G= 5 (aic+ oe]
`
`Figure 19.29 Passive lag loopfilter used te increase DPLL lock range.
`
`Active-PI Loop Filter
`
`The clock misalignment encountered in a DPLL using an XOR PD andpassiveloopfilter
`can be minimized by using the active proportional + integral (active-PI) loop filter shown
`in Fig. 19.30. The integrator allows the V,,,., voltage to move, and stay, away from
`VDD/2, This then eliminates the static phase error (the clock will align to the middle of
`the data). The transfer function ofthis filter is given by
`
`(19,42)
`
`l
`
`L+sRiC
`Ra
`Kr= Ric” R,
`od
`proportional
`
`+ Ric
`——
`integral
`
`The natural frequency of the resulting second-order system is given by
`
`KpeoK veo
`=I NRIC
`B83)
`= 19.43
`
`On
`
`Vppow
`
`eles
`
`Vppow Bein
`
`4
`
`
`
`VDD/2 (*)
`
`vw
`
`VDD
`
`Vinveo
`
`Figure 19.30 Active-Pl loopfilter.
`
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`574
`
`CMOSCircuit Design, Layout, and Simulation
`
`and the dampingratio is given by
`
`The lock rangeis
`
`(o>
`
`Aw, = 4nto,
`
`(19.44)
`
`(19.45)
`
`while the lock time remains 2n/@,. The pull-in range, using the active-PI loopfilter, is
`limited by the VCO oscillator frequency. Consider the following example.
`
`Example 19,3
`Repeat Ex. 19.2 using the active-P] loop filter. The SPICE model for an op-amp(a
`voltage-controlled voltage source) seen in Fig. 20.19 can be used for the op-amp.
`
`Using Eq. (19.43) in (19.44) gives
`
`c= R2€
`2
`
`[KeoKveo
`NR\C
`
`If we set the dampingfactor again to 1 we can write
`_ 187x 10°R3C
`7
`2nR |
`
`4
`
`Setting C to 10 pF and R, to 25k, then R, is 39k. The simulation results are seen in
`Fig, 19.31. The output clock is aligned to the center of the data. It’s important to
`make sure that the step size used in the SPICE transient simulation isn’t too big.
`For example, if a 100 MHz clock is used with a step size of 1 ns,it is likely that
`the loop either won’t lock or if it does lock, both the VCO control voltage and
`thus the output data will oscillate. A maximum step size for 100 MHz signals may
`be 100 ps. Also note the sparse data pattern will increase the lock time (thus the
`reason for the long simulation time in Fig. 19.31).
`
`Finally, it is important to rememberthat the VCO tuning schemein Fig. 19.25
`is not practical unless the components can be set manually (either off-chip or
`using fuses or switches on chip). Also, something very important that we are not
`discussing (yet)
`is power supply noise. The current-starved VCO's output
`frequency is not very stable with changes in VDD, @
`
`¥ — daetael 25
`
`— tick
`
`
`
`aw iH 7 “ 2 z bao aea pa.
`time
`ua
`
`é 4 my 248 80
`
`Figure 19.31 How the loop locks up on the center of the data.
`
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`

`Chapter 19 Digital Phase-Locked Loops
`
`575
`
`19.3.2 PFD DPLL
`
`Tri-State Output
`
`A block diagram of a DPLL using the PFD with tri-state output 1s shown in Fig. 19.32.
`The phasetransfer function is the same as Eq. (19.30)
`
`H(s) _ Pclock — KepmKeKVCO2 19,
`bdaa
`8+B*KppriK«Kyco
`eo
`
`where
`
`Kr
`
`1+sR2C
`=
`~ 14+s(R) +R2)C
`
`(19.47)
`
`Whenthis filter is driven with the tri-state output, no current flows in R, or R, with the
`output in the high impedance state. The voltage across the capacitor remains unchanged.
`We can think ofthe filter, tri-state output as an ideal integrator with a transfer function
`) _1+sR2C
`
`Substituting this equation into Eq. 19.46 and rearrangingresults in
`
`Kr= TR+Ra)C+Ra)C (19.48)
`
`Detock
`Setock
`
`
`
`
`oo 52 KepriKveoR2|KeonKvco Ddara ~ dare (19.49)
`
`MRj+R2)C
`
`MRy+R2)C
`
`From this equation, the natural frequency is
`
`_|KepwiKyco
`
`i, = eeeite
`
`(19.50)
`
`and the dampingfactor is determined by solving
`
`KepriK ycoRiC
`
`GOn=N(R+ R2)C ade
`2C0, = —————
`19.5
`
`VDD
`Kepiri
`
`
`Kr
`data
`Up
`P,FD
`1 Vinrco
`
`clack out
`Su
`
`
`data in
`
`data“a
`
`dclock Dawn
`
`Delock
`
`
`
`
`
`Divider
`
`
`B=1/N
`Pdelock = 7Delock
`
`Figure 19.32 Block diagram of a DPLL using a sequential phase detector (PFD).
`
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`576
`
`CMOSCircuit Design, Layout, and Simulation
`
`which results in a damping factor given by
`G= FRC
`
`The lock range is given by
`
`Ao, = 4nCo,
`
`(19.52)
`
`(19,53)
`
`while the lock time, 7, , remains 27/,. The pull-in range is limited by the VCO operating
`frequency. The pull-in time is given by
`
`Tp=2R,C- In
`
`(KycolN) -(VDD/2)
`(Kyco/N\(VDD/2) - Aw
`
`(19.54)
`
`where Aq is the magnitude of the inpur frequencystep,
`
`Implementing the PFD in CMOS
`
`The PFD seen in Fig, 19.10 can be implemented using inverters and nand gates as seen in
`Fig. 19.33, Simulating this circuit gives the results seen in Fig, 19.34. When the delockis
`lagging, the data the output of the PFDis the up pulse (indicating that the edge of dclock
`needs to speed up or occur earlier in time, that is, the VCO’s control voltage should
`increase). When dara is lagging dclock the down pulse goes high indicating dclock should
`slow down.
`
`We have somefine points that need to be discussed here. For example, what
`happens to up and down as the rising edges of dclock and data move close together?
`What we may get is some small glitches in the up and down signals. Or we may see both
`up and down staying low as the two pulses move closer together. In the PFD of Fig.
`19.33, the delay through the two inverters can be used to set how up and down behave as
`
`
`
`delock
`
`Figure 19.33 CMOSimplementation of a PFD.
`
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`

`Chapter 19 Digital Phase-Locked Loops
`
`577
`
` i —iist down
`vfALsopmomenvet5esraeaeaewpeet ie
`
`
`
`
`
`
`
`|
`
`Le BE |=D dclock
`
`Figure 19.34 Simulation results for the PFD in Fig. 19.33.
`
`the PFD’s inputs move close together. If, for example, both stay low when the PFD’s
`inputs get within 100 ps of each other, we get a static phase error. The loop won't lock
`any tighter than within 100 psofits ideal position. Another way of looking at this is that
`as the phase difference, Ad, moves towards zero (see Fig. 19.11), the gain (the slope of
`the curve in Fig. 19.11) decreases. The phase detector is then said to have a dead zone
`where the gain of the phase detector (the slope of the curves) decreases.
`
`Example 19.4
`Design a DPLL using the tri-state topology seen in Fig. 19.32 that generates a
`clock signal at a frequency of 100 MHz from a 50 MHz square wave input. This
`application of the DPLLis calledfrequency synthesis.
`
`The feedback path contains a divide by 2 circuit (N = 2). Let’s use the VCO with
`the characteristics seen in Fig. 19.18
`
`Kyco = 1.57 x 10° radians/V +s
`
`The gain of the phase detector (knowing VDD is | Y) is
`l
`Kepri = z
`
`The lock range, Af, will be set to 20 MHz. Againlet's set ¢ = 1. Using Eq.(19.53)
`
`Aw, = 4nGo, > ©, = 10x 10° radians/V +s
`
`Using Eq. (19.52) gives
`
`R3C = 200 vs
`
`Let's set the capacitor to 10 pF and R, to 20k. Solving Eq. (19.50) for R, gives
`42.5k (= R)).
`
`The simulation results are seen in Fig. 19.35. We should first notice that the
`VCO’s control voltage doesn’t have the excessive ripple like we had in the DPLL
`using the XOR gate phase detector. The response of the loop shows a nice ¢ = 1
`shape. Again note that a DPLL loop’s pull-in range is limited by the VCO’s
`operating frequency (which, in this example uses the VCO from Fig. 19.18, which
`ranges from 50 to 150 MHz). A good exercise to perform at this pointis to change
`the divider in the feedback path (to divide by |, 2, 4, etc.) and the input frequency
`(a signal we’ve called data) and look at the robustness of the loop. @
`
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`578
`
`CMOSCircuit Design, Layout, and Simulation
`
`Vinveo
`
`¥ —— delock+! 25
`
`—— clock+2 5
`— data
`
`clock out
` : data
`
`1450
`
`=
`1.600
`
`ool
`1 450
`
`2460
`
`1470
`time
`
`1460
`aS
`
`Figure 19.35 Simulation results for Ex. 19.4.
`
`PFD with a Charge Pump Output
`
`The PFD with a charge-pumpoutput is seen in Fig. 19.36. A CMOS implementation of a
`DPLL using this configuration is, in general, preferred over the tri-state output because of
`the better immunity to power supply variations. In the tristate configuration seen in Fig.
`19.32 note that when either the NMOS or PMOSswitches are on, either /DD or ground
`are connected directly to the loop filter. Power supply or ground noise can thus feed
`directly into the loop filter and then into the VCO’s control voltage.
`
`The loop filter integrates the charge supplied by the charge pump. The capacitor
`C, prevents /,,,,,,,R from causing voltage jumps on the input of the VCO and thus
`frequency jumps in the DPLL output. In general, C, is set at about one-tenth (or less) of
`C,. The loop-filter transfer function neglecting C, is given by
`= 1+sRC;Kr=
`
`(19.55)
`
`The feedbackloop transfer function is given by
`H(s) Sy Pclack =
`KpprKvco(\ +sRC\)
`ddate
`gt + sf aaa \+ sa
`From the transfer function the natural frequency is given by
`3 xpoiyco
`O, = NC,
`
`KepK
`
`ca:
`
`Rep
`
`Kk
`
`and the dampingfactoris
`
`C= SPR
`
`(19.56)
`
`(19.57)
`
`(19.58)
`
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`Chapter 19 Digital Phase-Locked Loops
`
`579
`
`The lock range and lock time remain the same (using the different values for the natural
`frequency and damping ratio) as the PFD with the tri-state output. Again, the pull-in
`range is set by the VCOoscillator frequency range. The pull-in time is given by
`
`Tr =2RCiIn}
`
`(KvcolN) :({pump)
`(KvcolN)- pump) = B®
`
`|
`
`ao)
`
`VDD
`
`data Vinveo
`daectock Cz
`
`From divider (counter)
`
`!Pump
`
`C\ L |
`
`Figure 19,36 PFD using the charge pump.
`
`Practical Implementationofthe Charge Pump
`
`Thecircuit seen in Fig. 19.36 is useful for illustrating the concept of the PFD with charge
`pump. However, in a practical circuit the fact that the sources of M1 and M2 charge to
`ground and VDD respectively when M1 and M2 are off creates some design issues. For
`example, suppose that the source of M1 is discharged to ground when the down signal
`goes high. When M1 turnson,it doesn’t supply the charge set by /,,,,,, to the loop filter
`but rather, until the voltage across the current sink increases, behaves like a switch simply
`connecting the filter’s input to ground (meaning that we are not controlling the signal that
`is applied to the loop filter). To get around this problem, consider the circuit seen in Fig.
`19.37. The bias voltages come from diode-connected MOSFETs(to form current mirrors,
`see Ch. 20). When up and down are low, M1L and M2L are on, The pump-up current
`source, MPup,
`is driving the pump-down current source, MNdwn, When either up or
`down goes high, the output is connected to one of the current sources. The MOSFETs
`MIL,R and M2L,R simply steer the current to the loopfilter. The only other concern we
`have with this topology is the fact that when M1L and M2Lare both on, the voltage on
`their drains won't precisely match the voltage across the loop filter (V,,,..). In other
`words, the voltage across each of the current sources (MPup and MNdwn) won’t be the
`same as it is when they are connected to the output node. Theresult is that charge sharing
`between the parasitic capacitance on the drains of MPup and MNdwnandthe capacitance
`used in the loop filter cause a static phase error or jitter. To eliminate this problem, an
`amplifier (see dashed lines in the figure) can be inserted to set the drain voltage of MIL
`and M2Lto the same value V,,,...
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`580
`
`CMOSCircuit Design, Layout, and Simulation
`
`VDD
`
`Vinveo
`
`
`
`
`From divider (counter)
`
`Figure 19.37 Practical implementation of the charge pump.
`
`
`
`Example 19,5
`Repeat Ex. 19.4 using the PFD and charge pumpseen in Fig. 19.37.
`
`One of the other benefits of using the charge pumpis the fact that we can select
`Lump » that is,
`
`Kepr =
`
`
`Lump
`2n
`
`Again, let’s set the lock range to 20 MHz. Using Eq. (19.53) with ¢ = | gives,
`again, @, = 10x 10° radians/V +s. From Eq. (19.58) we get
`
`RC, =200 ns so let’s use R = 20k, C, = 10 pF, and C, = | pF
`
`remembering that we generally set C, to one-tenth of C,. Using Eq. (19.57), we
`can now findthe value of/,,,,
`
`- 1,57 x 10°
`[Z
`Bi|ee =
`10x 10° = on-2- 10x10" — Tpump =8 pA
`
`Because this value isn’t that critical, we'll round it up to 10 yA. Figure 19.38
`showsthe simulation results. Notice the € = 1 (or maybealittle less because the
`voltage does overshootits final value byalittle bit) shape of the VCO’s control
`voltage. Let’s modify the loop filter to show what V,,,.. would look like if ¢ =
`0.1. All we have to do, from Eq. (19.58), is drop R by a factor of 10. The result is
`seen in Fig. 19.39. The control voltageis oscillating and the loop isn’t locking. Of
`course, we can also increase the damping factor. The loop now behavessluggishly
`and does not respond to fast changes in the input signal. For general design, where
`the process and temperature vary,
`it’s better to center the design on a larger
`damping factor to avoid instability. @
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`

`Chapter 19 Digital Phase-Locked Loops
`
`581
`
`Vinvco
`
`al
`
`— vinveo
`
`
`
`
`
`
`A clock out
`
`a: dclock
`1 500
`
`
`
`dala
`
`Figure 19.38 Simulation results for Ex. 19.5.
`
`Discussion
`
`Whenselecting values for the loop filter, we assumed that the output resistance of the
`phase detector was small (for the XOR and tri-state PD) compared to the impedances
`used in the loop filter. We also assumed that the input resistance of the VCO was infinite
`and the input capacitance of the VCO was small compared to the capacitance used in the
`loop filter. Considering the parasitics present in the DPLL is an important part of the
`design.
`
`The center frequency of the VCOis critical for good DPLL performance when
`using the XORgate with RC loop filter. If the center frequency,/.,,... of the VCO (ie.,
`V.vco ~ VDD/2) does not match twice the input data rate, the DPLL will lock up at a
`phase different from 7/2 (the input frequencies to any phase detector must be equal). The
`need for a precision center frequency is eliminated by using the XOR PD with an active-
`PI loop filter or by using the PFD. The other big benefit of using the PFD is that the
`VCO’s gain can belarger.
`
` aE
`
`i
`u,9
`
`t
`Lo
`us
`
`t
`La
`
`fs
`Lea
`
`i
`16
`
`o6
`
`i
`a2
`
`A
`o4
`
`ob
`tise
`
`Figure 19.39 Showing what happens when the dampingfactor 1s reducedto 0.1.
`
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`582
`
`CMOSCircuit Design, Layout, and Simulation
`
`Finally, selecting of the loop’s damping factor, ¢ , is very important. If the value
`is too small, the loop will have trouble locking or the output will jitter excessively
`of €
`when the loop is locked. This last problem is sometimes (gratuitously) called jitter
`peaking since a step in the DPLL’s input frequency causes excessive overshootin V,,.,
`with small C.
`
`19.4 System Considerations
`
`System concems are often the driving force behind the design of a DPLL. Referring to
`Fig. 19.1, we observe that the data transmitted through the channel should ideally arnve
`at the receiver with the same shape with which it was transmitted. In reality, the data
`becomes distorted. Distortion arises from nonlinearities in the receiver input amplifier
`and the finite bandwidth of the channel. To understand the conditions for distortionless
`transmission, consider the block diagram shown in Fig. 19.40. The system has a transfer
`function in the frequency domain of H(/) and in the time domain A(t). For distortionless
`transmission, we can relate the input and output of the system by
`
`WI) = K x(t ty)
`
`(19.60)
`
`where/, is the time delay through the system and K is a constant. This equation shows
`that for distortionless transmission through a system the output
`is simply a scaled,
`time-delayed version of the input, An interesting observation can be made by taking the
`Fourier Transform of both sides of this equation,
`
`¥(fy=K -X Pe?
`
`(19.61)
`
`The transfer function of a distortionless system can then be written as
`|
`Yf)
`= EMMY = Fes
`(19.62)
`Hf) Xf) Ke
`Figure 19,41 shows the magnitude and phase responses of a distortionless system. A
`system is distortionless when its amplitude response, lH()I. is a constant, K, and its
`phase response, 2H(/), is linear with a slope of —27r, overall frequencies ofinterest,
`
`
`x)
`Hf)
`h(i)
`x(t)
`
`
`
`Y(f)
`HM)
`
`Output
`
`Input
`
`System
`
`Figure 19.40 Representation of a system with input and output.
`
`The responses shownin Fig. 19.41 are ideal. In practice, the magnitude response
`of a system may look similar to Fig. 19.42a. At higher frequencies, the magnituderolls
`off. To compensate forthis roll-off, or other imperfections, a circuit called an equalizer is
`added in series with the system (Fig. 19.42b), The equalizer has a transfer function in
`which its magnitude response increases with increasing frequency beyond a point (Fig.
`19.42c). If the low-frequency gain of the equalizer is A/K and the low-frequency gain of
`the system is K, then the resulting gain of the system/equalizer combinationis A.
`
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`Chapter 19 Digital Phase-Locked Loops
`
`583
`
`lH())|
`
`Figure 19.41 Magnitude and phase responseof a distortionless system.
`
`Another source of potential distortion occurs when the receiver input data is
`regenerated into digital levels. This was discussed back in Sec. 18.3. Timing errors occur
`when the input data is not precisely sliced through its middle (see Fig. 18.12). What
`makesslicing the data correctly even more difficult is the fact that the amplitude response
`of the channel can change with time and the data pattern can affect the average level of
`the data. There are two solutions to this problem. Thefirst uses a circuit (see Fig. 18.29)
`that determines the peak positive and negative input analog amplitudes, averages the
`values, and feeds back the result to the comparator in the decision-making circuit. The
`second method encodes the digital data so that the duty cycle of the resulting encoded
`data is 50%. The encoding increases the channel bandwidth for a constantdata rate.
`
`lH(/)|
`
`K
`
`0
`
`(a)
`
`f
`
`
`
`H(f)
`System
`
`Input
`
`E(/)
`Equalizer
`
`Output
`
`(b)
`
`AH(NI1)
`
`
`
`IE(A)|WO"
`
`Hil
`
`
`(c)
`
`Figure 19.42 Using an equalizer to lowerdistortion in a system.
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`CMOSCircuit Design, Layout, and Simulation
`
`Encoding the data can eliminate the need for a decision circuit. If the resulting
`encoded data has a 50% duty cycle, it can be passed through a capacitor in the receiver,
`resulting in an analog signal centered around ground. The noninverting input of the
`comparator will then be connected to ground, The comparator will then be ableto slice
`the data at the correct moments in time (in the middle ofthe data bit). An example of an
`encoding scheme is shown in Fig. 19.43. Encoding occurs in the transmitter prior to
`transmission over the channel. This particular encoding scheme is referred to as the
`bi-phase format, or more precisely, the bi-phase-level (sometimes called bi-phase-L or
`Manchester NRZ) format. The cost of using this scheme over the NRZ data format is
`increased channel bandwidth. Other encoding schemes are shownin Fig. 19.44.
`
`dat
`aed
`clock
`
`Bi-phase encoded data out
`
`data
`
`clock Bi-phase
`
`
`Figure 19.43 Bi-phase data encoding,
`
`19.4.1 Clock Recovery from NRZ Data
`
`One of the most important steps in the design of a communication system is the selection
`of the transmission format, that is, NRZ, bi-phase, or some other format, together with
`use of parity, cyclic redundancy code, or some other encoding format. In this section we
`discuss some of the considerations that go into the design of a clock-recovery DPLL in a
`system that uses NRZ,
`
`Let’s begin this discussion by considering the NRZ data and clock shown in Fig.
`19.45. Let's further assume that these signals are the inputs to an XOR PD in a DPLL,
`which is not in lock since the clock is not aligned properly to the data. The resulting
`output of the XOR PD is shownin this figure as well. If we were to average this output
`using a loop filter, we would get VDD/2.In fact, it is easy to show that shifting the clock
`signal
`in time has no effect on the average output of the PD. Why? To answer this
`question, let’s use some numbers. Assumethat a bit width of data is 10 ns (which is also
`the period of the clock). The frequency of the square waveresulting from the alternating
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`Chapter 19 Digital Phase-Locked Loops
`
`385
`
`NRZ-level
`
`NR2Z-mark
`
`NRZ-space
`
`Return to zero
`
`Bi-phase-level
`
`Bi-phase-mark
`
`
`
`
`mark time
`
`
`
`
`
`| =high
`0=low
`
`| = transition at beginning of bit
`0 = no transition
`
`0 = transition at beginning of bit
`| =notransition
`
`| = highfirst half ofbit interval
`0 = low entire bit interval
`
`| =highfirst half ofbit interval
`0 = lowfirst half of bit interval
`
`| = transition at beginning and
`middle ofbit interval
`0 = transition at beginning ofbit
`interval only
`(Bi-phase-space inverted from this)
`
`Delay-
`modulation-
`
`1 = transition in the center of
`bit interval
`» 0 afier | = no transition
`O after 0 = transition at
`beginningofbit interval
`(Delay-modulation-space
`inverted from this)
`
`Figure 19.44 Data transmission formats.
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`CMOSCircuit Design, Layout, and Simulation
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`dala
`
`clock
`
`time Average of XOR output is VDD/2
`
`
`20 ns
`
`even thoughthe loop is not locked.
`
`Figure 19.45 The problemsof using clock without the divide by 2 to lock on data.
`
`strings of ones and zeros is 50 MHz. We knowthatif we take the Fourier Transform of a
`square-wave, only the odd harmonics (i.e., 50, 150, and 250 MHz)are present. Since the
`clock signal is at 100 MHz,there is no energy or information common between the clock
`and data signals. To remedy this, we divide the clock down in frequency, dclock, so that
`it is at the same frequency as the alternating ones and zeros ofthe data (divide by two).
`
`The next problem we encounter, if we use the divide by two in the feedback loop,
`occurs when we get dara that is a repeating string of 2 ones followed by 2 zeroes, Fig.
`19.46 (the delock is not locked to the data), Again, there is no common information
`between the two inputs, and the resulting XOR PD output will always have an average of
`VDD/2. In this case, however, the de/ock is running at 50 MHz, and the data is a
`square-wave of 25 MHz. Should wedivide the c/ock down furtherto avoid this situation?
`The answer is no. However many times we divide the clock down, wecanstill come up
`
`data
`
`delack
`
`oul
`
`XOR PD
`
`Figure 19.46 Problemstrying to lock on a data stream that is one-half the dclock frequency.
`
`Average of XOR output is VDD/2
`even though the loopis not locked.
`
`time
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`Chapter 19 Digital Phase-Locked Loops
`
`587
`
`with a data string that will not allow the loop to lock, Also, it is the actual edge transitions
`(the frequency of the data and dclock) that
`is used when the inputs are not pure
`squarewaves. Increasing the width of dc/ock has the effect of removing information and
`making it more difficult to lock up to the data, One solution to this problem is to use
`odd-parity with an 8-bit word (9 bits total) and eliminate, at the transmitting end, the
`possibility of all 8 bits being high, that is, 11111111 or 255. It is then impossible to
`generate a square-wave.
`
`The restrictions on the data pattern in a communications system using NRZ data
`can be reduced by detecting the edges of the input data with an edge detector circuit (Fig.
`19.47). The delay through the inverters sets the width of the output pulses, labeled “Edge
`out” in this circuit. The frequency content of the output pulses will always contain energy
`at the clock frequency and thus the loop can lock up on the data.
`
`NRZin)>tout
`NRZ in
`
`
`
`
`Edge out
`
`
`
`\
`
`Inverter delay
`
`Figure 19.47 Detecting the edges in NRZ data.
`
`As an example, consider the block diagram and data shown in Fig. 19.48, The
`Edge output is connected as the input of an KOR-based DPLL. The output of the VCO,
`clock, will lock up on the center of the Edge output, that is, the rising edge of the clock
`signal will become aligned with the center of Edge out. Averaging PD out, in this figure,
`results in VDD/2. If the clock is shifted to the left or right in time, the average value of
`PD out will shift down or up, causing the VCO frequency to change and keep the clock
`aligned to the center of Edge out. Several practical problems exist with this configuration.
`The delay through the inverters should be constant whether a high-to-low or a
`low-to-high transition is propagating through the inverters. Also, for best performance the
`delay of the inverters, or whatever elementis used for the delay (one common elementfor
`high-speed applications is a microstrip line) should be close to one-half of the bit-interval
`time. This delay is important as it directly affects the gain of the phase detector and
`therefore the transient properties of the DPLL.
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`CMOSCircuit Design, Layout, and Simulation
`
`Edge detector
`
`PD out
`
`Loop
`Filter
`
`
`
`lock
`
`
`
`
`
`
`
`NRZ in
`
`Edge out
`
`clack
`
`PD out
`
`Figure 19.48. Clock-recovery circuit for NRZ using an edge detector.
`Note that the DPLL is in lock, when the rising edge of clock
`is centered on the edge output pulse.
`
`time
`
`Not having the c/ock aligned to the center of the data bit can cause problems in
`high-speed, clock-recovery circuits. Simply adding a delay in series with the clock signal
`does not solve this problem since the temperature dependence and process variations of
`the associated circuit do not guarantee proper alignment. What is neededis a circuit that
`is self-correcting, causing the clock signal
`to align to the center of the data bit
`independent ofthe data-rate, the temperature, or process variations.
`
`The Hogge Phase Detector
`
`The PD portion ofa self-correcting, clock-recovery circuit is shown in Fig. 19.49 along
`with associated waveformsfor a locked DPLL. Nodes A and B are simply the input NRZ
`data shifted in time by one-half bit-interval and onebit-interval, respectively. The outputs
`of the phase detector are labeled Jncrease and Decrease. If Increase is low more often
`than Decrease, the average voltage out of the loop filter and thus the frequency out of the
`VCO will decrease. A loop filter that can be used in a self-correcting DPLL is shown in
`Fig. 19.50a. This filter is the active-PI loopfilter discussed in Sec. 19.3.1, with an added
`input
`to accommodate both outputs of the PD. Figure 19.50b shows the resulting
`waveforms in a DPLL where the clock is leading the center of the NRZ data, and thus
`Increase is high less often than Decrease. If the NRZ data was lagging the center of the
`data bit, Decrease would be high less often than Jncrease, resulting in an increase in the
`loop-filter output voltage. Note that in this discussion we have neglected the propagation
`delays present in the circuit. For a high-speed, self-correcting PD design, we would have
`to analyze each delay in the PD to determinetheir effect on the performance of the DPLL.
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`Chapter 19 Digital Phase-Locked Loops
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`589
`
`D
`
`Q
`
`clock
`(from VCO)
`
`NRZ in
`
`
`
`
`D
`
`Q
`
`
`
`NRZ @A
`
`A@B
`
`time
`
`
`
`
`
`
`
`NRZ in
`
`clock
`
`Node A
`
`elock
`
`Node B
`
`Increase
`
`Decrease
`
`
`
`Figure 19.49 The PD (Hogge) portion of a self-correcting, clock-recovery circuit in lock.
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`590
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`CMOSCircuit Design, Layout, and Simulation
`
` Increase
`
`Decrease
`
`Vinveo
`
`
`
`
`time
`
`NRZ in
`
`clack
`
`Node A
`
`clack
`
`Node B
`
`Ineréase
`
`Decrease
`
`(b)
`
`Figure 19.50 (a) Possible loop filter used in a self-correcting (Hogge) DPLL and
`(b) waveforms when the loop is not in lock and the clock leads the
`center of the data.
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`Chapter 19 Digital Phase-Locked Loops
`
`59]
`
`Jitter
`
`Jitter, in the most general sense, for clock-recovery and synchronization circuits, can be
`defined as the amount of time the regenerated clock varies once the loop is locked. Figure
`19.51a shows the idealized case when the clock doesn’t jitter, while Fig. 19.51b shows
`the actual situation where the clock-rising edge moves in time (jitters), In these figures,
`the oscilloscope is triggered by the rising edge of the dara. In the following discussion,
`we neglect power supply and oscillator noise,
`that
`is, we assume that the oscillator
`frequency is an exact numberthat is directly related to the VCO input voltage. In the
`section following this one, we cover delay-locked loops and further discuss the
`limitations of the VCO,
`
`Scope triggered here
`
`clock
`
`Jitter
`
`Figure 19.51 (a) Idealized view of clock and data withoutjitter and (b) with jitter,
`
`Consider using the charge pump with the self-correcting PD shownin Fig. 19.52.
`Whenthe loop is locked (from Fig. 19.49), both increase and decrease occur (with the
`same width) for every transition in the incoming data. Note that unlike a PFD/charge
`pump combination where the output of the charge pump remains unchanged when the
`loop is locked,
`the self-correcting PD/charge-pump combination generates a voltage
`ripple on the input of the VCO (similar to the XOR PD with RC or Active PIfilter)’.
`Let's assume that this ripple is 10 mV and use the values for VCO gain and frequencies
`given in Ex. 19.5 to illustrate the resulting jitter introduced into the output clock. The
`change
`in output
`frequency resulting from this
`ripple
`is
`I[O0mV-(1.57 x
`10°
`radians/V-s)-(1/21) or 2.5 MHz. This meansthat the output of the DPLL will vary from,
`say, 100 MHz to 102.5 MHz.In termsofa jitter specification (see Eq. (19.41)), the clock
`jitter is (roughly) 250 ps (2.5% of the output clock’s period).
`
`From this example, data dependentjitter, can be reduced by
`
`1.
`
`Reducing the gain of the VCO, Ripple on the i