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`US 20080288748Al
`
`c19) United States
`c12) Patent Application Publication
`Sutardja et al.
`
`(54) DYNAMIC CORE SWITCHING
`
`(76)
`
`Inventors:
`
`Sehat Sutardja, Los Altos Hills,
`CA (US); Hong-Yi Chen, Fremont,
`CA (US); Premanand Sakarda,
`Acton, MA (US); Mark N.
`Fullerton, Austin, TX (US); Jay
`Heeb, Gilbert, AR (US)
`
`Correspondence Address:
`HARNESS, DICKEY & PIERCE P.L.C.
`5445 CORPORATE DRIVE, SUITE 200
`TROY, MI 48098 (US)
`
`(21) Appl. No.:
`
`12/215,760
`
`(22)
`
`Filed:
`
`Jun. 30, 2008
`
`Related U.S. Application Data
`
`(63)
`
`(60)
`
`Continuation of application No. 12/145,660, filed on
`Jun. 25, 2008, which is a continuation-in-part of appli(cid:173)
`cation No. 11/523,996, filed on Sep. 20, 2006.
`
`Provisional application No. 60/968,143, filed on Aug.
`27, 2007, provisional application No. 60/978,936,
`filed on Oct. 10, 2007, provisional application No.
`60/981,606, filed on Oct. 22, 2007, provisional appli(cid:173)
`cation No. 61/022,431, filed on Jan. 21, 2008, provi(cid:173)
`sional application No. 61/029,476, filed on Feb. 18,
`2008, provisional application No. 61/049,641, filed on
`
`c10) Pub. No.: US 2008/0288748 Al
`Nov. 20, 2008
`(43) Pub. Date:
`
`May 1, 2008, provisional application No. 61/058,050,
`filed on Jun. 2, 2008, provisional application No.
`60/825,368, filed on Sep. 12, 2006, provisional appli(cid:173)
`cation No. 60/823,453, filed on Aug. 24, 2006, provi(cid:173)
`sional application No. 60/822,015, filed on Aug. 10,
`2006.
`
`Publication Classification
`
`(51)
`
`Int. Cl.
`G06F 15180
`G06F 9/00
`
`(2006.01)
`(2006.01)
`(52) U.S. Cl. ................................... 712/20; 712/E09.001
`
`(57)
`
`ABSTRACT
`
`A core switching system includes a mode switching module
`that receives a switch signal to switch operation between a
`first mode and a second mode. During the first mode, instruc(cid:173)
`tions associated with applications are executed by a first
`asymmetric core, and a second asymmetric core is inactive.
`During the second mode, the instructions are executed by the
`second asymmetric core, and the first asymmetric core is
`inactive. A core activation module stops processing of the
`applications by the first asymmetric core after interrupts are
`disabled. A state transfer module transfers a state of the first
`asymmetric core to the second asymmetric core. The core
`activation module allows the second asymmetric core to
`resume execution of the instructions and the interrupts are
`enabled.
`
`.................................................................................................................... JI. . . . . . . . . . . . . . . . . . . . . . ..
`
`,···130
`~-··
`
`Register File
`
`- Registers
`- Checkpoints
`- Program Counters
`
`112
`
`LP Core
`
`P,P Pipelines
`
`S,p Stages
`
`Cache
`
`Transistors
`
`Control Module
`
`114
`
`~--------·--·-----------------·-···-· ................................................................................................................... ,
`
`Petitioner Samsung Ex-1007, 0001
`
`

`

`Patent Application Publication Nov. 20, 2008 Sheet 1 of 17
`
`US 2008/0288748 Al
`
`2
`
`Main Processor
`
`3
`
`Secondary
`Processor
`
`FIG. 1A
`Prior Art
`
`Processor # 1
`
`Processor# 2
`
`--------
`
`Processor# N
`
`I
`
`I
`
`I
`
`FIG. 1 B
`Prior Art
`
`16
`
`HP Processor
`
`FIG. 2
`
`12
`
`LP
`Processor
`
`Petitioner Samsung Ex-1007, 0002
`
`

`

`Patent Application Publication Nov. 20, 2008 Sheet 2 of 17
`
`US 2008/0288748 Al
`
`42-1
`
`Application
`
`• :
`
`__ A_p_p-lic_;_ti-on--,fi•
`
`2
`2
`•
`
`24
`
`28
`
`HP Core
`
`Cache
`
`26
`
`THREADS
`
`LP Core
`
`Cache
`
`30
`
`Control Module
`
`34
`
`___ • __ __,• u : • ,
`
`. . .
`
`Application
`
`r, :
`:,•, 42-P
`! : 44-1
`: i
`Application
`....__A_p_p-lic_;_tio_n_ ..... ~~2
`
`Application
`
`_ . . . . . . . , ._ · __ ..... •
`...
`
`r, ;
`Lt-_·:.:.·:. 44-Q
`:
`.---A-p_p_lic-a"""ti-on--,..+--:,:
`
`46-1
`
`fi46-2
`
`Appli7Uon
`
`Appli;.,lon ~•6-R
`--------·· ............................. i
`... ----·········· ---------------·
`
`FIG. 3A
`
`Petitioner Samsung Ex-1007, 0003
`
`

`

`Patent Application Publication Nov. 20, 2008 Sheet 3 of 17
`
`US 2008/0288748 Al
`
`- -- - - - - - - - -- - - ·- -- -- -- -- -- -- -- • - - • -- - - - - - - • -- - - •• -- - - - - -- -- -- -- - - -- - - -- - - -- -- -- -- -- - - -- -- -- - - •• -- - J. ••• - -- - - •••• -- -- -- ••••
`
`,··· 130
`
`..
`..
`
`HP Core
`
`PHP Pipelines
`
`SHP Stages
`
`Cache
`
`THREADS
`
`LP Core
`
`PLP Pipelines
`
`SLP Stages
`
`Cache
`
`Transistors
`
`Register File
`
`- Registers
`- Checkpoints
`- Program Counters
`
`112
`
`Control Module
`
`114
`
`FIG. 38
`
`Petitioner Samsung Ex-1007, 0004
`
`

`

`z 0
`.... 0 =
`.... 0 = ""O = O" -....
`t "e -....
`
`~ ....
`
`(')
`
`~ ....
`
`(')
`
`('D = ....
`~ ....
`""O
`
`> ....
`
`QO
`.i;...
`-....J
`QO
`QO
`N
`
`0
`0
`N
`rJJ
`c
`
`QO --- 0
`
`....
`0 ....
`('D ....
`rJJ =(cid:173)
`
`.i;...
`
`('D
`
`-....J
`
`QO
`0
`0
`N
`~o
`N
`~
`
`Signal
`Mode
`
`,
`
`Module
`
`Core Profile
`
`120
`
`-
`
`-
`
`.
`
`,
`
`118
`
`on Type
`Applicati
`
`Usage·
`Cache
`
`Count
`Thread
`
`Usage
`
`Page File
`
`Usage
`Core
`
`FIG. 3D
`
`Settings
`
`User
`
`Cache Monitoring -r124
`
`Module
`
`v-122
`
`..,,,,,,
`
`Module
`
`Thread Transfer
`
`I
`
`Module
`Profile
`
`Idle
`
`Module
`Profile
`
`Module
`
`Core Profile
`
`"' Performance
`'
`
`'
`
`116
`
`120
`
`FIG. 3C
`
`1
`
`Control Module
`
`-
`
`Petitioner Samsung Ex-1007, 0005
`
`

`

`Patent Application Publication Nov. 20, 2008 Sheet 5 of 17
`
`US 2008/0288748 Al
`
`300~
`
`304
`
`Start
`
`LP
`
`N
`
`Increase power to HP
`Core and HP cache
`
`330
`
`Increase power to LP
`Core and LP cache
`
`N
`
`310
`
`Transfer threads of
`running applications to
`HP Core
`
`338
`
`Transfer threads of
`running applications to
`LP Core
`
`318
`
`FIG. 4
`
`Petitioner Samsung Ex-1007, 0006
`
`

`

`z 0
`.... 0 =
`.... 0 = ""O = O" -....
`t "e -....
`
`> ....
`
`QO
`.i;...
`-....J
`QO
`QO
`N
`
`0
`0
`N
`rJJ
`c
`
`QO --- 0
`
`-....J
`
`....
`0 ....
`('D ....
`rJJ =(cid:173)
`
`O'I
`
`('D
`
`QO
`0
`0
`N
`~o
`N
`~
`
`~ ....
`
`(')
`
`~ ....
`
`(')
`
`('D = ....
`~ ....
`""O
`
`240
`
`Module
`
`Core Profile
`
`PMS Module
`
`234
`
`Devices
`
`1/0
`
`242
`
`FIG. 5
`
`224-P
`
`224-2
`
`224-1
`
`228
`
`Memory
`
`Main
`
`212
`
`213
`
`Module
`switching
`
`Core
`
`Module
`
`Hypervisor
`
`204
`
`208
`
`L2 Cache
`
`L 1 Cache
`
`HP Core
`
`Kernel Module
`
`220
`
`I ••••••••••• ••••••••••••••••••••••••••••• • • •••••••••••• •••
`
`' ' '
`' ' ' ' '
`
`206
`
`200
`
`L 1 Cache
`
`LP Core
`
`205
`
`210
`
`HS Memory
`
`Petitioner Samsung Ex-1007, 0007
`
`

`

`Patent Application Publication Nov. 20, 2008 Sheet 7 of 17
`
`US 2008/0288748 Al
`
`306
`
`310
`
`320
`
`324
`
`Start
`
`250
`
`r - - - - - - " ' - - - - - - - , - - 2 5 2
`Profiling tool monitors system loading
`of LP Core.
`
`296
`
`Read state of HP Core and copy state
`into memory
`
`N
`
`260
`
`Transition LP Core to active state
`
`Read state of LP Core and copy state
`into memory
`
`On resume status, load state from
`memory into LP Core
`
`Transition HP Core to inactive state
`
`Resume execution in LP processor
`
`Execute Application level
`
`Transition HP processor to active
`state
`-------r--------;::..-268
`
`Load state of LP Core from memory
`into HP processor
`
`Transition LP processor to inactive
`state
`
`Resume execution in HP processor
`
`Execute Application level
`
`Profiling tool monitors speed or other
`parameters of HP processor.
`
`288
`
`N
`
`292
`
`FIG. 6
`
`Petitioner Samsung Ex-1007, 0008
`
`

`

`Patent Application Publication
`
`Nov. 20, 2008 Sheet 8 of 17
`
`US 2008/0288748 Al
`
`Start
`
`328
`
`N
`
`334
`
`Monitor speed of LP processor
`
`338
`
`Monitor executing application type
`
`y
`
`N
`
`Transition to HP processor
`
`356
`
`Monitor speed of HP processor
`
`N
`
`y
`
`364
`
`Transition to HP processor
`
`N
`
`N
`
`Transition to LP processor
`
`376
`
`FIG. 7
`
`Petitioner Samsung Ex-1007, 0009
`
`

`

`> ....
`
`0
`0
`N
`rJJ
`c
`
`QO --- 0
`
`QO
`.i;...
`-....J
`QO
`QO
`N
`
`FIG. SA
`
`~ -
`
`z 0
`.... 0 =
`.... 0 = ""O = O" -....
`('D = ..... t "e -....
`
`~ .....
`
`(')
`
`~ .....
`
`(')
`
`~ .....
`""O
`
`1,0
`
`('D
`('D
`
`....
`0 ....
`.....
`rJJ =(cid:173)
`
`-....J
`
`QO
`0
`0
`N
`~o
`N
`~
`
`'-202
`"
`
`I L 1 Cache I
`
`LP Core
`
`/200
`
`Wakeup Signal Exchange
`
`Wakeup Signal Exchange
`
`j
`
`380
`
`LP Core WFI Wakeup
`
`Masked Interrupts &
`
`Module
`
`Glue Logic
`
`HP Core WFI Wakeup
`
`Masked Interrupts &
`
`Debug
`
`Trace
`
`(IRQ, FIQ)
`
`External Interrupts
`
`J
`
`I
`
`L2oa
`
`L2 Cache
`
`206 ~ L 1 Cache
`
`HP Core
`
`,;-204
`
`Petitioner Samsung Ex-1007, 0010
`
`

`

`z 0
`.... 0 =
`.... 0 = ""O = O" -....
`('D = ..... t "e -....
`
`> ....
`
`QO
`.i;.,.
`-....J
`QO
`QO
`N
`
`0
`0
`N
`rJJ
`c
`
`QO --- 0
`
`....
`0 ....
`0
`....
`.....
`rJJ =(cid:173)
`
`('D
`('D
`
`-....J
`
`QO
`0
`0
`N
`~o
`N
`~
`
`~ .....
`
`(')
`
`~ .....
`
`(')
`
`~ .....
`""O
`
`FIG. 8B
`
`~
`
`~
`
`Wakeup Signal Exchange
`
`Wakeup Signal Exchange
`
`'--2c 2
`"
`
`'
`
`I L1 Cache I
`
`HP Core
`
`;-200
`
`Debug
`
`Trace
`
`Device
`
`Debug Mux
`
`• J384
`
`Trace Macro &
`
`386
`
`Module
`
`Mux Control
`
`L382
`
`Mux Control
`
`LP Core WFI Wakeup
`
`Masked Interrupts &
`
`Mux Device
`
`Interrupt Control &
`
`HP Core WFI Wakeup
`Masked Interrupts &
`
`_r380
`
`(IRQ, FIQ)
`
`External Interrupts
`
`I
`
`'-208
`
`L2 Cache
`
`I
`
`206 ~ L 1 Cache
`
`HP Core
`
`_;-204
`
`Petitioner Samsung Ex-1007, 0011
`
`

`

`z 0
`.... 0 =
`.... 0 = ""O = O" -....
`('D = ..... t "e -....
`
`> ....
`
`QO
`.i;...
`-....J
`QO
`QO
`N
`
`0
`0
`N
`rJJ
`c
`
`QO --- 0
`
`....
`0 ....
`....
`....
`.....
`rJJ =(cid:173)
`
`('D
`('D
`
`-....J
`
`QO
`0
`0
`N
`~o
`N
`~
`
`~ .....
`
`(')
`
`~ .....
`
`(')
`
`~ .....
`""O
`
`Hypervisor Module
`
`415
`
`414
`
`FIG. 9A
`
`Hardware Devices
`
`Module
`
`Sequence
`
`Core
`
`Module
`Switching
`
`Core
`
`Module
`
`Glue Logic
`
`380
`
`413
`
`LP & HP Cores
`
`420
`
`422
`
`432
`
`State Monitoring Module
`
`Device Timeout and
`
`Module
`PMU
`
`428 £430
`
`Module
`PMIC
`
`Device Driver Module
`
`Module
`Driver
`Battery
`
`426
`
`418
`
`424
`
`Module
`
`Scheduling
`
`Module
`IOCTL
`Kernel
`
`Module
`Profile
`Core
`
`Module
`Profile
`
`OS Task
`
`Module
`
`Idle Profile
`
`Module
`Profile
`
`Performance
`
`OS Services Module
`
`412
`
`410
`
`408
`
`406
`
`Applications
`
`416
`
`!400
`
`Event
`
`404
`
`Module
`
`Power Control
`
`User Profiles
`
`Power Management System (PMS) Module
`
`402
`
`Petitioner Samsung Ex-1007, 0012
`
`

`

`z 0
`.... 0 =
`.... 0 = ""O = O" -....
`('D = ..... t "e -....
`
`~ .....
`
`(')
`
`~ .....
`
`(')
`
`~ .....
`""O
`
`> ....
`
`QO
`.i;...
`-....J
`QO
`QO
`N
`
`0
`0
`N
`rJJ
`c
`
`QO --- 0
`
`....
`0 ....
`N
`....
`.....
`rJJ =(cid:173)
`
`('D
`('D
`
`-....J
`
`QO
`0
`0
`N
`~o
`N
`~
`
`380
`
`I Module
`I Glue Logic
`
`, ... 414
`
`Module
`Switching
`
`Core
`
`L43s
`
`'-
`
`Call
`
`r-W-434
`
`Module
`
`FCS
`
`Module
`vcs
`
`Module
`ccs
`
`µ413
`
`\
`4387
`
`4
`
`I
`
`'-422
`\
`
`Module
`
`Scheduling
`
`Module
`IOCTL
`Kernel
`
`OS Services Module
`
`416""""l,....--"
`
`Call
`
`Thread Quantl
`
`No. of Process
`No. of Tasks
`
`FIG. 9B
`
`420""1_ LP & HP Cores
`
`410....J t
`
`406J
`
`Module
`Profile
`
`Module
`Profile
`
`OS Task
`
`Performance
`
`r-1~
`
`Module
`412~ Profile
`Core
`
`Event
`
`404J
`
`428
`
`. Power Control -
`
`Module
`
`PMS Module
`
`1402
`
`Monitoring Module
`
`and State
`
`Device Timeout
`
`.)432
`
`[;426
`
`Module
`Driver
`Battery
`
`1,,418
`
`Device Driver Module
`
`Hardware Devices
`
`Module
`
`I PMIC
`
`Petitioner Samsung Ex-1007, 0013
`
`

`

`Patent Application Publication Nov. 20, 2008 Sheet 13 of 17
`
`US 2008/0288748 Al
`
`v
`.......
`v
`
`I
`
`.......
`v
`.......
`v
`
`Q)
`::::J
`"O
`0
`~
`C)
`c:::
`.c:::
`....,
`(.)
`"§
`Cl)
`(])
`"O
`0
`~
`
`Q)
`::::J
`"O
`0
`~
`C)
`c:::
`.c:::
`....,
`(.)
`"§
`Cl)
`~
`0
`u
`
`N
`v
`I
`.......
`.._,.
`~
`
`Q)
`::::J
`"O
`0
`~
`c:::
`0
`:,.::::;
`ro
`>
`:,.::::;
`(.)
`<(
`~
`0
`u
`
`('I')
`.._,.
`I
`.......
`v
`
`Q)
`::::J
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`~
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`
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`
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`ro
`I-
`....,
`(])
`ro
`....,
`en
`
`0
`en
`-
`(!)
`LL
`
`■
`
`Petitioner Samsung Ex-1007, 0014
`
`

`

`Patent Application Publication
`
`Nov. 20, 2008 Sheet 14 of 17
`
`US 2008/0288748 Al
`
`Start
`
`502
`
`!500
`
`508
`
`510
`
`512
`
`Disable interrupts
`
`Complete pending
`R/W
`
`Call hypervisor
`module to switch
`Cores
`
`Save Core1 state
`
`Flush L 1 cache for
`coherency
`
`Send event to
`Core2
`
`Reload Core1
`state
`
`Resume Core1
`
`Enable Interrupts
`
`y
`
`514
`
`516
`
`518
`
`528
`
`530
`
`532
`
`FIG. 10
`
`521
`
`Deactivate Core 1
`
`522
`
`Load Core1 state
`into Core2
`
`524
`
`Resume Core2
`
`526
`
`Enable Interrupts
`
`Petitioner Samsung Ex-1007, 0015
`
`

`

`Patent Application Publication Nov. 20, 2008 Sheet 15 of 17
`
`US 2008/0288748 Al
`
`•:·859
`
`. ' , ,
`
`----------------------------------·--------------------------------··
`Cellular Phone
`
`866
`
`860
`
`867
`
`966
`
`960
`
`967
`
`Power
`Supply
`
`869
`
`862
`
`Storage
`Device
`
`Memory
`
`864
`
`Network
`Interface
`
`Mic
`
`Cell Phone
`Control
`Module
`
`Display
`
`User Input
`
`FIG. 11A
`
`870
`872
`874
`876
`
`•:·958
`
`. ' ' .
`
`---------------························------------------------------
`Wireless Handset
`
`Power
`Supply
`
`962
`
`964
`
`Storage
`Device
`
`Memory
`
`Mic
`
`Handset
`Control
`Module
`
`i - - - - -N Audio Out
`
`Display
`
`• • •
`~---······------------------······-··············--·-·····-···········
`
`User Input
`
`970
`972
`974
`976
`
`FIG. 11B
`
`Petitioner Samsung Ex-1007, 0016
`
`

`

`Patent Application Publication Nov. 20, 2008 Sheet 16 of 17
`
`US 2008/0288748 Al
`
`,•--989
`• • I
`r······················-----------..4! --------------------------------
`Mobile Device
`
`Storage
`Device
`
`993
`
`Memory
`
`992
`
`Network
`Interface
`
`994
`
`Power
`Supply
`
`Mobile Device
`Control
`Module
`
`,---., Audio Output
`
`Display
`
`User Input
`
`997
`998
`996
`
`L-------------- ----------------••-•----•---•------•------•------••--
`990
`
`FIG. 11C
`
`• ---------------------------------..4.---------------------------------
`l
`GPS
`
`,---1089
`
`I
`I
`
`I .
`
`Power
`Supply
`
`Storage
`Device
`
`1093
`
`Memory
`
`1092
`
`991
`
`1091
`
`GPS Control
`Module
`
`r---'PI Audio Output
`
`Display
`
`User Input
`
`1097
`1098
`1096
`
`1090
`
`FIG. 11D
`
`Petitioner Samsung Ex-1007, 0017
`
`

`

`Patent Application Publication Nov. 20, 2008 Sheet 17 of 17
`
`US 2008/0288748 Al
`
`r-1100
`-------------------------------------------------------------------··--------------------------------------·-·-·--
`Desktop/Server
`
`1102
`
`Multi-Core
`Processing
`System
`
`Multi-Core
`Control Module
`
`1103
`
`1106
`
`Memory
`
`1108
`
`1/0 Core
`
`1/0 Devices
`
`1110
`
`1104
`
`1112
`-----------------------------------------------·-·····------------····----------·--·------------------······-------·
`' '
`
`Power Supply
`
`FIG. 11 E
`
`Petitioner Samsung Ex-1007, 0018
`
`

`

`US 2008/0288748 Al
`
`Nov. 20, 2008
`
`1
`
`DYNAMIC CORE SWITCHING
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`[0001] This application is a continuation of U.S. applica(cid:173)
`tion Ser. No. 12/145,660, filed Jun. 25, 2008, which claims
`the benefit of U.S. Provisional Application No. 60/968,143,
`filedAug. 27, 2007; U.S. ProvisionalApplicationNo. 60/978,
`936, filed Oct. 10, 2007; U.S. Provisional Application No.
`60/981,606, filed Oct. 22, 2007; U.S. Provisional Application
`No. 61/022,431 filed Jan. 21, 2008; U.S. Provisional Appli(cid:173)
`cation No. 61/029,476, filed Feb. 18, 2008; U.S. Provisional
`Application No. 61/049,641, filed May 1, 2008; and U.S.
`Provisional Application No. 61/058,050, filed Jun. 2, 2008
`and is a continuation-in-part of U.S. application Ser. No.
`11/523,996, filed Sep. 20, 2006, which claims the benefit of
`U.S. Provisional Application No. 60/825,368, filed Sep. 12,
`2006; U.S. Provisional Application No. 60/823,453, filed
`Aug. 24, 2006; and U.S. Provisional Application No. 60/822,
`015, filed Aug. 10, 2006. The disclosures of the above appli(cid:173)
`cations are incorporated herein by reference in their entirety.
`
`FIELD
`
`[0002] The present disclosure relates to mobile computing
`devices, and more particularly to dynamically switching
`cores of multi-core processing systems of mobile computing
`devices.
`
`BACKGROUND
`
`[0003] The background description provided herein is for
`the purpose of generally presenting the context of the disclo(cid:173)
`sure. Work of the presently named inventors, to the extent it is
`described in this background section, as well as aspects of the
`description that may not otherwise qualify as prior art at the
`time of filing, are neither expressly nor impliedly admitted as
`prior art against the present disclosure.
`[0004] Mobile computing devices such as cellular phones,
`MP3 players, global positioning system (GPS) devices, etc.
`are typically powered using both line power and battery
`power. The mobile computing devices typically include a
`processor, memory and a display, which consume power dur(cid:173)
`ing operation. The processor generally executes both simple
`applications that are less processing-intensive and complex
`applications that are more processing-intensive. Therefore,
`the capabilities of the processor such as processing speed are
`typically selected to match the performance requirements of
`the most processing-intensive applications that will be
`executed.
`[0005] One significant limitation of mobile computing
`devices relates to the amount of time for which the devices
`can be operated using batteries without recharging. Using a
`high-speed processor that meets the performance require(cid:173)
`ments of the processing-intensive applications generally
`increases power consumption, which corresponds to a rela(cid:173)
`tively short battery life.
`[0006] Referring now to FIGS. lA and 1B, some desktop
`and laptop computers use multiple processor integrated cir(cid:173)
`cuits (ICs) or a single processor IC with multiple cores. These
`systems can be of different types. As used herein, the term
`processor is used to refer to an IC with one or more processing
`cores. A multi-core processor refers to an IC, a system-on(cid:173)
`chip (SOC), or a system-in-package (SIP) with two or more
`processing cores.
`
`In FIG. lA, an asymmetric multi-processor (MP)
`[0007]
`system 1 comprising a main processor 2 and one or more
`secondary processors 3 is shown. The asymmetric MP system
`1 may also be implemented as a single IC or SOC with a main
`core and a secondary core. The main processor 2 has a dif(cid:173)
`ferent instruction set architecture (ISA) than the secondary
`processors 3. An operating system (OS) may run on the main
`processor 2. Applications may run on the secondary proces(cid:173)
`sors 3. The secondary processors 3 do not run threads of the
`OS and may be invisible to an OS scheduler. An OS driver
`interface to a real-time OS (RTOS) may run on the secondary
`processors 3. Key functions may be offloaded to the second(cid:173)
`ary processors 3 for power saving and reducing the duty cycle
`of the main processor 2. For example only, the asymmetric
`MP system 1 can be used for special-purpose processing (e.g.,
`video, 3D graphics, etc.). Since the secondary processors 3
`may run in addition to the main processor 2 when applications
`are executed, the asymmetric MP system 1 may consume
`large amounts of power.
`[0008]
`InFIG.1B, a symmetric MP system 5 may comprise
`N identical processors, where N is an integer greater than 1.
`The symmetric MP system 5 may also be implemented as a
`single IC or SOC with N identical cores. N may be propor(cid:173)
`tional to the processing load of the symmetric MP system 5.
`The N processors use the same ISA. The N processors may be
`visible to the OS scheduler. The N processors may have
`transparent access to system resources including memory and
`input/output (I/0). Depending on the processing load, one or
`more of the N processors can be utilized to execute applica(cid:173)
`tions. The high cost and high power consumption of the
`symmetric MP system 5 tends to make this architecture
`unsuitable for lower cost mobile devices.
`
`SUMMARY
`
`[0009] A system comprises a first asymmetric core, a sec(cid:173)
`ond asymmetric core, and a core switching module. The first
`asymmetric core executes an application when the system
`operates in a first mode and is inactive when the system
`operates in a second mode. The second asymmetric core
`executes the application when the system operates in the
`second mode. The core switching module switches operation
`of the system between the first mode and the second mode.
`The core switching module selectively stops processing of the
`application by the first asymmetric core after receiving a first
`control signal. The core switching module transfers a first
`state of the first asymmetric core to the second asymmetric
`core. The second asymmetric core resumes executing the
`application in the second mode.
`[0010]
`In another feature, the first control signal indicates
`that interrupts are disabled.
`[0011]
`In another feature, the second asymmetric core
`executes instructions without instruction translation when the
`second asymmetric core resumes executing the application
`during the second mode.
`[0012]
`In other features, the system further comprises an
`operating system (OS) that provides services to the applica(cid:173)
`tion. The core switching module switches execution of the
`application between the first asymmetric core and the second
`asymmetric core transparently to the OS.
`[0013]
`In other features, a first maximum speed of the first
`asymmetric core is greater than a second maximum speed of
`the second asymmetric core. The first asymmetric core oper(cid:173)
`ates at frequencies greater than a predetermined frequency.
`The second asymmetric core operates at frequencies less than
`
`Petitioner Samsung Ex-1007, 0019
`
`

`

`US 2008/0288748 Al
`
`Nov. 20, 2008
`
`2
`
`the predetermined frequency. A first maximum operating
`power level of the first asymmetric core is greater than a
`second maximum operating power level of the second asym(cid:173)
`metric core.
`[0014]
`In other features, the first asymmetric core uses a
`first instruction set architecture (ISA). The second asymmet(cid:173)
`ric core uses a second ISA. The first ISA is compatible with
`the second ISA. A first set of instructions of the first ISA is a
`superset ofa second set ofinstructions of the second ISA. The
`first set includes more instructions than the second set.
`[0015]
`In other features, the OS comprises a kernel. The
`core switching module executes above a level of the kernel.
`[0016]
`In other features, the system further comprises a
`hypervisor module. The core switching module is integrated
`with the hypervisor module.
`[0017]
`In other features, the core switching module saves
`the first state when the core switching module selectively
`stops processing of the application by the first asymmetric
`core. The core switching module powers up the second asym(cid:173)
`metric core and initializes the second asymmetric core using
`the first state. The interrupts are enabled after the second
`asymmetric core resumes executing the application. The core
`switching module shuts down the first asymmetric core when
`the second asymmetric core powers up. One of no power and
`standby power is supplied to the first asymmetric core after
`the first asymmetric core is shut down.
`[0018]
`In other features, the system further comprises a
`level-2 (L2) cache that communicates with the first asymmet(cid:173)
`ric core. One of no power and standby power is supplied to the
`L2 cache after the first asymmetric core is shut down.
`[0019]
`In other features, the core switching module initial(cid:173)
`izes the first asymmetric core using the first state when the
`second asymmetric core fails to power up. The first asymmet(cid:173)
`ric core resumes executing the application in the first mode
`and interrupts are enabled.
`[0020]
`the core switching module
`In other features,
`switches operation of the system between the second mode
`and the first mode. The core switching module selectively
`stops processing of the application by the second asymmetric
`core after receiving the first control signal. The core switching
`module transfers a second state of the second asymmetric
`core to the first asymmetric core. The first asymmetric core
`resumes executing the application in the first mode. The first
`control signal indicates that interrupts are disabled.
`[ 0021]
`In another feature, instructions are executed without
`instruction translation when the first asymmetric core
`resumes executing the application during the first mode.
`[0022]
`In other features, the system further comprises an
`operating system (OS) that provides services to the applica(cid:173)
`tion. The core switching module switches execution of the
`application between the second asymmetric core and the first
`asymmetric core transparently to the OS.
`[0023]
`In other features, the core switching module saves
`the second state when the core switching module selectively
`stops processing of the application by the second asymmetric
`core. The core switching module powers up the first asym(cid:173)
`metric core and initializes the first asymmetric core using the
`second state. The interrupts are enabled after the first asym(cid:173)
`metric core resumes executing the application.
`[0024]
`In other features, the system further comprises a
`level-2 (L2) cache that communicates with the first asymmet(cid:173)
`ric core. Power is supplied to the L2 cache after the first
`asymmetric core powers up.
`
`[0025]
`In other features, the core switching module shuts
`down the second asymmetric core when the first asymmetric
`core powers up. One ofno power and standby power is sup(cid:173)
`plied to the second asymmetric core after the second asym(cid:173)
`metric core is shut down.
`[0026]
`In other features, the core switching module initial(cid:173)
`izes the second asymmetric core using the second state when
`the first asymmetric core fails to power up. The second asym(cid:173)
`metric core resumes executing the application in the second
`mode, and the interrupts are enabled.
`[0027]
`In another feature, the system further comprises a
`core profile module that generates a second control signal
`based on at least one of core utilization, resource utilization,
`and performance of the application.
`[0028]
`In other features, the system further comprises a
`core change sequence (CCS) module that initiates a CCS
`based on the second control signal. The core switching mod(cid:173)
`ule switches execution of the application between one of the
`first and second asymmetric cores and another of the first and
`second asymmetric cores based on the CCS.
`[0029]
`In other features, the CCS module initiates the CCS
`when the core utilization of the second asymmetric core by
`the application is greater than or equal to a first predetermined
`threshold. The CCS module initiates the CCS when the core
`utilization of the second asymmetric core by the application is
`greater than or equal to a second predetermined threshold for
`a first predetermined time period. The CCS module initiates
`the CCS when an anticipated core utilization of the second
`asymmetric core is greater than or equal to a third predeter(cid:173)
`mined threshold. The anticipated core utilization is deter(cid:173)
`mined based on at least one of a type of the application and a
`history of execution of the application. The CCS module
`initiates the CCS when the core utilization of the first asym(cid:173)
`metric core by the application is less than or equal to a fourth
`predetermined threshold. The CCS module initiates the CCS
`when the core utilization of the first asymmetric core by the
`application is less than or equal to a fifth predetermined
`threshold for a second predetermined time period.
`[0030]
`In another feature, the CCS module initiates the
`CCS based on at least one of a type of the application, a
`number of applications, and a type of instruction executed by
`one of the first and second asymmetric cores.
`[0031]
`In another feature, the core profile module generates
`the second control signal based on a number of times execu(cid:173)
`tion of applications is switched between one of the first and
`second asymmetric cores and another of the first and second
`asymmetric cores.
`[0032]
`In other features, the system further comprises a
`power control module that controls power consumption of the
`system and that generates a third control signal based on the
`second control signal and the power consumption. The sys(cid:173)
`tem further comprises a core change sequence (CCS) module
`that initiates a CCS based on the third control signal. The core
`switching module switches execution of the application
`between one of the first and second asymmetric cores and
`another of the first and second asymmetric cores based on the
`CCS.
`[0033]
`In another feature, the system further comprises a
`frequency change sequence (FCS) module that initiates a
`FCS based on the second control signal and that selects an
`operating frequency of at least one of the first and second
`asymmetric cores based on the FCS.
`[0034]
`In another feature, the system further comprises a
`voltage change sequence (VCS) module that initiates a VCS
`
`Petitioner Samsung Ex-1007, 0020
`
`

`

`US 2008/0288748 Al
`
`Nov. 20, 2008
`
`3
`
`based on the second control signal and that selects a supply
`voltage of at least one of the first and second asymmetric
`cores based on the VCS.
`In another feature, the system further comprises a
`[0035]
`power management module that disables the interrupts when
`the system switches operation between the first mode and the
`second mode and that disables the interrupts when the system
`switches operation between the second mode and the first
`mode.
`In other features, the system further comprises a
`[0036]
`plurality of the first asymmetric core. The core switching
`module selectively activates and deactivates more than one of
`the plurality of the first asymmetric core based on the CCS
`when the system operates in the first mode.
`In another feature, the system further comprises a
`[0037]
`glue logic module that selectively communicates with the
`core switching module, that receives interrupts, that receives
`first signals from the application, and that routes the interrupts
`and the first signals to the one of the first and second asym(cid:173)
`metric cores activated by the core switching module.
`In another feature, a system-on-chip (SOC) com(cid:173)
`[0038]
`prises the system.
`In another feature, a system-in-package (SIP) com(cid:173)
`[0039]
`prises the system.
`In still other features, a method comprises executing
`[0040]
`an application using a first asymmetric core when operating
`in a first mode. The first asymmetric core is inactive when
`operating in a second mode. The method further comprises
`switching operation between the first mode and the second
`mode using a core switching module. The method further
`comprises selectively stopping processing of the application
`by the first asymmetric core using the core switching module
`after receiving a first control signal. The method further com(cid:173)
`prises transferring a first state of the first asymmetric core to
`the second asymmetric core using the core switching module
`and resuming execution of the application in the second mode
`using the second asymmetric core.
`In another feature, the method further comprises
`[0041]
`disabling interrupts and indicating via the first control signal
`that the interrupts are disabled.
`In another feature, the method further comprises
`[0042]
`executing instructions without instruction translation when
`the second asymmetric core resumes executing the applica(cid:173)
`tion during the second mode.
`In another feature, the method further comprises
`[0043]
`providing services to the application via an operating system
`(OS) and switching execution of the application between the
`first asymmetric core and the second asymmetric core trans(cid:173)
`parently to the OS using the core switching module.
`In other features, the method further comprises
`[0044]
`selectively operating the first asymmetric core at a first maxi(cid:173)
`mum speed and selectively operating the second asymmetric
`core at a second maximum speed. The first maximum speed is
`greater than the second maximum speed. The method further
`comprises selectively operating the first asymmetric core at a
`first maximum operating power level and selectively operat(cid:173)
`ing the second asymmetric core at a second maximum oper(cid:173)
`ating power level. The first maximum operating power level is
`greater than the second maximum operating power level. The
`method further comprises selectively operating the first
`asymmetric core at frequencies greater than a predetermined
`frequency and selectively operating the second asymmetric
`core at frequencies less than the predetermined frequency.
`
`In other features, the method further comprises
`[0045]
`operating the first asymmetric core using a first instruction set
`architecture (ISA) and operating the second asymmetric core