(12) United States Patent
`Kruglick
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 8,892,931 B2
`Nov. 18, 2014
`
`US008892931B2
`
`(54) POWER CHANNEL MONITOR FORA
`MULTICORE PROCESSOR
`(75) Inventor: Ezekiel John Joseph Kruglick, Poway,
`CA (US)
`
`(73) Assignee: tips theseevelopment LLC,
`glon,
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 260 days.
`
`(*) Notice:
`
`1
`(21) Appl. No.: 12/582,301
`(22) Filed:
`Oct. 20, 2009
`
`(65)
`
`Prior Publication Data
`
`Apr. 21, 2011
`
`US 2011 FOO93733 A1
`(51) Int. Cl.
`G06F L/26
`(2006.01)
`G06F L/32
`(2006.01)
`(52) U.S. Cl
`CPC ............ Goof ta203 (2013.01). Goof ta243
`(2013.01); Y02B 60/1239 (2013.01)
`USPC ............. 713/340; 713/300; 713/320: 714/22;
`711/211: 711/E12.033
`(58) Field of Classification Search
`USPC ................. 713/300,320, 322,323,324, 340;
`714/22; 711/211, E12.033
`See application file for complete search history.
`
`56
`(56)
`
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`
`(Continued)
`Primary Examiner — Michael J Brown
`(74) Attorney, Agent, or Firm Hope Baldauff, LLC
`(57)
`ABSTRACT
`Technologies are generally described for power channel
`monitoring in multicore processors. A power management
`system can be configured to monitor the power channels
`supplving individual cores within a multicore processor. A
`pply 1ng
`p
`power channel monitor can provide a direct measurement of
`power consumption for each core. The power consumption of
`individual cores can indicate which cores are encounterin
`9.
`higher or lower usage. The usage determination can be made
`without sending any data messages to, or from, the cores
`being measured. The determined usage load being serviced
`by each processor core may be used to adjust power and/or
`clock signals Supplied to the cores.
`
`19 Claims, 6 Drawing Sheets
`
`SUPPLY
`
`MANAGER
`160
`
`MONITOR
`150
`
`Patent Owner Daedalus Prime LLC
`Exhibit 2004 - Page 1 of 16
`
`

`

`US 8,892.931 B2
`Page 2
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`(56)
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`
`* cited by examiner
`
`Patent Owner Daedalus Prime LLC
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`US 8,892,931 B2
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`U.S. Patent
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`Nov. 18, 2014
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`US 8,892,931 B2
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`400 O
`
`BEGIN
`
`410
`MONITOR POWER CHANNELS SUPPLYING
`EACH CORE OF AMULTICORE PROCESSOR
`
`MEASURE POWER DELIVERED TO
`EACH CORE OVER THE POWER CHANNELS
`
`420
`
`430
`DETERMINE ALOADASSOCATED WITH
`EACH CORE FROM THE MEASURED POWER
`
`ADJUST THE POWER SUPPLIED TO
`A CORE BASEDUPON THE LOAD
`ASSOCATED WITH THE CORE
`
`ADJUST THE CLOCK SIGNAL TO
`A CORE BASEDUPON THE LOAD
`ASSOCATED WITH THE CORE
`
`440
`
`450
`
`460
`
`PROVIDE
`POWERMANAGEMENT INFORMATION TO
`THE MULTICORE PROCESSOR
`
`470
`EXPOSE A POWERMANAGEMENT CONTROL
`INTERFACE TO THE MULTICORE PROCESSOR
`
`
`
`FIG. 5
`
`Patent Owner Daedalus Prime LLC
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`

`1.
`POWER CHANNEL MONITOR FORA
`MULTICORE PROCESSOR
`
`US 8,892,931 B2
`
`2
`drawings, similar symbols typically identify similar compo
`nents, unless context dictates otherwise. The illustrative
`embodiments described in the detailed description, drawings,
`and claims are not meant to be limiting. Other embodiments
`may be utilized, and other changes may be made, without
`departing from the spirit or scope of the Subject matter pre
`sented herein. It will be readily understood that the present
`disclosure, as generally described herein, and illustrated in
`the figures can be arranged, Substituted, combined, separated,
`and designed in a wide variety of different configurations, all
`of which are explicitly contemplated herein.
`This disclosure is generally drawn, inter alia, to methods,
`apparatus, and systems related to power channel monitoring
`in multicore processors. Techniques are described for a power
`management system that can be configured to monitor the
`power channels Supplying individual cores within a multicore
`processor. The system may include a power monitor that
`provides a direct measurement of power consumption for
`each core. The power consumption of individual cores can
`indicate which cores are encountering higher or lower usage.
`The usage determination can be made without sending any
`data messages to, or from, the cores being measured. The
`determined usage load being serviced by each processor core
`may be used to adjust power and/or clock signals Supplied to
`the cores. Reducing data communications between cores can
`improve system operation, particularly as the number of cores
`increases. Furthermore, determining usage without datacom
`munications may also reduce processor computation cycles
`associated with traditional usage measurements such as
`operation counting.
`Powermonitoring in the manner presented herein can mea
`sure power consumed by processor cores within a multicore
`processor. The measured power and other power management
`information may be provided to a power manager module.
`The power manager module may be configured to adjust one
`or more operational parameters of the processor cores based
`upon the measured power. In some example scenarios, the
`power manager module may adjust the current, Voltage,
`power, clock signals, or any combination thereof provided to
`the corresponding processor cores. Example clock signal
`characteristics that can be adjusted may include a clock signal
`amplitude, frequency, Voltage, pulse width, period, or duty
`cycle. Also, the power manager module may be configured to
`indirectly adjust the use of, or task allocation to, each of the
`processor cores by providing power consumption and usage
`information to a higher level power management operation.
`Power monitoring in the manner presented herein can also
`provide more accurate processor core usage measurements
`than traditional temperature monitoring since temperature
`monitoring may be affected by the environment, the operation
`of neighboring cores, or other blocks within the integrated
`circuit Supporting the processor. Power monitoring can be
`used with dynamic Voltage and frequency scaling (DVFS)
`since the scaled Voltages or Switching frequencies will mani
`fest as reduced monitored power consumption. According to
`Some embodiments, power monitoring may also serve as a
`watchdog monitor to identify when a processor core is locked
`in an infinite loop or some other error state. These states can
`often be associated with consistently high power consump
`tion by an affected processor core.
`FIG. 1 is a block diagram illustrating a multicore processor
`120 configured for power channel monitoring according to
`one or more embodiments presented herein. The multicore
`processor 120 may comprise multiple cores 110A-110P. The
`multiple cores 110A-110P may be referred to collectively, or
`in general, as cores 110. A power Supply 130 (e.g., a power
`Supply circuit, a power Supply module, etc.) associated with
`
`BACKGROUND
`
`Unless otherwise indicated herein, the materials described
`in this section are not prior art to the claims in this application
`and are not admitted to be prior art by inclusion in this section.
`Multicore processors are generally made up of multiple
`processor cores with interconnections between the individual
`cores. Some architectures for interconnecting individual
`cores Support communication between neighboring cores
`with high efficiency. However, communications between
`nonadjacent cores within the multicore processor may incur
`delays due to passing messages between intermediate cores.
`As core counts within multicore processors increase, optimi
`Zation of communication between cores becomes increas
`ingly important. These communications may include mes
`sages querying the level load on the different cores within the
`multicore processor.
`Dynamic Voltage and frequency scaling (DVFS) is a power
`management technique where Voltages and/or clock frequen
`cies associated with a processor are adjusted to manage heat
`generation and power consumption. Dynamic Voltage scaling
`can decrease the Voltage applied to a processor in order to
`conserve power. This may be particularly useful in laptop
`computers and other types of battery powered mobile devices.
`Dynamic Voltage scaling can increase the Voltage applied to a
`processor in order to increase computer performance.
`Dynamic frequency scaling can decrease, or even pause, the
`clock frequency of the processor in order to decrease power
`consumption.
`Attempts to apply DVFS to individual cores within a mul
`ticore processor may encounter a number of difficulties as the
`number of cores increases. For example, obtaining steady and
`up-to-date information on the computation load or power
`required by each core through message queries to the cores
`can scale into a performance limitation for the multicore
`processor.
`
`5
`
`10
`
`15
`
`25
`
`30
`
`35
`
`BRIEF DESCRIPTION OF THE FIGURES
`
`The foregoing and other features of this disclosure will
`become more fully apparent from the following description
`and appended claims, taken in conjunction with the accom
`panying drawings. Understanding that these drawings depict
`only several embodiments in accordance with the disclosure
`and are, therefore, not to be considered limiting of its scope,
`the disclosure will be described with additional specificity
`and detail through use of the accompanying drawings, in
`which:
`FIG. 1 is a block diagram illustrating a multicore processor
`configured for power channel monitoring;
`FIG. 2 is a schematic diagram illustrating a multicore pro
`cessor with various power distribution architectures:
`FIG. 3 is a schematic diagram illustrating a multicore pro
`cessor having a multiplexed power monitor;
`FIG. 4 is a schematic diagram illustrating a multicore pro
`cessor having a multiplexed power monitor using current
`Sensors;
`FIG. 5 is a flow diagram illustrating a process for power
`channel monitoring in a multicore processor, and
`FIG. 6 is a block diagram illustrating an example comput
`ing system, all arranged according to at least some embodi
`ments presented herein.
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`DETAILED DESCRIPTION
`
`In the following detailed description, reference is made to
`the accompanying drawings, which form a parthereof. In the
`
`Patent Owner Daedalus Prime LLC
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`US 8,892,931 B2
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`10
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`15
`
`3
`the multicore processor 120 can be configured to provide
`power supply channels to the cores 110. The power supply
`channels may also be referred to as power rails. Power for
`each core, or group of cores, may be Supplied by a separate
`power channel.
`A power monitor 150 (e.g., a power monitor circuit, a
`power monitor module, etc.) associated with the multicore
`processor can be configured to monitor each of the power
`channels to determine the amount of power Supplied from the
`power supply 130 to each of the cores 110. A power manager
`160 (e.g., a power manager circuit, a power manager module,
`etc.) associated with the multicore processor 120 can be con
`figured to cooperatively operate with the power supply 130
`and the power monitor 150 to provide power management and
`thermal management for the multiprocessor 120.
`According to Some embodiments, the power manager 160
`can be configured to control the power supply 130 in response
`to measurements from the power monitor 150. According to
`some other embodiments, the power manager 160 can be
`configured to control clock signals Supplied to one or more of
`the cores 110 in response to measurements from the power
`monitor module 150. According to yet some other embodi
`ments, the power manager 160 can be configured to provide
`an interface to the cores 110 or other components of the
`multicore processor 120 or associated computing device. The
`provided interface may be adapted to read status information
`related to the power manager 160, Such as power channel
`measurements obtained from the power monitor 150. The
`interface may also be adapted to write to the power manager
`160 to set configurations, controls or other variables associ
`ated with one or more of the power manager 160, the power
`monitor 150, and/or the power supply 130.
`One example of dynamic thermal management that may be
`employed by the power manager 160 can be referred to as
`clock gating. Global clock gating can be adapted to turn off
`all, or Substantially all, clock signals to halt processor opera
`tion of multicore processor 120. Local clock gating can be
`adapted to turn off individual clock signals to cores 110 or
`other blocks of the multicore processor 120. The gating off of
`40
`clocks can temporarily reduce power consumption and may
`be used when there is an over-temperature condition or when
`an over-temperature condition is being avoided. While clocks
`are gated off, processor states Such as registers, branch pre
`dictor tables, and local caches may be maintained. As such,
`clock gating can act as a suspend, or sleep, mode for processor
`cores 110 within the multicore processor 120 rather than an
`off-switch.
`In addition to gating clock signals to temporarily stop one
`or more of the cores 110, the power manager 160 may also be
`configured to adjust the clock frequency (e.g., decrease the
`frequency to slow operational speed, or increase the fre
`quency to increase operational speed) Supplied to one or more
`of the cores 110. Alternatively, the clock may be run at a
`constant speed during the on-state of a duty cycle and gated
`off during the off-state of the duty cycle. As such, a clock duty
`cycle may adjusted by the power manager 160 to provide a
`periodic gating of the clock to reduce power consumption at
`the corresponding core 110. In addition to clock frequency
`and duty cycle, additional characteristics of the clock signal
`can be adjusted Such as signal amplitude (either single ended
`or differential), voltage or current level, pulse width, period,
`etc. Adjusting of one or more characteristics associated with
`clock signals may be controlled by the power manager 160
`Such that the power consumption associated with each of the
`individual cores 110 within the multicore processor 120 may
`be controlled.
`
`30
`
`4
`By providing a status and control interface, the power
`manager 160 may also be arranged to Support higher level
`power management techniques. For example, policy-based
`thread migration techniques can be configured to relocate
`processes or threads between the cores 110 to manage power
`consumption and thermal characteristics of multicore proces
`Sor 120. These higher level power management techniques
`may also be combined with physical approaches such as
`DVFS. Empirical tests can demonstrate that a multicore pro
`cessor 120 having two cores 110 using thread relocation
`management along with basic Voltage and frequency man
`agement can, in Some examples, yield approximately 250%
`improvement in available resources or inequivalent reduction
`in power consumption.
`According to another higher level, or hybrid, power man
`agement approach, a compiler or runtime environment may
`be configured to set optimization parameters used to compile
`or execute code according to the power management condi
`tion of a processor or core 110. The compiler can also be
`configured to suggest DVFS settings for the processor or core
`110 according to computational needs.
`It should be appreciated that the power channel monitoring
`techniques presented herein may be applied not only to pro
`cessor cores 110, but also to any other blocks or functional
`units within the multicore processor 120. For example,
`memories, caches, input/output drivers, controllers, other
`blocks, or other functional units within the multicore proces
`sor 120 may be supported by the power channel monitoring
`techniques presented herein. Furthermore, the techniques
`may be applied to any blocks, cores, modules, circuits or
`other Subdivisions within any integrated circuit, chip, system
`on chip (SOC), multichip array, application specific inte
`grated circuits (ASICs), field programmable gate arrays (FP
`GAS), other programmable logic, memories, controllers, or
`so forth where such subdivisions may have individual, or
`partially isolated, power Supply channels.
`It should be appreciated that functions of the power moni
`tor 150 and the power manager 160 may be provided within
`other modules. For example, such functionality may be inte
`grated into the power Supply 130 or other control, manage
`ment, or supervisor modules. Similarly, the functions of the
`power monitor 150 and the power manager 160 may be com
`bined into a single module.
`Turning now to FIG. 2, a schematic diagram illustrates a
`multicore processor 120 with various power distribution
`architectures arranged according to one or more embodi
`ments presented herein. The power supply 130 can be con
`figured to supply power to the cores 110 of the multicore
`processor. Power for each core, or group of cores, may be
`Supplied by a separate power channel. For example, power
`channel 210A may supply power from the power supply 130
`to the processor core 110A while power channel 210B may
`supply power from the power supply 130 to both of the
`processor cores 110B and 110C. Similarly, power channel
`210C may supply power from the power supply 130 to the
`three processor cores 110D, 110E, and 110F. According to
`Some embodiments, power may be supplied to each core, or
`group of cores, with two or more power channels. For
`example, the power channel 210D may be configured to sup
`ply power at 5VDC (volts direct current) to the processor core
`110G while a second power channel may be configured to
`supply power at 3.3 VDC to the same processor core 110G.
`Various other levels of power Supply Voltage or current may
`also be supported according to various embodiments.
`Turning now to FIG. 3, a schematic diagram illustrates a
`multicore processor 120 having a multiplexed power monitor
`arranged according to one or more embodiments presented
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`Patent Owner Daedalus Prime LLC
`Exhibit 2004 - Page 10 of 16
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`US 8,892,931 B2
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`herein. The power supply 130 can be configured to supply
`power to the cores 110 of the multicore processor. In this
`example, power can be supplied to core 110A over power
`channel 210A, to core 110B overpower channel 210B, and to
`core 110C over power channel 210C. The power channels
`210A-210C may be referred to collectively, or in general, as
`power channels 210. While three cores 110 are illustrated
`along with three power channels 210, it should be appreciated
`that any number of cores 110 and power channels 210 may be
`present within the multicore processor. The number of cores
`110 and power channels 210 may be the same, or the number
`may differ as more than one core 110 may be supplied by a
`single power channel 210 and a core 110 may be supplied by
`more than one power channel 210.
`The power delivered over each of the power channels 210
`may be measured by the power monitor 150. According to
`Some embodiments, an analog-to-digital converter (ADC)
`230 may be adapted to measure the analog state of a power
`channel 210 and provide digital information that corresponds
`to the measured analog state. In one example, the ADC 230
`may be configured to directly, or indirectly, measure the Volt
`age of a power channel 210. In another example, the ADC 230
`may be configured to measure the current of a power channel
`210 as further detailed with respect to FIG. 4.
`A multiplexer 220 may be configured to select which, of
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`several, power channels 210 is currently being sampled by the
`ADC 230. One or more control inputs 240 associated with the
`multiplexer 220 may be used to select the current power
`channel 210 for monitoring. The control inputs 240 may be
`provided by the power monitor 150, the power manager 160,
`a counter, a state machine, or other circuit or module associ
`ated with the power management of the multicore processor
`120. It should be appreciated that the multiplexer 220 and/or
`the ADC 230 may be integrated into the power monitor 150
`according to embodiments.
`The current and/or Voltage associated with the power chan
`nels 210 may be measured by the power monitor 150. Accord
`ing to various embodiments, the Voltage may be substantially
`fixed while the current may vary according to the power
`demand of the core 110. Alternatively, the current may be
`substantially fixed while the voltage varies according to the
`power demand of the core 110. Depending upon which of the
`current or Voltage are varying, the power monitor 150 can
`measure the varying current and/or the varying Voltage. The
`Substantially fixed current or Voltage can be a known, or
`specified, value. The power may then be computed according
`to the relationship that power equals current multiplied by
`voltage. For example, power (in Watts) may be determined by
`multiplying the current (in Amperes) by the Voltage (in Volts).
`Voltage may also be referred to as potential, electrical poten
`tial, potential difference, or electromotive force. Current may
`be viewed as a time rate of charge flow. Also, power may be
`considered a capacity for doing work in a given period of
`time, where work may be viewed as applying a force over a
`distance, such as when moving a charge against a field.
`The current and/or voltage of the power channels 210 may
`be measured by the power monitor 150 without substantial
`modification of the power delivery system within the multi
`core processor 120. As discussed above, direct measurement
`of the power supplied to cores 110 and other blocks of the
`multicore processor 120 can provide information about a
`computational load, or a usage level, associated with each
`core 110 without loading any data buses with message que
`1S.
`Measuring the power consumption of the cores 110 with
`the power monitor 150 may inform thermal modeling, ther
`mal load balancing, load planning, and other system manage
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`ment functions related to power and thermal management.
`According to some embodiments, the power manager 160
`may use the power consumption information associated with
`the processor cores 110 to adjust settings for the supplied
`voltages or clock frequencies of the associated cores 110. For
`example, if a particular processor core 110 is consuming a
`reduced amount of power, the power manager 160 may deter
`mine that the core 110 is handing a reduced computation load
`and thus lower the voltage supplied to that core 110, or reduce
`the clock frequency supplied to that core 110.
`In FIG. 4, a schematic diagram illustrates a multicore pro
`cessor 120 having a multiplexed power monitor using current
`sensors 310A-310C arranged according to one or more
`embodiments presented herein. A current sensor 310A may
`be placed inline with powerchannel 210A supplying power to
`core 110A. Similarly, current sensor 310B may be placed
`inline with power channel 210B supplying power to core
`110B and current sensor 310C may be placed inline with
`power channel 210C supplying power to core 110C. The
`current sensors 310A-310C may be referred to collectively, or
`in general, as current sensors 310. According to some
`embodiments, the power monitor 150 may be configured to
`measure a current associated with the Supply channels 210.
`These current measurements may be performed using current
`sensors 310. A signal representative of the measured current
`may be a Voltage (as discussed below) or a current and may be
`converted into a digital, or numerical, value using ADC 230.
`An example current sensor 310 may involve measuring a
`drop in potential, or Voltage, over a known load (or resistance)
`that is placed inline with the power channel 210 for which
`current being measured. However, it may be undesirable,
`from a thermal and power loss perspective, to drop an entire
`Supply current through a known load. Thus, a scaled current
`mirror may be used as a current sensor 310 where a scaled
`representation of the current in the supply channel 210 may be
`provided by the current mirror for measurement. Alterna
`tively, a feedback Voltage signal within the current mirror
`may be measured directly. A current mirror can be any circuit
`designed to copy a current Supplied through one component
`of the circuit by adjusting a current within another component
`of the circuit.
`Referring now to FIG. 5, additional details will be provided
`regarding the embodiments presented herein for power chan
`nel monitoring of core usage within a multicore processor. In
`particular, FIG. 5 is a flow diagram illustrating a process 400
`for power channel monitoring in a multicore processor
`arranged according to at least Some embodiments presented
`herein.
`It should be appreciated that the operations described
`hereinare implemented as a sequence of operational or manu
`facturing acts, as a sequence of computer implemented acts or
`program modules running on a computing system, or as inter
`connected machine logic circuits or circuit modules within
`the computing system. The implementation is a matter of
`choice dependent on the performance and other requirements
`of the various embodiments. Some of the logical operations
`desc