`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`XILINX, INC.,
`
`Petitioner
`
`v.
`
`POLARIS INNOVATIONS LIMITED,
`
`Patent Owner.
`
`
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 6,157,589
`
`Case No. IPR2023-00516
`
`
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`

`

`
`
`TABLE OF CONTENTS
`
`
`I.
`Introduction ...................................................................................................... 1
`II. Mandatory Notices (37 C.F.R. §42.8) ............................................................. 1
`A.
`Real Parties-In-Interest (37 C.F.R. §42.8(b)(1)) ................................... 1
`B.
`Related Matters (37 C.F.R. §42.8(b)(2)) ............................................... 1
`C.
`Lead and Back-Up Counsel (37 C.F.R. §42.8(b)(3)) ............................ 2
`D.
`Service Information ............................................................................... 2
`Payment of Fees (37 C.F.R. §42.103) ............................................................. 2
`III.
`IV. Requirements for IPR (37 C.F.R. §42.104) ..................................................... 3
`A. Grounds for Standing (37 C.F.R. §42.104(a)) ...................................... 3
`B.
`Challenge Under 37 C.F.R. §42.104(b) and Relief Requested ............. 3
`Summary of the ’589 Patent ............................................................................ 4
`A.
`Brief Description ................................................................................... 4
`B.
`Summary of the Prosecution ................................................................. 7
`C.
`Applicant Admitted Prior Art in the Background of the ’589 Patent . 10
`VI. Technology Overview ................................................................................... 12
`VII. Overview of the Prior Art Used in the Grounds ............................................ 16
`A. Kocis (EX1004) ................................................................................... 16
`B.
`Lee (EX1005) ...................................................................................... 17
`C.
`JESD 21-C (EX1006) .......................................................................... 18
`D.
`Iketani (EX1007) ................................................................................. 20
`VIII. Claim Construction (37 C.F.R. §42.104(B)(3)) ............................................ 21
`
`V.
`
`
`
`i
`
`
`
`

`

`
`
`C.
`
`IX. Level of Ordinary Skill in the Art ................................................................. 21
`X.
`There is a Reasonable Likelihood That at Least One Claim of the ’589
`Patent is Unpatentable .............................................................................................. 22
`A. Ground 1: Claims 1, 9, 11, and 13 are Anticipated by Kocis ............. 22
`B.
`Ground 2: Claims 2, 8, 10, and 12 are Obvious Over Kocis in
`Combination with JESD 21-C ............................................................. 37
`Grounds 3A & 3B: Claims 1 and 11 are Anticipated by or Obvious
`Over Lee .............................................................................................. 46
`D. Ground 4: Claims 1 and 11 are Obvious Over Lee in Combination
`with Iketani .......................................................................................... 59
`Ground 5: Claims 2, 8, 10, and 12 are Obvious Over Lee in
`Combination with JESD 21-C ............................................................. 63
`Ground 6: Claims 2, 8, 10, and 12 are Obvious over Lee in
`Combination with Iketani and JESD 21-C .......................................... 65
`G. Ground 7: Claims 9 and 13 are Obvious Over Lee in Combination
`with Kocis ............................................................................................ 66
`H. Ground 8: Claims 9 and 13 are Obvious Over Lee in Combination
`with Iketani and Kocis ......................................................................... 71
`XI. The Board Should Consider the Petition on the Merits and Not Exercise its
`Discretion to Deny Institution .................................................................................. 72
`A.
`Fintiv (Section 314(a)) ........................................................................ 72
`B.
`Section 325(d) ..................................................................................... 72
`XII. Conclusion ..................................................................................................... 74
`
`
`
`E.
`
`F.
`
`
`
`
`
`ii
`
`
`
`

`

`
`
`EXHIBIT LIST
`
`
`Exhibit
`1001
`
`Description
`U.S. Patent No. 6,157,589 (the “’589 Patent”)
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`1008
`
`1009
`
`1010
`
`1011
`
`1012
`
`1013
`
`U.S. Prosecution History of the ’589 Patent
`
`Declaration of Stephen W. Melvin
`
`U.S. Patent No. 5,559,753 to Kocis entitled “Apparatus and
`Method for Preventing Bus Contention During Power-Up in a
`Computer System With Two or More DRAM Banks” (“Kocis”)
`
`U.S. Patent No. 5,774,402 to Lee entitled “Initialization Circuit for
`a Semiconductor Memory Device” (“Lee”)
`
`JEDEC Standard No. 21-C, entitled “Configurations for Solid
`State Memories,” Compilation of Releases 1 through 7, dated
`January 1997 (“JESD 21-C”)
`
`U.S. Patent No. 5,703,510 to Iketani et al. entitled “Power On
`Reset Circuit For Generating Reset Signal at Power On”
`(“Iketani”)
`
`Prosecution History of EPO Patent Application No. 99 113 048.5
`(Original)
`
`Excerpt of Prosecution History of EPO Patent Application No.
`99 113 048.5 (Original)
`
`Excerpt of Prosecution History of EPO Patent Application No.
`99 113 048.5 (English Translation)
`
`Japanese Patent Publication No. JP 09 106668 A to Samsung
`Electronics Co. Ltd. dated April 22, 1997 (“Tetsuka”)
`
`Declaration of Julie Carson
`
`JEDEC Standard No. 21-C, entitled “Configurations for Solid
`State Memories,” Release 7, dated January 1997
`
`
`
`iii
`
`
`
`

`

`
`
`
`
`
`
`
`Exhibit
`
`1014
`
`Description
`Scheduling Order, Polaris Innovations Limited v. Xilinx, Inc.,
`1:22-cv-00174-RGA, Docket No. 20 (May 31, 2022)
`
`1015
`
`1016
`
`1017
`
`1018
`
`1019
`
`United States District Courts — Federal Court Management
`Statistics, National Judicial Caseload Profile (June 30, 2022),
`available at https://www.uscourts.gov/sites/
`default/files/fcms_na_distprofile0630.2022_0.pdf
`
`Motion Success for Stay Pending IPR before Judge Richard G.
`Andrews in the District of Delaware (Docket Navigator data from
`2020 to 1/20/2023)
`
`Excerpt of Micron Technology, Inc., “DRAM Data Book” (1992)
`
`Excerpt of Samsung Electronics Co., Ltd., “Data Book: DRAM”
`(Dec. 1995)
`
`Samsung Electronics, “4M x 8Bit x 4 Banks Synchronous DRAM”
`Doc. No. KM48S16030, Rev. 2 (March 1998)
`
`
`
`iv
`
`
`
`

`

`
`
`Claim 1
`[1.P]
`
`[1.1]
`
`[1.2]
`
`[1.3]
`
`Claim 2
`[2]
`
`Claim 8
`[8]
`
`LISTING OF CHALLENGED CLAIMS
`
`A dynamic semiconductor memory device of a random access type,
`comprising:
`
`an initialization circuit controlling a switching-on operation and
`supplying a supply voltage stable signal once a supply voltage has been
`stabilized after the switching-on operation,
`
`said initialization circuit having a control circuit for controlling
`operations and an enable circuit receiving the supply voltage stable
`signal and externally applied further command signals,
`
`said enable circuit outputting an enable signal after a predetermined
`proper initialization sequence of the externally applied further
`command signals being identified and the enable signal effecting an
`unlatching of said control circuit.
`
`The semiconductor memory device according to claim 1, wherein the
`externally applied further command signals forming the
`predetermined proper initialization sequence to be identified by said
`enable circuit includes at least one of a preparation command signal
`for word line activation, a refresh command signal, and a loading
`configuration register command signal.
`
`The semiconductor memory device according to claim 1, wherein
`the identification of an initialization sequence that is identified as
`the predetermined proper initialization sequence by said enable
`circuit and generates the enable signal constitutes a command
`sequence conforming to a JEDEC standard.
`
`
`
`v
`
`
`
`

`

`
`
`Claim 9
`[9]
`
`Claim 10
`[10]
`
`The semiconductor memory device according to claim 1,
`wherein said control circuit has output drivers remaining
`latched during the switching-on operation until said enable
`signal is generated by said enable circuit.
`
`The semiconductor memory device according to claim 1,
`wherein the predetermined proper initialization sequence
`includes one of the following chronologically successive
`command sequences:
`a) firstly PRE, secondly ARF, thirdly MRS;
`b) firstly PRE, secondly MRS, thirdly ARF; and
`c) firstly MRS, secondly PRE, or thirdly ARF;
`where,
`PRE=the preparation command signal for word line activation,
`ARF=the refresh command signal, and
`MRS=the loading configuration register command signal.
`
`Claim 11
`[11.P] An improved method for initializing a dynamic semiconductor
`memory device of a random access type via an initialization circuit
`controlling a switching-on operation of the dynamic semiconductor
`memory device and of its circuit components, the improvement which
`comprises:
`
`[11.1]
`
`supplying, via the initialization circuit, a supply voltage stable signal
`once a supply voltage has been stabilized after the switching-on
`operation of the dynamic semiconductor memory device; and
`
`
`
`vi
`
`
`
`

`

`
`
`
`
`
`
`
`[11.2]
`
`supplying, via an enable circuit of the initialization circuit, an enable
`signal, the initialization circuit receiving the supply voltage stable
`signal and further command signals externally applied to the dynamic
`semiconductor memory device, after an identification of a
`predetermined proper initialization sequence of the further command
`signals the enable signal being generated and effecting an unlatching
`of a control circuit provided for a proper operation of the dynamic
`semiconductor memory device.
`
`Claim 12
`[12]
`
`Claim 13
`[13]
`
`The method according to claim 11, which comprises providing at least
`one of a preparation command signal for word line activation, a refresh
`command signal, and a loading configuration register command signal
`as the further command signals.
`
`The method according to claim 11, which comprises maintaining a
`latched condition of output drivers of the dynamic semiconductor
`memory device during the switching-on operation until the enable
`signal is generated by the enable circuit.
`
`vii
`
`
`
`

`

`
`
`I.
`
`INTRODUCTION
`
`Xilinx, Inc. petitions for Inter Partes Review (“IPR”) of claims 1, 2, and 8-
`
`13 of U.S. Patent 6,157,589 (the “’589 Patent”).
`
`II. MANDATORY NOTICES (37 C.F.R. §42.8)
`
`A. Real Parties-In-Interest (37 C.F.R. §42.8(b)(1))
`
`Petitioner Xilinx, Inc. (“Xilinx” or “Petitioner”), Advanced Micro Devices,
`
`Inc. (“AMD”), and ATI Technologies ULC (“ATI”) are the real parties-in-interest.
`
`AMD is the parent of Xilinx and ATI is an indirect, wholly owned subsidiary of
`
`AMD.
`
`B. Related Matters (37 C.F.R. §42.8(b)(2))
`
`Polaris asserted four patents, including the ’589 Patent, against Xilinx in
`
`Polaris Innovations Ltd. v. Xilinx, Inc., CA 1:22-CV-00174-RGA (D. Del.), in a
`
`complaint filed on February 8, 2022 and served on February 22, 2022. Xilinx is
`
`concurrently filing this Petition and IPR petitions for the other three asserted
`
`patents: IPR2023-00513, IPR2023-00514, and IPR2023-00517.
`
`Kingston Technology Company, Inc. (“Kingston”), previously petitioned for
`
`inter partes review of claims 11 and 12 of the ’589 Patent on November 10, 2016,
`
`and the Patent Trial and Appeal Board (“Board”) denied Kingston’s petition.
`
`Kingston Tech. Co., Inc. v. Polaris Innovations Ltd., IPR2017-00238, Paper 9
`
`
`
`1
`
`
`
`

`

`
`
`(PTAB May 2, 2017). Kingston based its petition on different grounds and prior art
`
`than those described herein.
`
`C. Lead and Back-Up Counsel (37 C.F.R. §42.8(b)(3))
`
`Petitioner provides the following designation of counsel.
`
`Lead Counsel
`Brian W. Oaks (Reg. No. 44,981)
`MCDERMOTT WILL & EMERY LLP
`303 Colorado Street, Suite 2200
`Austin, TX 78701
`TEL: 512-726-2574
`EMAIL: boaks@mwe.com
`
`
`
`D.
`
`Service Information
`
`Backup Counsel
`Aashish G. Kapadia (Reg. No. 78,844)
`MCDERMOTT WILL & EMERY LLP
`303 Colorado Street, Suite 2200
`Austin, TX 78701
`TEL: 512-298-6488
`EMAIL: akapadia@mwe.com
`
`Thomas M. DaMario (Reg. No. 77,142)
`MCDERMOTT WILL & EMERY LLP
`444 West Lake Street, Suite 4000
`Chicago, IL 60606
`TEL: 312-984-7527
`EMAIL: tdamario@mwe.com
`
`Please address all correspondence to the address above. Petitioner consents
`
`to electronic service by email at xilinxMWETeam@mwe.com.
`
`III. PAYMENT OF FEES (37 C.F.R. §42.103)
`
`Petitioner authorizes the Office to charge Deposit Account No. 50-0417 for
`
`the petition fee set in 37 C.F.R. §42.15(a) and for any other required fees.
`
`
`
`2
`
`
`
`

`

`
`
`IV. REQUIREMENTS FOR IPR (37 C.F.R. §42.104)
`
`A. Grounds for Standing (37 C.F.R. §42.104(a))
`
`Petitioner certifies that the ’589 Patent is available for IPR and that
`
`Petitioner is not barred or estopped from requesting IPR.
`
`B. Challenge Under 37 C.F.R. §42.104(b) and Relief Requested
`
`Petitioner requests IPR of claims 1, 2, and 8-13 of the ’589 Patent on the
`
`grounds listed below. In support, this petition includes a declaration of Dr. Stephen
`
`Melvin (EX1003).
`
`Ground Claims
`
`Basis for Rejection
`
`1
`
`2
`
`3A/3B
`
`1, 9, 11, 13
`
`§102: Kocis
`
`2, 8, 10, 12
`
`§103: Kocis in combination with JESD 21-C
`
`1, 11
`
`1, 11
`
`§102/§103: Lee
`
`§103: Lee in combination with Iketani
`
`2, 8, 10, 12
`
`§103: Lee in combination with JESD 21-C
`
`2, 8, 10, 12
`
`§103: Lee in combination with Iketani and
`JESD 21-C
`
`4
`
`5
`
`6
`
`7
`
`8
`
`
`
`9, 13
`
`9, 13
`
`
`
`§103: Lee in combination with Kocis
`
`§103: Lee in combination with Iketani and Kocis
`
`3
`
`
`
`

`

`
`
`V.
`
`SUMMARY OF THE ’589 PATENT
`
`A. Brief Description
`
`The ’589 Patent is directed to a Dynamic Semiconductor Random Access
`
`Memory (“DRAM”) device and a method for initializing a DRAM device. EX1001
`
`at 2:7-14. The device and method purportedly solve a problem in the prior art by
`
`providing a way for circuits to be “reliably held in a desired defined state” while
`
`the device is powering on. Id. at 1:22-35. This purported advancement is achieved
`
`by detecting a particular initialization sequence. Id. To detect the initialization
`
`sequence, the device contains an initialization circuit having a control circuit and
`
`an enable circuit. Id. at 2:15-36.
`
`As seen in FIG. 1 of the ’589 Patent (reproduced below), once the
`
`initialization circuit performs a switching-on operation and the internal voltage
`
`regulation and detection circuit 5 detects that the supply voltage at input 6 is
`
`stabilized, detection circuit 5 supplies a supply voltage stable signal (POWERON)
`
`to the enable circuit 9. Id. at 3:42-4:23.
`
`
`
`4
`
`
`
`

`

`
`
`EX1001 (’589 Patent) at FIG. 1
`The enable circuit 9 receives the supply voltage stable signal (POWERON) at
`
`
`
`input 11 and various command signals at input 10. Id. Once the enable circuit
`
`receives the supply voltage stable (POWERON) signal and the various command
`
`signals in a specific sequence, it outputs an enable signal (CHIPREADY) at output
`
`12 which then unlatches the control circuit 13. Id.
`
`FIG. 2 of the ’589 Patent (reproduced below for reference), illustrates an
`
`example of enable circuit 9 in more detail.
`
`
`
`5
`
`
`
`

`

`
`
`EX1001 (’589 Patent) at FIG. 2
`It contains “three bistable multivibrator stages 14, 15 and 16 each having a set
`
`
`
`input S, a reset input R, and also an output Q.” Id. at 4:24-58. The supply voltage
`
`stable signal (POWERON), described above, is applied to the enable circuit at
`
`input 11. Id. Additionally, the command signals described above at input 10 are
`
`shown in more detail. Id. Input 10A receives a preparation command for word line
`
`activation, called PRE or PRECHARGE. Id. Input 10B receives a refresh
`
`command, called ARF or AUTOREFRESH. Id. Input 10C receives a loading
`
`configuration register command, called MRS or MODE-REGISTER-SET. Id. The
`
`enable signal (CHIPREADY) is output at output 12 after “a predetermined
`
`chronological initialization sequence of the command signals PRE, ARF and MRS
`
`and activation of the [supply voltage steady] POWERON signal.” Id.
`
`
`
`6
`
`
`
`

`

`
`
`B.
`
`Summary of the Prosecution
`
`1.
`
`EPO
`
`U.S. Patent Application No. 09/343,431, which issued as the ’589 Patent,
`
`claims priority to a German Patent publication filed on June 30, 1998. See EX1001
`
`at [30]. Original EPO claim 1 has nearly identical scope and subject matter to
`
`Granted US Claim 1
`A dynamic semiconductor memory
`device of a random access type,
`comprising:
`an initialization circuit controlling a
`switching-on operation and supplying a
`supply voltage stable signal once a
`supply voltage has been stabilized after
`the switching-on operation, said
`initialization circuit having a control
`circuit for controlling operations and an
`enable circuit receiving the supply
`voltage stable signal and externally
`applied further command signals, said
`enable circuit outputting an enable
`signal after a predetermined proper
`initialization sequence of the externally
`applied further command signals being
`identified and the enable signal
`effecting an unlatching of said control
`circuit.
`
`granted US claim 1:
`
`Original EPO Claim 1
`A dynamic semiconductor memory
`device of a random-access type
`(DRAM/SDRAM) having an
`initialization circuit which controls the
`switching-on operation of the
`semiconductor memory device and of
`its circuit components and which
`supplies a supply voltage stable signal
`(POWERON) once the supply voltage
`has been stabilized after the switching-
`on of the semiconductor memory
`device,
`characterized in that
`the initialization circuit has an enable
`circuit (9) that receives the supply
`voltage stable signal (POWERON)
`and further command signals (PRE,
`ARF, MRS) externally applied to the
`semiconductor memory device which
`enable circuit supplies an enable
`signal (CHIPREADY) after the
`recognition of a predetermined proper
`initialization sequence of the
`command signals (PRE, ARF, MRS)
`applied to the semiconductor memory
`device which enable signal causes the
`unlatching of a control circuit (13)
`
`
`
`7
`
`
`
`

`

`
`
`Original EPO Claim 1
`provided for the proper operation of
`the semiconductor memory device.
`EX1010 at 12; EX1001 at claim 1.
`
`Granted US Claim 1
`
`During prosecution, the EPO rejected claim 1 based on Japanese Patent
`
`Publication No. JP09106668A dated April 22, 1997 (“Tetsuka,” attached as
`
`EX1011). EX1010 at 7-9. Tetsuka is the Japanese counterpart to U.S. Patent No.
`
`5,774,402 to Lee (“Lee”), which forms the basis for the invalidity Grounds 3-8
`
`discussed herein. Compare EX1011 at Cover, (31) with EX1005 at Cover, [30]
`
`(each claiming priority to Korean Patent Publication 26181/1995); see also
`
`EX1008 at 67 (indicating that Lee is a “Member of the Patent Family” of Tetsuka).
`
`In response to this rejection, the applicant amended claim 1 to incorporate the
`
`subject matter of dependent claim 2, which ultimately led to allowance. EX1010 at
`
`1, 5. Original EPO claim 2, the subject matter of which was required to obtain
`
`allowance, has nearly identical scope and subject matter to granted US claim 2:
`
`Original EPO Claim 2
`A semiconductor memory device
`according to Claim 1,
`characterized in that the command
`signals (PRE, ARF, MRS) externally
`applied to the semiconductor memory
`device in the initialization sequence
`recognized by the enable circuit (9)
`comprise the preparation command for
`word line activation (PRE-CHARGE),
`and/or the refresh command
`(AUTOREFRESH), and/or the load
`
`Granted US Claim 2
`The semiconductor memory device
`according to claim 1, wherein the
`externally applied further command
`signals forming the predetermined
`proper initialization sequence to be
`identified by said enable circuit includes
`at least one of a preparation command
`signal for word line activation, a refresh
`command signal, and a loading
`configuration register command signal.
`
`
`
`8
`
`
`
`

`

`
`
`Original EPO Claim 2
`configuration register command
`(MODE-REGISTER-SET).
`EX1010 at 12; EX1001 at claim 2.
`
`Granted US Claim 2
`
`In submitting the claim amendments identified above, the applicant did not
`
`argue that the Examiner’s rejections based on Tetsuka were improper or incorrect.
`
`See EX1010 at 12.
`
`2.
`
`USPTO
`
`U.S. Patent Application No. 09/343,431, which issued as the ’589 Patent,
`
`was filed on June 30, 1999 with a claim of priority to the German patent
`
`application dated June 30, 1998 referenced above (EX1002 at 31).
`
`As discussed above, during EPO prosecution, the applicant amended original
`
`EPO claim 1 to incorporate the subject matter of original EPO claim 2 in order to
`
`gain allowance. The claims filed in front of the USPTO had the same subject
`
`matter as the original EPO claims (i.e., original US claim 1 had the same subject
`
`matter as original EPO claim 1, without the additional limitations of original EPO
`
`claim 2 that was eventually added into the EPO claim 1 to obtain allowance).
`
`Compare EX1002 at 20 with EX1010 at 12. Despite knowledge that Lee was an
`
`English language family member of Tetsuka, as reported in the European Search
`
`Report (EX1008 at 67), the applicant cited only Tetsuka, without a separate
`
`English translation, to the USPTO. The applicant did not disclose the European
`
`Search Report or the Lee reference to the USPTO. Subsequently, the U.S.
`
`
`
`9
`
`
`
`

`

`
`
`Examiner allowed the claims without any rejections and without any amendment to
`
`claim 1, contrary to the amendment made to obtain allowance in the EPO. EX1002
`
`at 100-01.
`
`As is detailed below in the grounds of unpatentability, the EPO examiner
`
`was correct to not allow claim 1 of the EPO patent, and the US examiner should
`
`also not have allowed the similar US claim 1. The EPO examiner correctly
`
`determined that Tetsuka anticipated EPO claim 1, and the same is true of the
`
`anticipation of US claim 1 by Lee, which has the same content as Tetsuka. The
`
`Grounds below include Lee, and an additional reference, Kocis, that was not before
`
`either examiner.
`
`C. Applicant Admitted Prior Art in the Background of the ’589
`Patent
`
`The admitted prior art in the background section of the ’589 Patent further
`
`confirms that the subject matter of the challenged claims, including the dependent
`
`claims, is not patentable. EX1003, ¶38. For example, the background explains:
`
`In the case of the SDRAM semiconductor memory modules that have
`been disclosed to date, all the control circuits of the component have
`been unlatched only with the POWERON signal. The signal
`POWERON is active if the internal Supply Voltages have reached the
`necessary values that are necessary for the proper operation of the
`component. The module is then in a position to recognize and execute
`instructions.
`
`
`
`10
`
`
`
`

`

`
`
`EX1001 at 1:65-2:5. The Kocis, Lee and Iketani references used in the Grounds of
`
`this Petition confirm that this concept of initializing the memory circuits only after
`
`there is a stable voltage was in the prior art.
`
`Furthermore, the background of the ’589 Patent goes on to describe all the
`
`details of the initialization sequence recited in the challenged independent and
`
`dependent claims:
`
`According to the JEDEC standard for SDRAM semiconductor
`memories, a
`recommended
`initialization
`sequence
`(so-called
`“POWERON-SEQUENCE”) is provided as follows:
`
`a. the application of a supply voltage and a start pulse in order to
`maintain an NOP condition at the inputs of the component;
`
`b. the maintenance of a stable supply voltage of a stable clock
`signal, and of stable NOP input conditions for a minimum time
`period of 200 us;
`
`line activation
`for word
`the preparation command
`c.
`(PRECHARGE) for all the memory banks of the device;
`
`the activation of eight or more refresh commands
`4.
`(AUTOREFRESH); and
`
`5. the activation of a loading configuration register command
`(MODE-REGISTER-SET) for initializing the mode register.
`
`EX1001 at 1:43-61. The Kocis, Lee and JESD 21-C references used in the Grounds
`
`of this Petition confirm that this concept of not initializing the memory circuits
`
`until there is a predetermined initialization sequence of command signals was in
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`the prior art—the exact same sequence of commands disclosed in the ’589 Patent
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`background and recited in the challenged dependent claims was disclosed in
`
`JESD 21-C.
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`VI. TECHNOLOGY OVERVIEW
`
`The technology of the ’589 Patent generally relates to semiconductor
`
`memory devices, also referred to as random access memory (“RAM”). As of the
`
`filing date of the ’589 Patent, there were multiple types of RAM available. Such
`
`variants include Dynamic RAM (“DRAM”) and Synchronous Dynamic RAM
`
`(“SDRAM”). EX1003, ¶47.
`
`DRAM chips contain one or more memory arrays, which are rectangular
`
`grids of storage cells, organized into rows and columns, each cell holding one bit
`
`of data. A depiction of a DRAM chip’s memory array with the rows and columns
`
`is reproduced below. EX1003, ¶¶48-49.
`
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`12
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`DRAM is characterized as “dynamic” because the values held in the
`
`memory array’s storage cells are represented by electric charges that slowly leak
`
`out of the circuit over time. In order to maintain the data stored in dynamic
`
`memory cells, they must be periodically “refreshed” by reading the cell’s value and
`
`restoring its charge. Another aspect of dynamic memory is that before a read
`
`operation can be performed, a “precharge” operation is necessary. This affects the
`
`timing of how reads and writes are processed in a dynamic memory device.
`
`EX1003, ¶¶50-51.
`
`In typical systems involving DRAM devices, there is a dedicated address
`
`bus that carries row and column addresses to the DRAMs and a dedicated data bus
`
`that communicates read and write data between the CPU and the DRAMs. Control
`
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`
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`signals comprise the row and column strobes, output enables, clocks, clock
`
`enables, chip enables and other related signals. These signals are typically
`
`controlled by a memory controller, that is either integrated with or separate from
`
`the CPU, and connect to every DRAM in the system. EX1003, ¶52.
`
`Input signals labeled “CAS” and “RAS” (or sometimes “CASB” and
`
`“RASB,” in which the “B” refers to “bar” which means that the signals are low
`
`active) are specific to DRAM type devices. Column Address Strobe (CAS) and
`
`Row Address Strobe (RAS) signals have to do with the multiplexing of column
`
`and row lines on the same address pins. Additional control signals include, for
`
`example, Chip Select (CS), which enables the memory chip’s command decoder,
`
`and Write Enable (WE), which determines whether an operation is a read or a
`
`write. Additionally, DRAM may have special function signals, such as DSF, which
`
`enables certain special operational functions when active. These various input
`
`signals are used to perform specific commands by way of a command decoder
`
`within the DRAM device, which accepts the various signals and interprets the
`
`sequence as a particular command. Depending on the combination of these input
`
`signals sent from the memory controller to the DRAM device, a different
`
`command is identified and performed. For reference, a functional block diagram of
`
`a 1992 Micron DRAM device is provided below (EX1017 at 1-88). EX1003, ¶53.
`
`
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`14
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`Similarly, a functional block diagram of a 1996 Samsung DRAM device is
`
`provided below (EX1018 at 217).
`
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`15
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`

`
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`Similar to the prior art used in the grounds below, both of these DRAM devices
`
`required a power-on sequence that utilized a initialization sequence of control
`
`signals. See EX1017 at 1-79; EX1018 at 224 n.1.
`
`The original DRAM devices were asynchronous, meaning that they did not
`
`rely on an external clock signal. Subsequently, synchronous DRAM devices
`
`(SDRAMs) were introduced in which an external clock signal is supplied by the
`
`memory controller and signals are sampled based on the clock signal. The primary
`
`benefit of SDRAM is that it allows faster operation due to increased predictability
`
`of event timing. Despite some changes to control signal nomenclature and other
`
`functionality specific to the use of external clock signals, the underlying
`
`architecture of SDRAM is essentially the same as asynchronous DRAM. EX1003,
`
`¶54.
`
`VII. OVERVIEW OF THE PRIOR ART USED IN THE GROUNDS
`
`A. Kocis (EX1004)
`
`Kocis was filed on January 25, 1995 and was issued on September 24, 1996.
`
`EX1004 at [22], [45]. Kocis discloses a DRAM circuit with circuitry for disabling
`
`data output drivers to prevent bus contention during system power-up. EX1004 at
`
`Abst. The circuitry disclosed in Kocis includes a counter for counting a
`
`initialization sequence of RAS signals and a circuit for detecting that a supply
`
`voltage has achieved a proper voltage threshold. EX1004 at Abst. The circuitry in
`
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`
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`Kocis disables output drivers and an associated control circuit until a certain
`
`number of RAS signals are received and the supply voltage has met the necessary
`
`threshold. EX1004 at Abst.
`
`Kocis qualifies as prior art under at least §§102(a), (b), and (e) because it
`
`was filed, published, and issued before the earliest possible priority date (June 30
`
`1998, hereinafter the “Priority Date”) of the ’589 patent.
`
`B.
`
`Lee (EX1005)
`
`Lee was filed on August 23, 1996 and claims priority to Korean Document
`
`No. 26181/1995 dated August 23, 1995. EX1005 at [22], [30]. Lee explains that as
`
`semiconductor memory devices become more complicated, they require
`
`initialization circuits for resetting the various functional circuits within the chip.
`
`EX1005 at 1:18-27. Traditionally, power-on reset circuits were provided to ensure
`
`stable power sources. Id. As with Kocis, Lee takes this one step further and seeks
`
`to additionally provide an initialization circuit for semiconductor memory that is
`
`based on external logic signals. EX1005 at 2:21-23.
`
`In particular, Lee describes an initialization circuit for a semiconductor
`
`memory device which includes an initialization signal generator that generates an
`
`initialization signal in response to a specific sequence of reset control signals.
`
`EX1005 at Abst. The initialization signal is activated when three reset control
`
`
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`17
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`

`
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`signals are activated in the proper sequence and is deactivated when one of the
`
`control signals is deactivated. Id.
`
`Lee contains both a first and second initialization signal generator. The first
`
`initialization circuit generator is triggered based on the correct sequence of control
`
`signals DSF, RASB, and CASB. EX1005 at 3:9-22. The second initialization
`
`circuit generator is triggered based on proper powerup of the power source. Id.
`
`The resulting initialization signals are then sent to Lee’s transfer unit which, based
`
`on the initialization signals, generates a reset signal ϕRST sent “to a circuit to be
`
`initialized within the chip.” EX1005 at 4:14-24, 4:59-5:4.
`
`Lee qualifies as prior art under at least §102(e) because it was filed before
`
`the Priority Date of the ’589 Patent (and then subsequently was issued as a granted
`
`patent).
`
`C.
`
`JESD 21-C (EX1006)
`
`JESD 21-C is a “Memory Device Standard” for “establish[ing] pin
`
`assignments, power supply potentials, and package configurations and dimensions
`
`for a series of memory devices.” EX1006 at page 3-1. Furthermore, “In some
`
`cases, special timing diagrams are included, where they are essential to the
`
`implementation and use of the standards.” Id. In particular, JESD 21-C discloses
`
`the exact initialization sequence of control signals for power-up that is recited in
`
`the claims.
`
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`The JESD 21-C Standard is and was a well-known industry standard
`
`compiled and published by the Joint Electron Device Engineering Council
`
`(“JEDEC”). EX1003, ¶¶91-93 (explaining that a POSITA would have been well-
`
`aware of JEDEC memory standards like JESD 21-C and would have been aware of
`
`how to access those standards, what they disclose, and how to design a memory
`
`device according to the standards); see also, e.g., Samsung Elecs. Am., Inc. v.
`
`Goodman, IPR2017-02021, Paper 19 at 18-19 (PTAB Oct. 29, 2019) (finding that
`
`JEDEC’s JESD 21-C is a printed p