KM48S16030
`
`4M x 8Bit x 4 Banks Synchronous DRAM
`
`FEATURES
`• JEDEC standard 3.3V power supply
`• LVTTL compatible with multiplexed address
`• Four banks operation
`• MRS cycle with address key programs
`-. CAS Latency (2 & 3)
`-. Burst Length (1, 2, 4, 8 & full page)
`-. Burst Type (Sequential & Interleave)
`• All inputs are sampled at the positive going edge of the system
`clock.
`• Burst Read Single-bit Write operation
`• DQM for masking
`• Auto & self refresh
`• 64ms refresh period (4K cycle)
`
`FUNCTIONAL BLOCK DIAGRAM
`
`Preliminary
`CMOS SDRAM
`
`GENERAL DESCRIPTION
` The KM48S16030 is 134,217,728 bits synchronous high data
`rate Dynamic RAM organized as 4 x 4,194,304 words by 8 bits,
`fabricated with SAMSUNG¢s high performance CMOS technol-
`ogy. Synchronous design allows precise cycle control with the
`use of system clock I/O transactions are possible on every clcok
`cycle. Range of operating frequencies, programmable burst
`length and programmable latencies allow the same device to be
`useful for a variety of high bandwidth, high performance mem-
`ory system applications.
`
`ORDERING INFORMATION
`
`Part NO.
` KM48S16030T-G/F8
` KM48S16030T-G/FH
` KM48S16030T-G/FL
` KM48S16030T-G/F10
`
`MAX Freq.
`125MHz
`100MHz
`100MHz
`100MHz
`
`Interface Package
`
`LVTTL
`
`54pin
`TSOP(II)
`
`LWE
`
`LDQM
`
`DQi
`
`I/O Control
`
`Output Buffer
`
`Data Input Register
`
`Sense AMP
`
`4M x 8
`
`4M x 8
`
`4M x 8
`
`4M x 8
`
`Column Decoder
`
`Latency & Burst Length
`
`Programming Register
`
`Row Decoder
`
`Col. Buffer
`
`Bank Select
`
`Row Buffer
`
`Refresh Counter
`
`LCBR
`
`LRAS
`
`Address Register
`
`CLK
`
`ADD
`
`LCKE
`
`LRAS
`
`LCBR
`
`LWE
`
`LCAS
`
`LWCBR
`
`LDQM
`
`Timing Register
`
`CLK
`
`CKE
`
`CS
`
`RAS
`
`CAS
`
`WE
`
`DQM
`
`*
`
`Samsung Electronics reserves the right to
`change products or specification without
`notice.
`
` REV. 2 Mar. '98
`
`XILINX EXHIBIT 1019
`Page 1
`
`

`

`KM48S16030
`
`PIN CONFIGURATION (TOP VIEW)
`
`Preliminary
`CMOS SDRAM
`
`54PIN TSOP (II)
`(400mil x 875mil)
`(0.8 mm PIN PITCH)
`
`54
`53
`52
`51
`50
`49
`48
`47
`46
`45
`44
`43
`42
`41
`40
`39
`38
`37
`36
`35
`34
`33
`32
`31
`30
`29
`28
`
`VSS
`DQ7
`VSSQ
`N.C
`DQ6
`VDDQ
`N.C
`DQ5
`VSSQ
`N.C
`DQ4
`VDDQ
`N.C
`VSS
`N.C/RFU
`DQM
`CLK
`CKE
`N.C
`A11
`A9
`A8
`A7
`A6
`A5
`A4
`VSS
`
`1234567891
`
`0
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`27
`
`VDD
`DQ0
`VDDQ
`N.C
`DQ1
`VSSQ
`N.C
`DQ2
`VDDQ
`N.C
`DQ3
`VSSQ
`N.C
`VDD
`N.C
`WE
`CAS
`RAS
`CS
`BA0
`BA1
`A10/AP
`A0
`A1
`A2
`A3
`VDD
`
`
`
`PIN FUNCTION DESCRIPTION
`
`PIN
`CLK
`
`CS
`
`NAME
`System Clock
`
`Chip Select
`
`CKE
`
`Clock Enable
`
`A0 ~ A11
`
`Address
`
`BA0 ~ BA1
`
`Bank Select Address
`
`INPUT FUNCTION
`Active on the positive going edge to sample all inputs.
`Disables or enables device operation by masking or enabling all inputs except
`CLK, CKE and DQM
`
`Masks system clock to freeze operation from the next clock cycle.
`CKE should be enabled at least one cycle prior to new command.
`Disable input buffers for power down in standby.
`
`Row / column addresses are multiplexed on the same pins.
`Row address : RA0 ~ RA11, column address : CA0 ~ CA9
`
`Selects bank to be activated during row address latch time.
`Selects bank for read/write during column address latch time.
`
`RAS
`
`CAS
`
`WE
`
`Row Address Strobe
`
`Latches row addresses on the positive going edge of the CLK with RAS low.
`Enables row access & precharge.
`
`Column Address Strobe
`
`Latches column addresses on the positive going edge of the CLK with CAS low.
`Enables column access.
`
`Write Enable
`
`Enables write operation and row precharge.
`Latches data in starting from CAS, WE active.
`
`DQM
`
`Data Input/Output Mask
`
`Makes data output Hi-Z, tSHZ after the clock and masks the output.
`Blocks data input when DQM active.
`
`DQ0 ~ 7
`VDD/VSS
`
`Data Input/Output
`Power Supply/Ground
`
`VDDQ/VSSQ
`
`Data Output Power/Ground
`
`Data inputs/outputs are multiplexed on the same pins.
`Power and ground for the input buffers and the core logic.
`Isolated power supply and ground for the output buffers to provide improved noise
`immunity.
`
`N.C/RFU
`
`No Connection/
`Reserved for Future Use
`
`This pin is recommended to be left No Connection on the device.
`
` REV. 2 Mar. '98
`
`XILINX EXHIBIT 1019
`Page 2
`
`

`

`KM48S16030
`
`ABSOLUTE MAXIMUM RATINGS
`
` Parameter
`
`Voltage on any pin relative to Vss
`
`Voltage on VDD supply relative to Vss
`Storage temperature
`
`Power dissipation
`
`Short circuit current
`
`Symbol
`
`VIN, VOUT
`VDD, VDDQ
`TSTG
`PD
`IOS
`
`Preliminary
`CMOS SDRAM
`
`Value
`
`-1.0 ~ 4.6
`
`-1.0 ~ 4.6
`
`-55 ~ +150
`
`1
`
`50
`
`Unit
`
`V
`
`V
`(cid:176) C
`W
`
`mA
`
`Note :
`
`Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
`Functional operation should be restricted to recommended operating condition.
`Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
`
`DC OPERATING CONDITIONS
`Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70(cid:176) C)
` Parameter
`Symbol
`Min
`Typ
`
`Max
`
`3.6
`
`VDDQ+0.3
`0.8
`
`-
`
`0.4
`
`5
`
`5
`
`Unit
`
`Note
`
`V
`
`V
`
`V
`
`V
`
`V
`
`uA
`
`uA
`
`1
`
`2
`
`IOH = -2mA
`IOL = 2mA
`3
`
`3,4
`
`Supply voltage
`
`Input logic high votlage
`
`Input logic low voltage
`
`Output logic high voltage
`
`Output logic low voltage
`
`Input leakage current(Inputs)
`
`Input leakage current (I/O pins)
`
`VDD, VDDQ
`VIH
`VIL
`VOH
`VOL
`IIL
`IIL
`
`3.0
`
`3.3
`
`2.0
`
`-0.3
`
`2.4
`
`-
`
`-5
`
`-5
`
`3.0
`
`0
`
`-
`
`-
`
`-
`
`-
`
`
`
`Note :
`
`1. VIH (max) = 5.6V AC.The overshoot voltage duration is £ 3ns.
`2. VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.
`3. Any input 0V £ V IN £ VDDQ ,
` Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.
` VDDQ.
`4. Dout is disabled, 0V £ VOUT
`
`CAPACITANCE (VDD = 3.3V, TA = 23(cid:176)C, f = 1MHz, V REF =1.4V – 200 mV)
`Parameter
`Symbol
`Min
`
`Clock
`
`RAS, CAS, WE, CS, CKE, DQM
`
`Address
`
`DQ0 ~ DQ3
`
`CCLK
`CIN
`CADD
`COUT
`
`2.5
`
`2.5
`
`2.5
`
`4
`
`Max
`
`4
`
`5
`
`5
`
`6.5
`
`Unit
`
`pF
`
`pF
`
`pF
`
`pF
`
` REV. 2 Mar. '98
`
`XILINX EXHIBIT 1019
`Page 3
`
`£
`

`

`KM48S16030
`
`DC CHARACTERISTICS
`(Recommended operating condition unless otherwise noted, TA = 0 to 70(cid:176)C)
`
`Parameter
`
`Symbol
`
`Test Condition
`
`Preliminary
`CMOS SDRAM
`
`CAS
`Latency
`
`Version
`
`-8
`
`-H
`
`-L
`
`-10
`
`Unit
`
`Note
`
` Burst Length =1
` tRC ‡ tRC (min)
` IOL = 0 mA
`
` VIL(max), tCC = 15ns
`CKE £
`CKE & CLK £
` VIL(max), tCC = ¥
`CKE ‡ V IH(min),CS ‡ V IH(min),tCC=15ns
`Input signals are changed one time during
`30ns
` VIL(max), tCC = ¥
`CKE ‡ V IH(min), CLK £
`Input signals are stable
`
` VIL(max), tCC = 15ns
`CKE £
`CKE & CLK £
` VIL(max), tCC = ¥
`CKE ‡ V IH(min), CS ‡ V IH(min), tCC = 15ns
`Input signals are changed one time during
`30ns.
` VIL(max), tCC = ¥
`CKE ‡ V IH(min), CLK £
`Input signals are stable
`
`Operating Current
`(One Bank Active)
`
`Precharge Standby Current in
`power-down mode
`
`Precharge Standby Current
`in non power-down mode
`
`Active Standby Current
`in power-down mode
`
`Active Standby Current
`in non power-down mode
`(One Bank Active)
`
`Operating Current
`(Burst Mode)
`
`Refresh Current
`
`Self Refresh Current
`
`ICC1
`
`ICC2P
`ICC2PS
`
`ICC2N
`
`ICC2NS
`
`ICC3P
`ICC3PS
`
`ICC3N
`
`ICC3NS
`
`ICC4
`
`ICC5
`
`ICC6
`
`Note :
`
`1. Measured with outputs open.
`2. Refresh period is 64ms.
`3. KM48S16030T-G**
`4. KM48S16030T-F**
`
`
`
` IOL = 0 mA
` Page Burst
` tCCD = 2CLKs
`
`tRC ‡ tRC (min)
`
`CKE £
`
` 0.2V
`
`3
`
`2
`
`150
`
`115
`
`125
`
`115
`
`125
`
`125
`
`200
`
`125
`
`115
`
`165
`
`1
`
`600
`
`120
`
`110
`
`110
`
`105
`
`mA
`
`1
`
`1
`
`1
`
`15
`
`7
`
`5
`
`5
`
`30
`
`20
`
`mA
`
`mA
`
`mA
`
`mA
`
`mA
`
`mA
`
`mA
`
`mA
`
`uA
`
`1
`
`2
`
`3
`
`4
`
` REV. 2 Mar. '98
`
`XILINX EXHIBIT 1019
`Page 4
`
`

`

`KM48S16030
`
`AC OPERATING TEST CONDITIONS (VDD = 3.3V – 0.3V , TA = 0 to 70(cid:176)C)
` Parameter
`Value
`
`Input levels (Vih/Vil)
`
`Input timing measurement reference level
`
`Input rise and fall time
`
`Output timing measurement reference level
`
`Output load condition
`
`2.4 / 0.4
`
`1.4
`
`tr / tf = 1 / 1
`
`1.4
`
`See Fig. 2
`
`3.3V
`
`1200W
`
`50pF
`
`Output
`
`870W
`
`VOH (DC) = 2.4V, IOH = -2mA
`VOL (DC) = 0.4V, IOL = 2mA
`
`Output
`
`Z0=50W
`
`
`
`Preliminary
`CMOS SDRAM
`
`Unit
`
`V
`
`V
`
`ns
`
`V
`
`Vtt=1.4V
`
`50W
`
`50pF
`
`(Fig. 1) DC Output Load Circuit
`
`(Fig. 2) AC Output Load Circuit
`
`OPERATING AC PARAMETER
`(AC operating conditions unless otherwise noted)
`
`Parameter
`
`Symbol
`
`Row active to row active delay
`
`-8
`
`16
`
`Version
`
`-H
`
`20
`
`20
`
`-L
`
`20
`
`20
`
`-10
`
`20
`
`24
`
`Unit
`
`Note
`
`ns
`
`ns
`
`1
`
`1
`
`RAS to CAS delay
`
`Row precharge time
`
`Row active time
`
`Row cycle time
`
`Last data in to row precharge
`
`Last data in to new col. address delay
`
`Last data in to burst stop
`
`Col. address to col. address delay
`
` tRRD(min)
` tRCD(min)
` tRP(min)
` tRAS(min)
` tRAS(max)
` tRC(min)
` tRDL(min)
` tCDL(min)
` tBDL(min)
` tCCD(min)
`CAS latency=3
`
`Note :
`
`Number of valid
`output data
`
`CAS latency=2
`
`1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
` and then rounding off to the next higher integer.
`2. Minimum delay is required to complete write.
`3. All parts allow every cycle column address change.
`4. In case of row precharge interrupt, auto precharge and read burst stop.
`
` REV. 2 Mar. '98
`
`20
`
`20
`
`48
`
`68
`
`8
`
`20
`
`50
`
`70
`
`10
`
`20
`
`50
`
`70
`
`10
`
`24
`
`50
`
`80
`
`12
`
`100
`
`1
`
`1
`
`1
`
`2
`
`1
`
`ns
`
`ns
`
`us
`
`ns
`
`ns
`
`CLK
`
`CLK
`
`CLK
`
`ea
`
`1
`
`1
`
`1
`
`2
`
`2
`
`2
`
`3
`
`4
`
`XILINX EXHIBIT 1019
`Page 5
`
`

`

`KM48S16030
`
`Preliminary
`CMOS SDRAM
`
`AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
`
`Parameter
`
`Symbol
`
`-8
`
`-H
`
`-L
`
`-10
`
`Min
`
`Max
`
`Min
`
`Max
`
`Min
`
`Max
`
`Min
`
`Max
`
`Unit Note
`
`CLK cycle time
`
`CLK to valid
`output delay
`
`Output data
`hold time
`
`CAS latency=3
`
`CAS latency=2
`
`CAS latency=3
`
`CAS latency=2
`
`CAS latency=3
`
`tCC
`
`tSAC
`
`tOH
`
`8
`
`12
`
`3
`
`1000
`
`6
`
`6
`
`10
`
`10
`
`3
`
`1000
`
`6
`
`6
`
`10
`
`12
`
`3
`
`1000
`
`6
`
`7
`
`10
`
`13
`
`3
`
`1000
`
`ns
`
`1
`
`7
`
`7
`
`ns
`
`1, 2
`
`ns
`
`2
`
`CAS latency=2
`
`CLK high pulse width
`
`CLK low pulse width
`
`Input setup time
`
`Input hold time
`
`CLK to output in Low-Z
`
`CLK to output
`in Hi-Z
`
`CAS latency=3
`
`CAS latency=2
`
`tCH
`tCL
`tSS
`tSH
`tSLZ
`
`tSHZ
`
`3
`
`3
`
`3
`
`2
`
`1
`
`1
`
`3
`
`3
`
`3
`
`2
`
`1
`
`1
`
`3
`
`3
`
`3
`
`2
`
`1
`
`1
`
`3
`
`3.5
`
`3.5
`
`2.5
`
`1.5
`
`1
`
`6
`
`6
`
`6
`
`6
`
`6
`
`7
`
`7
`
`7
`
`3
`
`3
`
`3
`
`3
`
`2
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`ns
`
`Note :
`
`1. Parameters depend on programmed CAS latency.
`2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
`3. Assumed input rise and fall time (tr & tf)=1ns.
` If tr & tf is longer than 1ns, transient time compensation should be considered,
` i.e., [(tr + tf)/2-1]ns should be added to the parameter.
`
`
`
` REV. 2 Mar. '98
`
`XILINX EXHIBIT 1019
`Page 6
`
`

`

`Preliminary
`CMOS SDRAM
`
`66Mhz and 100Mhz Pull-Up
`
`0
`
`0.5
`
`1
`
`1.5
`
`2
`
`2.5
`
`3
`
`3.5
`
`0
`
`-100
`
`-200
`
`-300
`
`ma
`
`-400
`
`-500
`
`-600
`
`66Mhz
`min
`I(mA)
`
`-0.7
`-7.5
`-13.3
`-27.5
`-35.5
`-41.1
`-47.9
`-52.4
`-72.5
`-93
`
`KM48S16030
`
`IBIS Specification
`
`IOH Characteristics(Pull-up)
`Voltage
`100Mhz
`100Mhz
`min
`max
`I(mA)
`I(mA)
`-2.4
`-27.3
`-74.1
`-129.2
`-153.3
`-197
`-226.2
`-248
`-269.7
`-284.3
`-344.5
`-502.4
`
`(V)
`3.45
`3.3
`3
`2.6
`2.4
`2
`1.8
`1.65
`1.5
`1.4
`1
`0
`
`0
`-21.1
`-34.1
`-58.7
`-67.3
`-73
`-77.9
`-80.8
`-88.6
`-93
`
`250
`
`200
`
`150
`
`100
`
`50
`
`0
`
`0
`
`voltage
`
`Ioh min(100Mhz)
`Ioh min(66Mhz)
`Ioh max(66 and 100Mhz)
`
`66Mhz and 100Mhz Pull-Down
`
`0.5
`
`1
`
`1.5
`
`2
`
`2.5
`
`3
`
`3.5
`
`voltage
`
`Iol min(100Mhz)
`Iol min(66Mhz)
`Iol max(100Mhz)
`
` REV. 2 Mar. '98
`
`
`
`ma
`
`IOL Characteristics(Pull-Down)
`100Mhz
`100Mhz
`Voltage
`min
`max
`(V)
`I(mA)
`I(mA)
`0
`0.0
`0.0
`0.4
`27.5
`70.2
`0.65
`41.8
`107.5
`0.85
`51.6
`133.8
`1
`58.0
`151.2
`1.4
`70.7
`187.7
`1.5
`72.9
`194.4
`1.65
`75.4
`202.5
`1.8
`77.0
`208.6
`1.95
`77.6
`212.0
`3
`80.3
`219.6
`3.45
`81.4
`222.6
`
`66Mhz
`min
`I(mA)
`0.0
`17.7
`26.9
`33.3
`37.6
`46.6
`48.0
`49.5
`50.7
`51.5
`54.2
`54.9
`
`XILINX EXHIBIT 1019
`Page 7
`
`

`

`Preliminary
`CMOS SDRAM
`
`Minimum VDD Clamp Current
`(referenced to VDD)
`
`1
`
`2
`
`Voltage
`
`I(ma)
`
`Minimum VSS Clamp Current
`
`-2
`
`-1
`
`3
`
`0
`
`Voltage
`
`I(ma)
`
` REV. 2 Mar. '98
`
`20
`
`15
`
`10
`
`5
`
`0
`
`0
`
`I(ma)
`
`KM48S16030
`
`VDD Clamp @CLK,CKE, CS,DQM & DQ
`VDD
`I(mA)
`0.0V
`0.0mA
`0.2V
`0.0mA
`0.4V
`0.0mA
`0.6V
`0.0mA
`0.7V
`0.0mA
`0.8V
`0.0mA
`0.9V
`0.0mA
`1.0V
`0.23mA
`1.2V
`1.34mA
`1.4V
`3.02mA
`1.6V
`5.06mA
`1.8V
`7.35mA
`2.0V
`9.83mA
`2.2V
`12.48mA
`2.4V
`15.30mA
`2.6V
`18.31mA
`
`-3
`
`0
`
`I(ma)
`
`VSS Clamp @CLK,CKE, CS,DQM & DQ
`VSS
`I(mA)
`-2.6
`-57.23mA
`-2.4
`-45.77mA
`-2.2
`-38.26mA
`-2.0
`-31.22mA
`-1.8
`-24.58mA
`-1.6
`-18.37mA
`-1.4
`-12.56mA
`-1.2
`-7.57mA
`-1.0
`-3.37mA
`-0.9
`-1.75mA
`-0.8
`-0.58mA
`-0.7
`-0.05mA
`-0.6
`0.0mA
`-0.4
`0.0mA
`-0.2
`0.0mA
` 0.0
`0.0mA
`
`
`
`-10
`
`-20
`
`-30
`
`-40
`
`-50
`
`-60
`
`XILINX EXHIBIT 1019
`Page 8
`
`

`

`KM48S16030
`
`FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE
`
`Preliminary
`CMOS SDRAM
`
`(Unit : number of clock)
`
`KM48S16030T-8
`
`Frequency
`
`125MHz (8.0ns)
`
`100MHz (10.0ns)
`
`83MHz (12.0ns)
`
`75MHz (13.0ns)
`
`CAS
`Latency
`
`tRC
`68ns
`
`tRAS
`48ns
`
`tRP
`20ns
`
`tRRD
`16ns
`
`tRCD
`20ns
`
`tCCD
`8ns
`
`tCDL
`8ns
`
`tRDL
`8ns
`
`3
`
`3
`
`2
`
`2
`
`2
`
`9
`
`7
`
`6
`
`6
`
`5
`
`6
`
`5
`
`4
`
`4
`
`4
`
`3
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`3
`
`2
`
`2
`
`2
`
`2
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`66MHz (15.0ns)
`
`KM48S16030T-H
`
`Frequency
`
`100MHz (10.0ns)
`
`83MHz (12.0ns)
`
`75MHz (13.0ns)
`
`66MHz (15.0ns)
`
`60MHz (16.7ns)
`
`(Unit : number of clock)
`
`CAS
`Latency
`
`tRC
`70ns
`
`tRAS
`50ns
`
`tRP
`20ns
`
`tRRD
`20ns
`
`tRCD
`20ns
`
`tCCD
`10ns
`
`tCDL
`10ns
`
`tRDL
`10ns
`
`2
`
`2
`
`2
`
`2
`
`2
`
`7
`
`6
`
`6
`
`5
`
`5
`
`5
`
`5
`
`4
`
`4
`
`3
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`KM48S16030T-L
`
`Frequency
`
`100MHz (10.0ns)
`
`83MHz (12.0ns)
`
`75MHz (13.0ns)
`
`66MHz (15.0ns)
`
`60MHz (16.7ns)
`
`(Unit : number of clock)
`
`CAS
`Latency
`
`tRC
`70ns
`
`tRAS
`50ns
`
`tRP
`20ns
`
`tRRD
`20ns
`
`tRCD
`20ns
`
`tCCD
`10ns
`
`tCDL
`10ns
`
`tRDL
`10ns
`
`3
`
`2
`
`2
`
`2
`
`2
`
`7
`
`6
`
`6
`
`5
`
`5
`
`5
`
`5
`
`4
`
`4
`
`3
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`(Unit : number of clock)
`
`
`
`CAS
`Latency
`
`tRC
`80ns
`
`tRAS
`50ns
`
`tRP
`24ns
`
`tRRD
`20ns
`
`tRCD
`24ns
`
`tCCD
`10ns
`
`tCDL
`10ns
`
`tRDL
`12ns
`
`3
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`2
`
`3
`
`2
`
`2
`
`2
`
`2
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`2
`
`1
`
`1
`
`1
`
`1
`
` REV. 2 Mar. '98
`
`KM48S16030T-10
`
`Frequency
`
`100MHz (10.0ns)
`
`83MHz (12.0ns)
`
`75MHz (13.0ns)
`
`66MHz (15.0ns)
`
`60MHz (16.7ns)
`
`3
`
`3
`
`2
`
`2
`
`2
`
`8
`
`7
`
`7
`
`6
`
`5
`
`5
`
`5
`
`4
`
`4
`
`3
`
`XILINX EXHIBIT 1019
`Page 9
`
`

`

`KM48S16030
`
`SIMPLIFIED TRUTH TABLE
`
`Preliminary
`CMOS SDRAM
`
`COMMAND
`
`CKEn-1
`
`CKEn
`
`CS
`
`RAS
`
`CAS WE
`
`DQM BA0,1
`
`A10/AP
`
`Register
`
`Mode Register Set
`
`Refresh
`
`Auto Refresh
`
`Self
`Refresh
`
`Entry
`
`Exit
`
`Bank Active & Row Addr.
`
`Read &
`Column Address
`
`Write &
`Column Address
`
`Auto Precharge Disable
`
`Auto Precharge Enable
`
`Auto Precharge Disable
`
`H
`
`H
`
`L
`
`H
`
`H
`
`H
`
`X
`
`H
`
`L
`
`H
`
`X
`
`X
`
`X
`
`L
`
`L
`
`L
`
`H
`
`L
`
`L
`
`L
`
`L
`
`L
`
`H
`
`X
`
`L
`
`H
`
`H
`
`L
`
`L
`
`H
`
`X
`
`H
`
`L
`
`L
`
`L
`
`H
`
`H
`
`X
`
`H
`
`H
`
`L
`
`X
`
`X
`
`X
`
`X
`
`X
`
`X
`
`OP CODE
`
`X
`
`X
`
`V
`
`V
`
`V
`
`Row Address
`
`L
`
`H
`
`L
`
`Column
`Address
`(A0~A9)
`
`Column
`Address
`(A0~A9)
`
` A11,
`A9 ~ A0
`
`Note
`
`1, 2
`
`3
`
`3
`
`3
`
`3
`
`4
`
`4, 5
`
`4
`
`Auto Precharge Enable
`
`Burst Stop
`
`Precharge
`
`Bank Selection
`
`All Banks
`
`Clock Suspend or
`Active Power Down
`
`Precharge Power Down Mode
`
`DQM
`
`Entry
`
`Exit
`
`Entry
`
`Exit
`
`No Operation Command
`
`
`
`H
`
`H
`
`H
`
`X
`
`X
`
`L
`
`H
`
`L
`
`H
`
`L
`
`H
`
`L
`
`H
`
`H
`
`X
`
`L
`
`L
`
`H
`
`H
`
`L
`
`X
`
`L
`
`X
`
`H
`
`L
`
`H
`
`L
`
`H
`
`V
`
`X
`
`X
`
`H
`
`X
`
`V
`X
`
`X
`
`H
`
`H
`
`X
`
`V
`
`X
`
`X
`
`H
`
`X
`
`V
`
`X
`
`L
`
`L
`
`X
`
`V
`
`X
`
`X
`
`H
`
`X
`
`V
`
`X
`
`V
`
`X
`
`X
`
`X
`
`X
`
`X
`
`X
`
`X
`
`V
`
`H
`
`L
`
`H
`
`X
`
`X
`
`X
`
`X
`
`4, 5
`
`6
`
`X
`
`7
`
`X
`
`X
`
` REV. 2 Mar. '98
`
`L
`H
`H
`H
` (V=Valid, X=Don¢t Care, H=Logic High, L=Logic Low)
`Note :
`1. OP Code : Operand Code
` A0 ~ A11 & BA0 ~ BA1 : Program keys. (@MRS)
`2. MRS can be issued only at all banks precharge state.
` A new command can be issued after 2 CLK cycles of MRS.
`3. Auto refresh functions are as same as CBR refresh of DRAM.
` The automatical precharge without row precharge command is meant by "Auto".
` Auto/self refresh can be issued only at all banks precharge state.
`4. BA0 ~ BA1 : Bank select addresses.
` If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
` If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
` If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
` If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
` If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
`5. During burst read or write with auto precharge, new read/write command can not be issued.
` Another bank read/write command can be issued after the end of burst.
` New row active of the assoiated bank can be issued at tRP after the end of burst.
`6. Burst stop command is valid at every burst length.
`7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
` but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
`
`XILINX EXHIBIT 1019
`Page 10
`
`