I, Julie Carlson, declare as follows:
`
`1.
`
`I have personal knowledge of the facts set forth herein, and if called to
`
`testify, I could and would competently testify to the same.
`
`2.
`
`I have been involved in semiconductor standardization and publication
`
`services for over twenty years. During this time, I have worked at JEDEC, a
`
`standards-setting organization for the microelectronics industry, to edit, publish, and
`
`maintain JEDEC business records and standards developed by its numerous
`
`committees and subcommittees.
`
`3.
`
`I have been involved with the standardization and publication activities
`
`of JEDEC continuously since 1997. I was the Manager of Standards and
`
`Publications at JEDEC from February 1997 through June 2005. After relocating to
`
`Maine in 2005, I transitioned to working as a full-time Consultant for JEDEC. Since
`
`June 2005, I have continued to work as a Consultant for JEDEC, where my
`
`responsibilities include the maintenance and publication of JEDEC documents and
`
`standards. I am familiar with JEDEC’s historical record-keeping and publication
`
`practices since at least 1992, based on my review of JEDEC’s business records
`
`since that time and my regular discussions with JEDEC employees and members.
`
`During my tenure at JEDEC, JEDEC has not changed the system it uses to maintain
`
`JEDEC documents.
`
`1
`
`XILINX EXHIBIT 1012
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`4.
`
`As a Consultant, I maintain all documents approved for publishing and
`
`have access to all documents at JEDEC. I receive JEDEC documents in draft form
`
`and prepare them for publishing. I also edit and help draft JEDEC’s manuals of
`
`operation and procedure.
`
`5.
`
`For over 60 years, JEDEC has been the global leader in developing and
`
`publishing open standards for the microelectronics industry. JEDEC’s membership
`
`consists of more than 3,000 volunteers representing over 350 member companies,
`
`and includes key technical individuals from most device, assembly, system, and
`
`testing companies. JEDEC publications and standards are adopted worldwide.
`
`JEDEC is accredited by ANSI and maintains liaisons with numerous standards
`
`bodies throughout the world.
`
`6.
`
`Prior to 2000, JEDEC standards were typically available for purchase
`
`from JEDEC or approved reseller IHS. Since at least 2000, JEDEC standards have
`
`been publicly available for download from the JEDEC website
`
`(https://www.jedec.org), where they are cataloged and indexed by keyword and
`
`technological subject matter. Most of the standards are free to download, but larger
`
`volumes are available for purchase through JEDEC’s website and approved reseller
`
`IHS.
`
`7.
`
`By 2000, the JEDEC website was publicly available and commonly
`
`used by manufacturers, companies in the microelectronics industry, and other
`2
`
`
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`XILINX EXHIBIT 1012
`Page 2
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`

`
`
`interested parties to access and obtain standards information pertaining to that
`
`industry. Anyone can register online at JEDEC.org to access free standards and
`
`other JEDEC publications. Registration and most published standards are free and
`
`selected standards are only available to non-members for a fee. Between
`
`approximately 2000 and 2010, a registered user was required to log in before
`
`viewing JEDEC’s free download area, which featured a list of standards and
`
`documents available for download. Around 2010, the website was re-designed so
`
`that a log-in was no longer required to visit the free download area and view a list
`
`of available standards and documents—instead, login information was only
`
`required to view and download a standard or other JEDEC document.
`
`8.
`
`To confirm my statements above regarding access to JEDEC
`
`documents via JEDEC’s website, I have visited the Internet Archive to look at
`
`captures of the “FREE Download Area” login and registration pages of JEDEC’s
`
`website, which occurred on June 15, 2000 and September 1, 2000, respectively:
`
`<http://web.archive.org/web/20000615041617/http:/www.jedec.org/DOWNLOAD/
`
`default.cfm> and
`
`<http://web.archive.org/web/20000901000313/http://www.jedec.org/DOWNLOAD
`
`/copyright_agreement.htm>. Printouts of these captures are attached as Exhibits A
`
`and B and are consistent with my personal recollection of the JEDEC website. I
`
`have also visited the Internet Archive to look at the first capture after the re-design
`3
`
`
`
`XILINX EXHIBIT 1012
`Page 3
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`

`

`of JEDEC’s website, which occurred on February 24, 2010:
`
`<http://web.archive.org/web/20100224045304/http://www.jedec.org/standards-
`
`documents/results/field_doc_type%3A%22JESD%22?order=field_doc_full_numbe
`
`r_value&sort=asc>. A printout of this capture is attached as Exhibit C and is
`
`consistent with my personal recollection of the JEDEC website.
`
`9.
`
`This declaration concerns the following standards published by
`
`JEDEC:
`
`(1) JEDEC STANDARD, Configurations for Solid State Memories, JEDEC
`
`Standard No. 21-C, Release 7 (January 1997) (hereinafter, “JESD21-C Release 7”);
`
`(2) JEDEC STANDARD, Double Data Rate (DDR) SDRAM Specification,
`
`JESD79, Release 1 (June 2000) (hereinafter, “JESD79 Release 1”);
`
`(3) JEDEC STANDARD, Double Data Rate (DDR) SDRAM Specification,
`
`JESD79, Release 2 (May 2002) (hereinafter, “JESD79 Release 2”);
`
`(4) JEDEC STANDARD, DDR2 SDRAM Specification, JESD79-2A (January
`
`2004) (hereinafter, “JESD79-2A”); and
`
`(5) JEDEC STANDARD, Configurations for Solid State Memories, JEDEC
`
`Standard No. 21-C, Release 14 (January 2005) (hereinafter, “JESD21-C Release
`
`14”) (collectively, “the JEDEC Standards”). I have reviewed the above JEDEC
`
`standards. The copies of the JEDEC Standards attached to this declaration as
`
`Exhibits D-H are identical to the copies of the JEDEC Standards in JEDEC’s files.
`4
`
`XILINX EXHIBIT 1012
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`10. The following statements on the public availability of the JEDEC
`
`Standards as of their respective publish dates are based on personal knowledge. The
`
`development of all JEDEC documents follows the process set forth in JM21:
`
`JEDEC Manual of Organization and Procedure. According to that process, the date
`
`on the cover of a JEDEC document is the month the document was finalized,
`
`approved by legal, and published. For the JESD21-C Release 7, JESD79 Release 1,
`
`JESD79 Release 2, JESD79-2A, and JESD21-C Release 14 standards, the dates on
`
`the covers (and thus the dates the standards were published and/or posted to
`
`JEDEC’s website) are January 1997, June 2000, May 2002, January 2004, and
`
`January 2005, respectively.
`
`11.
`
`I am familiar with the circulation and publication procedures used by
`
`JEDEC. Upon approval of the Board of Directors, the JEDEC publications
`
`department prepares documents for publication and seeks final review and approval
`
`to publish from the JEDEC legal department.
`
`12. Before 2000, once legal approval was received, the JEDEC
`
`publications department made the approved document available to the JEDEC
`
`membership and members of the public through JEDEC and, for most documents
`
`except larger volumes and subscription services, through an approved reseller IHS.
`
`For larger volumes, such as JESD21-C, the date on the cover of the Standard
`
`indicates the date that it was sent to those with a subscription to the annual updating
`5
`
`
`
`XILINX EXHIBIT 1012
`Page 5
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`
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`service for the volume, in which subscribers would receive the new and/or updated
`
`replacement pages of the various modules of the Standard as they were released and
`
`insertion instructions for the new and/or updated replacement pages. In addition,
`
`copies of the entire volume, as well as any other finalized standard, would have
`
`been available for purchase from JEDEC by anyone in the public. The release
`
`indicated at the bottom of a given page of larger volumes indicates the release in
`
`which that page would have received by subscribers and would have been available
`
`for purchase by anyone in the public.
`
`13. Since 2000, once legal approval is received, the JEDEC publications
`
`department uploads the approved documents to the JEDEC website with a brief
`
`description. When a standard is published on JEDEC’s website, it becomes
`
`available in the “Standards & Documents” section, where standards are listed by
`
`title, document number, and publish date. An email announcement is then sent to
`
`the sponsoring committee and any approved resellers.
`
`14. Based on my personal knowledge of JEDEC’s policies, the JESD21-C
`
`Release 7 Standard was made publicly available in January 1997, consistent with
`
`the date notation on the first page of the Standard, through a subscription and
`
`availability for purchase by any member of the public, and the JESD79 Release 1,
`
`JESD79 Release 2, JESD79-2A, and JESD21-C Release 14 standards were made
`
`publicly available via JEDEC’s website in June 2000, May 2002, January 2004, and
`6
`
`
`
`XILINX EXHIBIT 1012
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`
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`January 2005, respectively, consistent with the date on the cover page of each
`
`respective Standard.
`
`15. Based on my personal knowledge of JEDEC’s policies, the JESD21-C
`
`Releases 1 through 6 were also publicly available at least by January 1997, when
`
`JESD21-C Release 7 was made publicly available, through a subscription and
`
`availability for purchase by any member of the public of JESD21-C as an entire
`
`volume. Similarly, the JESD21-C Releases 1 through 13 were also publicly
`
`available at least by January 2005, when JESD21-C Release 14 was made publicly
`
`available, through a subscription and availability for purchase by any member of
`
`the public of JESD21-C as an entire volume.
`
`16. My knowledge of the procedures surrounding the creation of the date
`
`notation and publication is based on JEDEC’s policies and practices as I understand
`
`them through my work at JEDEC. I rely on these policies and practices in the
`
`course of my work. I have no reason to believe that JEDEC’s typical practice was
`
`not followed. I have no reason to believe that the JESD21-C Release 7 Standard
`
`was not published and made accessible to JEDEC membership and any member of
`
`the public in January 1997. I also have no reason to believe that the JESD21-C
`
`Release 14 Standard was not published and made accessible to JEDEC membership
`
`and any member of the public in January 2005. I also have no reason to believe that
`
`the JESD79 Release 1, JESD79 Release 2, and JESD79-2A standards were not
`7
`
`
`
`XILINX EXHIBIT 1012
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`
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`made publicly available via JEDEC’s website in June 2000, May 2002, and January
`
`2004, respectively. I also have no reason to believe that the JESD21-C Releases 1
`
`through 6 were not published and made accessible to any member of the public by a
`
`subscription or purchase of JESD21-C at least by January 1997, when the JESD-
`
`21C Release 7 Standard was made publicly available. I also have no reason to
`
`believe that the JESD21-C Releases 1 through 13 were not published and made
`
`accessible to any member of the public by a subscription or purchase of JESD21-C
`
`at least by January 2005, when the JESD-21C Release 14 Standard was made
`
`publicly available.
`
`17. To further confirm my statements above regarding the JESD79 DDR
`
`Standard, I visited the Internet Archive to look at the first capture of the JEDEC
`
`website after June 2000, which occurred on August 17, 2000:
`
`<http://web.archive.org/web/20000817100341/http://www.jedec.org/Default.htm>.
`
`A printout of this capture is attached as Exhibit I and is consistent with my personal
`
`recollection of the JEDEC website. As shown in Exhibit I, the JESD79 Release 1
`
`“DDR” Standard was featured on the JEDEC homepage, which included a link to
`
`the following page captured on August 17, 2000, which allowed anyone to
`
`download the JESD79 DDR Standard for “DDR” memory:
`
`<http://web.archive.org/web/20000817100514/http:/www.jedec.org/DOWNLOAD/
`
`pub21/HotDDR/Default.cfm>. A printout of this capture is attached as Exhibit J
`8
`
`
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`XILINX EXHIBIT 1012
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`
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`and is consistent with my personal recollection of the JEDEC website. As can be
`
`seen from this capture on August 17, 2000, the JESD79 Release 1 DDR Standard
`
`was described on the JEDEC website as the “JEDEC Standard 79, Double Data
`
`Rate (DDR) SDRAM Specification (datasheet for 64Mb SDRAM)” and was
`
`available for download by the public by that date, consistent with my statements
`
`above.
`
`18. Exhibit K is a printout of
`
`<https://web.archive.org/web/20000711020535/http://www.jedec.org/service_mem
`
`bers/New_Members/memberco.htm>, which is a capture on July 11, 2000 of
`
`JEDEC’s list of member companies as of that date. Exhibit L is a printout of
`
`<https://web.archive.org/web/20020605015448/http://www.jedec.org/service_mem
`
`bers/New_Members/memberco.htm>, which is a capture on June 5, 2002 of
`
`JEDEC’s list of member companies as of that date. Exhibit M is a printout of
`
`<https://web.archive.org/web/20040202081543/http://jedec.org:80/service_member
`
`s/New_Members/memberco.cfm>, which is a capture on February 2, 2004 of
`
`JEDEC’s list of member companies as of that date. Exhibit N is a printout of
`
`<https://web.archive.org/web/20051024132448/http://www.jedec.org:80/service_m
`
`embers/New_Members/memberco.cfm>, which is a capture on October 24, 2005 of
`
`JEDEC’s list of member companies as of that date. Exhibits K, L, M, and N are
`
`consistent with my personal recollection of JEDEC’s membership. The member
`9
`
`
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`XILINX EXHIBIT 1012
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`
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`companies listed in Exhibit K would have had access to JESD79 Release 1 by no
`
`later than July 11, 2000. The member companies listed in Exhibit L would have had
`
`access to JESD79 Release 2 by no later than June 5, 2002. The member companies
`
`listed in Exhibit M would have had access to JESD79-2A by no later than February
`
`2, 2004. Lastly, the members listed in Exhibit N would have had access to
`
`JESD21-C Release 14 no later than October 24, 2005.
`
`
`
`I, Julie Carlson, do hereby declare and state that all statements made herein of my
`
`own knowledge are true and that all statements made on information and belief are
`
`believed to be true; and further that these statements were made with the knowledge
`
`that willful false statements and the like so made are punishable by fine or
`
`imprisonment, under Section 1001 of Title 18 of the United States Code.
`
`
`
`
`
`Executed on 1/27/2023
`
`
`
`
`
`
`
`Julie D. Carlson
`
`10
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`XILINX EXHIBIT 1012
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`Exhibit A
`Exhibit A
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`XILINX EXHIBIT 1012
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`XILINX EXHIBIT 1012
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`The Wayback Machine - http://web.archive.org/web/20000615041617/http://www.jedec.org:80/DOWNLOAD/default.cfm
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`
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`
`Log on, please:
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`
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`access the download area
`
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`
`Click here to gain access to
`the Free Download AREA:
`create a Login name and
`password
`
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`
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`
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`
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`This file was last updated: 12/19/2022
`04:41:18
`
`JEDEC Home: http://www.jedec.org
`
`
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`XILINX EXHIBIT 1012
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`Exhibit B
`Exhibit B
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`XILINX EXHIBIT 1012
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`XILINX EXHIBIT 1012
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`The Wayback Machine - http://web.archive.org/web/20000901000313/http://www.jedec.org:80/DOWNLOAD/copyright_agreement.htm
`
`XILINX EXHIBIT 1012
`Page 15
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`Before registering, please read the
`JEDEC Copyright Agreement
`
`XILINX EXHIBIT 1012
`Page 16
`
`

`

`more...
`
`
`
`JEDEC standards and
`publications are designed to
`serve the public interest by
`eliminating misunderstanding
`between manufacturers and
`purchasers and facilitating
`interchangeability and
`improvement of products.
`
`JEDEC standards,
`publications, package outlines
`and all other documents
`posted on JEDECs worldwide
`web site (collectively referred
`to as the files) may be
`downloaded free of charge;
`however, the ownership of
`the copyright resides with the
`JEDEC Solid State Technology
`Association.
`
`JEDEC files may be
`reproduced for internal use
`only without restriction;
`however, the reproduction of
`these files for any other
`purpose, whether in
`electronic and/or hard copy
`form, is PROHIBITED. The
`creation of CD ROMs
`containing the files or
`references to the files and
`links to the JEDEC web site is
`also PROHIBITED. Users of
`JEDEC copyrighted works
`wishing to distribute the files
`for purposes other than noted
`may do so only by purchase,
`or by contacting the JEDEC
`office in writing requesting
`permission to reproduce the
`files along with the reason(s)
`for such a request.
`
` I have read JEDEC’s copyright
`statement and agree to the terms set
`forth above.
`I have read JEDEC’s copyright
`statement and do NOT agree to the
`terms set forth above.
`
`Submit
`
`XILINX EXHIBIT 1012
`Page 17
`
`

`

`Approved for publication on
`March 31, 2000
`
`Return Previous Screen
`
`
`
`Page updated: 12/19/2022
`04:41:48
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`XILINX EXHIBIT 1012
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`Exhibit C
`Exhibit C
`
`XILINX EXHIBIT 1012
`Page 19
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`XILINX EXHIBIT 1012
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`

`The Wayback Machine - http://web.archive.org/web/20100224045304/http://www.jedec.org:80/standards-doc…
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`XILINX EXHIBIT 1012
`Page 20
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`JC-15: Electrical and Thermal Characterization Techniques for Electronic Packages and
`Interconnects
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`Standards & Documents Search: JESD (JEDEC
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`Results 1 - 20 of 296
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`Results
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`Filter by Document Number or Partial Document Number
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`Apply
`
`Title
`LEADLESS CHIP CARRIER PINOUTS STANDARDIZED FOR LINEARS:
`
`Document #
`JESD1
`
`Date
`Apr
`1982
`
`This standard shows how to convert existing DIP pinouts for op-amps, comparators, and D/A converters, to
`chip carrier packages.
`
`Committee(s): JC-41
`
`Download JESD1
`
`Free download. Registration or login required.
`
`XILINX EXHIBIT 1012
`Page 21
`
`

`

`Title
`LOW FREQUENCY POWER TRANSISTORS:Status: Reaffirmed September
`1981, October 2002
`
`Document #
`JESD10
`
`Date
`Jan
`1976
`
`This standard consists of a listing of letter symbols, terms, and definitions that are used in power transistors. It
`also includes information on JEDEC registration procedures, verification tests, and thermal characteristics.
`
`Committee(s): JC-25
`
`Download JESD10
`
`Free download. Registration or login required.
`
`TERMS, DEFINITIONS, AND LETTER SYMBOLS FOR
`MICROCOMPUTERS, MICROPROCESSORS, AND MEMORY INTEGRATED
`CIRCUITS:
`
`JESD100B.01
`
`Dec
`2002
`
`A revised reference for technical writers and educators, manufacturers, buyers and users of microprocessors,
`microcomputers, mircocontrollers, memory ICs, and other complex devices. The terms and their definitions in
`this standard have been updated and are in general agreement with the latest publications of the IEEE and the
`IEC. The companion standard for other integrated circuits is JESD99A. Also included is a system for generating
`symbols for time intervals found in complex sequential circuits, including memories. JESD100B.01 is the first
`minor revision of JESD100-B, December 1999. Annex A briefly shows entries that have changed.
`
`Committee(s): JC-10
`
`Download JESD100B.01
`
`Free download. Registration or login required.
`
`CHIP CARRIER PINOUTS STANDARDIZED FOR CMOS 4000, HC AND HCT
`SERIES OF LOGIC CIRCUITS:
`
`JESD11
`
`Dec
`1984
`
`This standard indicates the procedures used to convert existing DIP and flat packages for digital parts (SSI &
`MSI) to chip carrier packages.
`
`Committee(s): JC-40.2
`
`Download JESD11
`
`Free download. Registration or login required.
`
`SEMICUSTOM INTEGRATED CIRCUITS (FORMERLY PUBLISHED AS
`STANDARD FOR GATE ARRAY BENCHMARK SET):
`
`JESD12
`
`Jun
`1985
`
`The purpose of these benchmarks is to provide a common set of high level functions which serve as vehicles for
`comparing the performance of gate arrays implemented in any technology using any internal structure. These
`benchmarks effectively provide an unbiased measure of gate array vendors' ability to implement a desired
`complex function on a particular gate array at a known level of performance.
`
`Committee(s): JC-44
`
`Download JESD12
`
`XILINX EXHIBIT 1012
`Page 22
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`

`

`Title
`Free download. Registration or login required.
`
`Document #
`
`Date
`
`ADDENDUM No. 1 to JESD12 - TERMS AND DEFINITIONS FOR GATE
`ARRAYS AND CELL-BASED INTEGRATED CIRCUITS:
`
`JESD12-1B
`
`Aug
`1993
`
`The purpose of this standard is to promote the uniform use of abbreviations, terms, and definitions throughout
`the semiconductor industry. It is a useful guide for users, manufactures, educators, technical writers, and others
`interested in the characterization, nomenclature, and classification of semicustom integrated circuits.
`
`Committee(s): JC-44
`
`Download JESD12-1B
`
`Free download. Registration or login required.
`
`ADDENDUM No. 2 to JESD12 - STANDARD FOR CELL-BASED
`INTEGRATED CIRCUIT BENCHMARK SET:
`
`JESD12-2
`
`Feb
`1986
`
`The purpose of these benchmarks is to provide a common set of high level functions that serve as vehicles for
`comparing the performance of cell-based ICs implemented in any technology using any internal structure.
`JESD12-2 extends the gate array benchmark set (JESD12) to cell-based ICs.
`
`Committee(s): JC-44
`
`Download JESD12-2
`
`Free download. Registration or login required.
`
`ADDENDUM No. 3 to JESD12 - CMOS GATE ARRAY MACROCELL
`STANDARD:
`
`JESD12-3
`
`Jun
`1986
`
`This standard defines a minimum set of macro cell standards for CMOS gate arrays. A total of 41 macro cell
`types are addressed, all of which are commonly used by gate array designers to implement Application Specific
`Integrated Circuits.
`
`Committee(s): JC-44
`
`Download JESD12-3
`
`Free download. Registration or login required.
`
`ADDENDUM No. 4 to JESD12 - METHOD OF SPECIFICATION OF
`PERFORMANCE PARAMETERS FOR CMOS SEMICUSTOM INTEGRATED
`CIRCUITS:
`
`JESD12-4
`
`Apr
`1987
`
`This standard defines how to specify various performance parameters of semicustom ICs, including cell and
`interconnect propagation delays, input/output levels and capacitance, and power dissipation.
`
`Committee(s): JC-44
`
`Download JESD12-4
`
`Free download. Registration or login required.
`
`XILINX EXHIBIT 1012
`Page 23
`
`

`

`ADDENDUM No. 5 to JESD12 - DESIGN FOR TESTABILITY GUIDELINES:
`
`JESD12-5
`
`Title
`
`Document #
`
`Date
`Aug
`1988
`
`This standard is intended to provide circuit designers with the information needed to develop complex
`integrated circuits that can be reliably and economically tested without compromising flexibility.
`
`Committee(s): JC-44
`
`Download JESD12-5
`
`Free download. Registration or login required.
`
`ADDENDUM No. 6 to JESD12 - INTERFACE STANDARD FOR
`SEMICUSTOM INTEGRATED CIRCUITS:
`
`JESD12-6
`
`Mar
`1991
`
`This standard defines logic interface levels for CMOS, TTL, ECL, and BiCC inputs and outputs. This standard
`is intended to provide an industry-wide set of specifications, for Application Specific Integrated Circuit (ASIC)
`signal inputs and outputs, both necessary and sufficient to define a circuits electrical interfacing with the
`external environment. JESD12-6 is intended to provide the ASIC manufacturer and user with a common set of
`signal interface levels. The standard defines interface levels for 5 volt operation.
`
`Committee(s): JC-44
`
`Download JESD12-6
`
`Free download. Registration or login required.
`
`STANDARD SPECIFICATION FOR DESCRIPTION OF B SERIES CMOS
`DEVICES:
`
`JESD13-B
`
`May
`1980
`
`This standard provides for uniformity, multiplicity of sources, elimination of confusion, and ease of device
`specifications and system design by users. It gives electrical levels and timing diagrams for B Series CMOS
`devices.
`
`Committee(s): JC-40.2
`
`Download JESD13-B
`
`Free download. Registration or login required.
`
`SEMICONDUCTOR POWER CONTROL MODULES:Status: Reaffirmed June
`1992, April 1999, April 2002
`
`JESD14
`
`Nov
`1986
`
`Semiconductor Power Control Modules (SPCM) are modules consisting of thyristors or transistors, or both, as
`the primary controlling elements. Methods of manufacture of semiconductor power control modules include the
`assembling of individual components and the use of semiconductor hybrids or monolithic processing
`technologies, or both.
`
`Committee(s): JC-22.2
`
`Download JESD14
`
`Free download. Registration or login required.
`
`XILINX EXHIBIT 1012
`Page 24
`
`

`

`Title
`
`THERMAL MODELING OVERVIEW
`
`Document #
`
`Date
`
`JESD15
`
`Oct
`2008
`
`This document and the associated series of documents are intended to promote the continued development of
`modeling methods, while providing a coherent framework for their use by defining a common vocabulary to
`discuss modeling, creating requirements for what information should be included in a thermal modeling report,
`and specifying modeling procedures, where appropriate, and validation methods. This document provides an
`overview of the methodology necessary for performing meaningful thermal simulations for packages containing
`semiconductor devices. The actual methodology components are contained in separate detailed documents.
`
`Committee(s): JC-15.1, JC-15
`
`Download JESD15
`
`Free download. Registration or login required.
`
`COMPACT THERMAL MODEL OVERVIEW
`
`JESD15-1
`
`Oct
`2008
`
`This document should be used in conjunction with the master document, JESD15, and JESD15-2, and
`subsidiary documents as they become available. This document is intended to function as an overview to
`support the effective use of Compact Thermal Model (CTM) methodologies as specified in the companion
`methods documents. At present, there are two such documents; JESD15-3, and JESD15-4.
`
`Committee(s): JC-15.1, JC-15
`
`Download JESD15-1
`
`Free download. Registration or login required.
`
`TWO-RESISTOR COMPACT THERMAL MODEL GUIDELINE
`
`JESD15-3
`
`Jul
`2008
`
`This document specifies the definition and construction of a two-resistor compact thermal model (CTM) from
`the JEDEC junction-to-case and junction-to-board thermal metrics. The guidance provided in this document
`only applies to thermal metrics defined in JEDEC standards JESD51-8 and JESD51-12. The scope of this
`document is limited to single-die packages that can be effectively represented by a single junction temperature.
`
`Committee(s): JC-15
`
`Download JESD15-3
`
`Free download. Registration or login required.
`
`DELPHI COMPACT THERMAL MODEL GUIDELINE
`
`JESD15-4
`
`Oct
`2008
`
`This guideline specifies the definition and lists acceptable approaches for constructing a compact thermal model
`(CTM) based on the DELPHI methodology. The purpose of this document is twofold. First, it aims to provide
`clear guidance to those seeking to create DELPHI compact models of packages. Second, it aims to provide
`users with an understanding of the methodology by which they are created and validated, and the issues
`associated with their use.
`
`XILINX EXHIBIT 1012
`Page 25
`
`

`

`Committee(s): JC-15
`
`Download JESD15-4
`
`Title
`
`Document #
`
`Date
`
`Free download. Registration or login required.
`
`ASSESSMENT OF AVERAGE OUTGOING QUALITY LEVELS IN PARTS PER
`MILLION (PPM):Status: Reaffirmed September 2008
`
`JESD16-A
`
`Apr
`1995
`
`This standard was revised to clarify assumptions necessary to estimate AOQ, revise the minimum sample size
`algorithm, address small sample size concerns, and provide methods for combining groups for AOQ estimation.
`Derivation of any new methods for combing groups for AOQ estimation. Derivation of any new methods
`introduced into this document have been provided in annexes. A statistical method is based on confidence
`interval statistics. A procedure was established for reporting AOQ when the minimum sample size criterion is
`not met. Not all sections of EIA-554 are appropriate for use by device manufacturers therefore JEDEC wishes
`to continue using JESD16A. In December 2008 the formulating committee approved to remove EIA-554 (July
`1996, Reaffirmed September 2002) from the JEDEC website. To obtain a copy of EIA-554 please contact GEIA
`at http://www.geia.org/
`
`Committee(s): JC-13
`
`Download JESD16-A
`
`Free download. Registration or login required.
`
`LATCH-UP IN CMOS INTEGRATED CIRCUITS - SUPERSEDED BY JESD78,
`February 1999Status: Rescinded February 1999
`
`JESD17
`
`Aug
`1988
`
`Committee(s): JC-40.2
`
`Download JESD17
`
`Free download. Registration or login required.
`
`STANDARD FOR DESCRIPTION OF FAST CMOS TTL COMPATIBLE
`LOGIC:
`
`JESD18-A
`
`Jan
`1993
`
`The purpose of this standard is to provide for uniformity, multiplicity of sources, elimination of confusion, and
`ease of device specification and design by users. The standard covers specifications for description of
`'54/74FCTXXXX' series fast CMOS TTL compatible devices.
`
`Committee(s): JC-40.2
`
`Download JESD18-A
`
`Free download. Registration or login required.
`
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`
`XILINX EXHIBIT 1012
`Page 26
`
`

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`XILINX EXHIBIT 1012
`Page 27
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`

`

`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Exhibit D
`Exhibit D
`
`XILINX EXHIBIT 1012
`Page 28
`
`XILINX EXHIBIT 1012
`Page 28
`
`

`

`
`
`CONFIGURATIONS FOR
`SOLID STATE MEMORIES
`
`
`
`
`
`JEDEC Standard No.21-C
`
`
`
`Release 7
`
`
`
`| ELECTRONIC INDUSTRIES ASSOCIATION
`
`ENGINEERING DEPARTMENT
`
`
`
`GINE Pag
`o>Boxe
`7
`cS
`
`XILINX EXHIBIT 1012
`age 29
`
`XILINX EXHIBIT 1012
`Page 29
`
`

`

`NOTICE
`
`EIA/JEDEC Standards and Publications contain material that has been prepared, progressively reviewed, and
`approved through the JEDEC Council level and subsequently reviewed and approved by the ELA General
`Counsel.
`
`EIA/JEDEC Standards and Publications are designed to serve the public interest through eliminating
`misunderstandings between manufacturers and purchases, facilitating interchangeability and improvement
`of products, and assisting the purchaser is selecting and obtaining with minimum delay the proper product
`for his particular need. Existence of such standards shall mot in any respect nreclude any member or
`nonmember of JEDEC from manufacturing or selling products not conforming to such standards, nor shall
`the existence of such standards preclude their voluntary use by those other than ELA members, whether the
`standard is to be used either domestically or internationally.
`
`EIA/JEDEC Standards and Publications are adopted without regard to whether their adoption mayinvolve
`patentsor articles, materials, or processes. By such action, ELA/JEDEC does not assume anyliability to any
`patent owner, nor does it assume any obligation whatever to parties adopting the ELA/JEDEC Standards or
`Publications.
`
`The information included in ELAJEDEC Standards and Publications represents a sound approachto product
`specification and application, principally from the solid state device manufacturer viewpoint