United States Patent (19)
`Krause
`
`USOO6157589A
`Patent Number:
`11
`(45) Date of Patent:
`
`6,157,589
`Dec. 5, 2000
`
`54) DYNAMIC SEMICONDUCTOR MEMORY
`DEVICE AND METHOD FOR INITIALIZING
`A DYNAMIC SEMCONDUCTOR MEMORY
`DEVICE
`
`FOREIGN PATENT DOCUMENTS
`9/1997 European Pat. Off..
`4/1997 Japan.
`
`O 797 207 A2
`9-106668
`
`75 Inventor: Gunnar Krause, Munich, Germany
`73 Assignee: Siemens Aktiengesellschaft, Munich,
`Germany
`
`21 Appl. No.: 09/343,431
`22 Filed:
`Jun. 30, 1999
`30
`Foreign Application Priority Data
`Jun. 30, 1998 DEI Germany ........................... 198 29 287
`(51) Int. Cl." ....................................................... G11C 8700
`52 U.S. C. ...
`... 365/226; 36.5/228
`58 Field of Search ..................................... 365/226, 227,
`365/228
`
`56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,307.319 4/1994 Kohketsu et al..
`5,841,724 11/1998 Ebel et al. .............................. 365/226
`5,894,446 4/1999 Itou ......................................... 365/222
`
`Primary Examiner Vu A. Le
`Attorney, Agent, or Firm-Herbert L. Lerner; Laurence A.
`Greenber; Werner H. Stemer
`57
`ABSTRACT
`A dynamic Semiconductor memory device of a random
`access type has an initialization circuit that controls the
`Switching-on operation of the Semiconductor memory
`device and of its circuit components. The initialization
`circuit Supplies a Supply Voltage Stable signal once the
`Supply Voltage has been Stabilized after the Switching-on of
`the Semiconductor memory device. The initialization circuit
`has an enable circuit that receives the Supply Voltage Stable
`Signal and further command Signals externally applied to the
`Semiconductor memory device. The enable circuit Supplies
`an enable Signal after a predetermined proper initialization
`Sequence of the command Signals applied to the Semicon
`ductor memory device is identified. The enable Signal effects
`the unlatching of a control circuit provided for the proper
`operation of the Semiconductor memory device.
`
`13 Claims, 3 Drawing Sheets
`
`14
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`10A
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`
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`PRE
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`ARF
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`1OC
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`MRS
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`POWERON
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`U.S. Patent
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`Dec. 5, 2000
`
`Sheet 1 of 3
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`6,157,589
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`Fig 1
`
`
`
`
`
`input Circuit
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`
`
`
`
`
`
`Command
`DECODER
`
`TE Circuit for
`Memory Blocks
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`CHPREADY
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`
`
`
`
`
`
`internal Voltage
`Regulation and
`Detection
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`
`
`
`
`Enable Circuit
`
`POWERON
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`U.S. Patent
`
`Dec. 5, 2000
`
`Sheet 2 of 3
`
`6,157,589
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`10A
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`PRE
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`14
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`POWERON
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`Fig 2
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`SIGNAL
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`am as - as
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`a m r -ama u
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`-o
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`HGH
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`""--------------------- LOW
`PRE
`Q
`9.----------
`
`
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`ARF
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`MRS
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`CHPREADY
`
`-o-
`
`Time
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`U.S. Patent
`
`Dec. 5, 2000
`
`Sheet 3 of 3
`
`6,157,589
`
`D CHIPREADY
`
`12
`
`POWER ONC
`
`an
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`or us as a
`
`a
`
`u as a
`
`h
`
`h ea w
`
`an a
`
`a
`
`a
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`Fig. 4
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`6,157,589
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`1
`DYNAMIC SEMCONDUCTOR MEMORY
`DEVICE AND METHOD FOR INITIALIZING
`A DYNAMIC SEMCONDUCTOR MEMORY
`DEVICE
`
`BACKGROUND OF THE INVENTION
`
`2
`with the POWERON signal. The signal POWERON is
`active if the internal Supply Voltages have reached the
`necessary values that are necessary for the proper operation
`of the component. The module is then in a position to
`recognize and execute instructions.
`SUMMARY OF THE INVENTION
`It is accordingly an object of the invention to provide a
`dynamic Semiconductor memory device and a method for
`initializing a dynamic Semiconductor memory device which
`overcome the above-mentioned disadvantages of the prior
`art methods and devices of this general type, which is as
`Simple as possible in Structural terms and which effectively
`prevents the risk of a short circuit of the data lines and/or of
`uncontrolled activation of internal current loads.
`With the foregoing and other objects in view there is
`provided, in accordance with the invention, a dynamic
`Semiconductor memory device of a random access type,
`containing an initialization circuit controlling a Switching
`on operation and Supplying a Supply Voltage Stable Signal
`once a Supply voltage has been Stabilized after the
`Switching-on operation. The initialization circuit has a con
`trol circuit for controlling operations and an enable circuit
`receiving the Supply Voltage Stable signal and externally
`applied further command Signals. The enable circuit output
`ting an enable Signal after a predetermined proper initial
`ization Sequence of the externally applied further command
`Signals are identified and the enable signal effecting an
`unlatching of the control circuit.
`The invention provides for the initialization circuit to
`have an enable circuit, which receives the Supply Voltage
`Stable Signal and the externally applied further command
`Signals. The enable circuit generates the enable signal after
`the identification of the predetermined proper initialization
`Sequence of the command Signals is achieved. The enable
`Signal effects the unlatching of the control circuit provided
`for the proper operation of the Semiconductor memory
`device.
`Following the principle of the invention, the enable Signal
`(CHIPREADY) is generated and becomes active in depen
`dence on further internal Signals and the initialization
`Sequence and then unlatches predetermined circuits. The
`predetermined circuits remain latched until the end of the
`predetermined initialization Sequence. By way of example,
`commands are decoded but not executed and the output
`drivers are held at high impedance.
`According to the preferred application in SDRAM
`memory devices according to the JEDEC Standard, it is
`provided that the command Signals, externally applied to the
`Semiconductor memory device, of the initialization
`sequence are to be identified by the enable circuit. The
`command Signals include a preparation command Signal for
`word line activation (PRECHARGE), and/or a refresh com
`mand signal (AUTOREFRESH), and/or a loading configu
`ration register command signal (MODE-REGISTER-SET).
`According to an advantageous structural refinement of the
`initialization circuit according to the invention, it is provided
`that the enable circuit has at least one bistable multivibrator
`Stage with a Set input which receives the command Signal
`(PRECHARGE, AUTOREFRESH, MODE-REGISTER
`SET). The bistable multivibrator also has a reset input to
`which the Supply voltage stable signal (POWERON), a
`Signal derived therefrom, or a linked signal is applied. The
`bistable multivibrator further has an output at which the
`enable signal (CHIPREADY) is outputted.
`In particular, the enable circuit has a plurality of bistable
`multivibrator Stages respectively receiving the command
`Signals.
`
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`Field of the Invention
`The invention relates to a dynamic Semiconductor
`memory device of the random access type (DRAM/
`SDRAM) having an initialization circuit which controls a
`Switching-on operation of the Semiconductor memory
`device and of its circuit components. The initialization
`circuit supplies a supply voltage stable signal (POWERON)
`once a Supply voltage has been Stabilized after the
`Switching-on of the Semiconductor memory device. The
`invention also relates to a method for initializing Such a
`dynamic Semiconductor memory device, and also to the use
`of an enable circuit, that Supplies an enable Signal, for
`controlling the Switching-on operation of the dynamic Semi
`conductor memory device.
`In the case of SDRAM semiconductor memories accord
`ing to the JEDEC Standard, it is necessary to ensure during
`the switch-on operation (“POWERUP”) that the internal
`control circuits provided for the proper operation of the
`Semiconductor memory device are reliably held in a defined
`desired State, in order to prevent undesirable activation of
`output transistors that would cause, on the data lines, a short
`circuit (so-called “bus contention” or “data contention”) or
`uncontrolled activation of internal current loads. The Solu
`tion to the problem turns out to be difficult on account of a
`fundamental unpredictability of the time characteristic of the
`Supply Voltage and of the Voltage level or levels at the
`external control inputs during the Switch-on operation of the
`Semiconductor memory. According to the Specifications of
`the manufacturer an SDRAM component should ignore all
`commands which are present chronologically before a
`defined initialization Sequence. The Sequence consists of
`predetermined commands that must be applied in a defined
`chronological order. However, a Series of functions and
`commands which are allowed during proper operation of the
`component are desired or allowed chronologically only after
`the initialization Sequence. According to the JEDEC Stan
`dard for SDRAM semiconductor memories, a recommended
`initialization sequence (so-called “POWERON
`45
`SEQUENCE") is provided as follows:
`a. the application of a Supply Voltage and a start pulse in
`order to maintain an NOP condition at the inputs of the
`component,
`b. the maintenance of a stable Supply Voltage of a stable
`clock signal, and of stable NOP input conditions for a
`minimum time period of 200 us;
`c. the preparation command for word line activation
`(PRECHARGE) for all the memory banks of the
`device;
`4. the activation of eight or more refresh commands
`(AUTOREFRESH); and
`5. the activation of a loading configuration register com
`mand (MODE-REGISTER-SET) for initializing the
`60
`mode register.
`After the identification of Such a defined initialization
`Sequence, the memory module is normally in a So-called
`IDLE state, that is to Say it is precharged and prepared for
`proper operation. In the case of the SDRAM semiconductor
`memory modules that have been disclosed to date, all the
`control circuits of the component have been unlatched only
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`3
`In an expedient refinement of the invention, it is provided
`that the output of at least one of the bistable multivibrator
`Stages is passed to a reset input of a further multivibrator
`Stage. In this case, it may furthermore be provided that, in
`one of the bistable multivibrator Stages, the Supply Voltage
`stable signal (POWERON) and the signal output from the
`output of the further multivibrator Stage are passed, after
`having been logically combined by a gate, to the reset input
`of the multivibrator Stage.
`Other features which are considered as characteristic for
`the invention are set forth in the appended claims.
`Although the invention is illustrated and described herein
`as embodied in a dynamic Semiconductor memory device
`and a method for initializing a dynamic Semiconductor
`memory device, it is nevertheless not intended to be limited
`to the details shown, Since various modifications and struc
`tural changes may be made therein without departing from
`the Spirit of the invention and within the Scope and range of
`equivalents of the claims.
`The construction and method of operation of the
`invention, however, together with additional objects and
`advantages thereof will be best understood from the follow
`ing description of Specific embodiments when read in con
`nection with the accompanying drawings.
`
`4
`and the structure of the circuits 1, 3 and 5 are sufficiently
`known to the person skilled in the art and therefore do not
`need to be explained in any more detail. What is important
`for understanding the invention is the fact that the circuit 5
`supplies an active POWERON signal if, after the POW
`ERUP phase of the SDRAM memory, the internal supply
`Voltages present at the output 8 have reached the values
`necessary for proper operation of the component.
`According to the invention, the initialization circuit fur
`thermore has an enable circuit 9 connected downstream of
`the circuits 3 and 5. The command signals PRE, ARF and
`MRS are applied to an input 10 of the enable circuit 9 and
`the POWERON signal is applied to an input 11 of the enable
`circuit 9. An enable signal CHIPREADY is supplied at an
`output 12 of the enable circuit 9 after the identification of a
`predetermined proper initialization Sequence of the com
`mand Signals applied to the Semiconductor memory device
`is achieved. The enable signal effects unlatching of control
`circuits 13 provided for proper operation of the Semicon
`ductor memory device. The internal control circuits 13 serve
`inter alia for Sequence control for one or more of the
`memory blocks of the SDRAM memory and are known as
`Such.
`FIG. 2 shows a preferred exemplary embodiment of the
`enable circuit 9 according to the invention. The enable
`circuit 9 contains three bistable multivibrator stages 14, 15
`and 16 each having a Set input S, a reset input R, and also
`an output Q. An AND gate 17 connected upstream of the
`reset input R of the multivibrator stage 15 and an AND gate
`18 connected downstream of all the outputs Q of the
`multivibrator stages 14, 15, 16 are further provided. The
`enable circuit further has an inverter 19 connected down
`stream of the AND gate 18. The enable signal CHIPREADY
`being output at the output 12 of the inverter 19 and the
`enable signal CHIPREADY is active HIGH, that is to say
`activated when its voltage level is at logic HIGH. The
`command signals PRE, ARF, MRS applied to the respective
`set inputs S of the bistable multivibrator stages 14, 15, 16 are
`each active LOW, that is to say these signals are active when
`their voltage level is at logic LOW, while the POWERON
`signal is again active HIGH. The POWERON signal is
`applied directly to the reset inputS R in the case of the
`multivibrator stages 14 and 16 and is firstly applied to one
`input of the AND gate 17 in the case of the multivibrator
`Stage 15, the Signal output from the output Q of the multi
`vibrator stage 14 is applied to the other input of the AND
`gate 17, the output of the AND gate 17 is connected to the
`reset input of the multivibrator stage 15.
`The method of operation of the enable circuit 9 illustrated
`in FIG. 2 is such that activation of the enable signal
`CHIPREADY at is the output 12 to logic HIGH is generated
`only when a predetermined chronological initialization
`sequence of the command signals PRE, ARF and MRS and
`activation of the POWERON signal to the logic level HIGH
`are detected. Only then are the control circuits 13 unlatched
`on account of the activation of the enable Signal
`CHIPREADY; the control circuits 13 remaining latched
`prior to this.
`In the Schematic time Sequence diagram according to FIG.
`3, exemplary command Sequences during the Switching-on
`operation of the Semiconductor memory device are illus
`trated in order to elucidate the method of operation of the
`enable circuit 9. In the case situation A, the signal PRE
`CHARGE is activated to active LOW too early relative to
`the activation of the POWERON signal, with the result that,
`the enable signal CHIPREADY is not yet activated to logic
`HIGH Since the proper initialization Sequence requires a
`
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`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a diagrammatic, block diagram of components
`of an initialization circuit which controls a Switching-on
`operation of a Semiconductor memory and its circuit com
`ponents according to the invention;
`FIG. 2 is circuit diagram of an enable circuit that Supplies
`an enable signal (CHIPREADY);
`FIG. 3 is a time Sequence diagram for elucidating a
`method of operation of the circuit according to FIG. 2.; and
`FIG. 4 is a circuit diagram of the enable circuit according
`to an exemplary embodiment of the invention.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`In all the figures of the drawing, Sub-features and integral
`parts that correspond to one another bear the same reference
`Symbol in each case. Referring now to the figures of the
`drawing in detail and first, particularly, to FIG. 1 thereof,
`there are shown circuit components, important for under
`standing the invention, of an SDRAM memory device
`operating according to the JEDEC Standard. The circuit
`components include an initialization circuit controlling a
`Switching-on operation of the SDRAM memory device and
`its circuit components. The initialization circuit has an input
`circuit 1, to whose input 2 command and clock signals that
`are externally applied in reference to the Semiconductor
`memory are provided. The command and clock Signals are
`amplified and conditioned before being received by a com
`55
`mand decoder 3 connected downstream of the input circuit
`1 and at whose output 4, inter alia, the command Signals
`PRE or PRECHARGE (preparation command for word line
`activation), ARF or AUTOREFRESH (refresh command)
`and MRS or MODE-REGISTER-SET (loading configura
`tion register command) are output. The initialization circuit
`further has a circuit 5 for internal Voltage regulation and/or
`detection, at whose input 6 the external Supply Voltages that
`are externally applied to the Semiconductor memory exter
`nally are fed in. The circuit 5 has a first output 7 outputting
`a POWERON signal and a second output 8 supplying
`Stabilized internal Supply Voltages. The method of operation
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`S
`waiting time before the first command. The Signal Swing of
`the command PRECHARGE according to case situation A is
`thus correctly ignored. In case situation B, the chronological
`order of the activation of the signal AUTOREFRESH to
`logic LOW is incorrect Since the proper initialization
`sequence prescribes a previous PRECHARGE command
`before the AUTOREFRESH command. The signal Swing of
`the AUTOREFRESH signal to logic LOW according to case
`Situation B is therefore likewise ignored, and the enable
`Signal does not go to logic HIGH. In case situation C, a
`correct chronological order of the commands
`PRECHARGE, AUTOREFRESH, MODE-REGISTER
`SET is present conforming to the JEDEC standard, in a
`logically consistent manner, since the POWERON signal is
`also at logic HIGH, an enable signal CHIPREADY at logic
`HIGH is now supplied. Illustrated using dashed lines,
`another further conceivable initialization Sequence that is
`allowed and therefore triggers an enable Signal is repre
`sented by the symbol D; activation of the command MODE
`REGISTER-SET to logic LOW is allowed at any time after
`the activation of the POWERON signal.
`FIG. 4 shows further details of a preferred exemplary
`embodiment of the enable circuit 9 according to the inven
`tion. In this exemplary embodiment, each of the bistable
`multivibrators 14, 15, 16 is constructed from in each case
`two NAND gates 14A, 14B, 15A, 17, 16A, 16B and also an
`inverter 14C, 15C and 16C, which are connected to one
`another in the manner illustrated. The NAND gate 17 is
`provided with three inputs in the bistable multivibrator 15.
`I claim:
`1. A dynamic Semiconductor memory device of a random
`acceSS type, comprising:
`an initialization circuit controlling a Switching-on opera
`tion and Supplying a Supply Voltage Stable signal once
`a Supply Voltage has been Stabilized after the Switching
`on operation, Said initialization circuit having a control
`circuit for controlling operations and an enable circuit
`receiving the Supply Voltage Stable Signal and exter
`nally applied further command Signals, Said enable
`circuit outputting an enable Signal after a predeter
`mined proper initialization Sequence of the externally
`applied further command Signals being identified and
`the enable Signal effecting an unlatching of Said control
`circuit.
`2. The Semiconductor memory device according to claim
`1, wherein the externally applied further command Signals
`forming the predetermined proper initialization Sequence to
`be identified by Said enable circuit includes at least one of a
`preparation command Signal for word line activation, a
`refresh command Signal, and a loading configuration register
`command Signal.
`3. The Semiconductor memory device according to claim
`1, wherein Said enable circuit has at least one bistable
`multivibrator Stage having a Set input receiving the exter
`nally applied further command Signals, a reset input receiv
`ing one of the Supply Voltage Stable Signal, a signal derived
`from the Supply Voltage Stable Signal and a linked Signal, and
`an output outputting Said enable signal.
`4. The Semiconductor memory device according to claim
`3, wherein Said at least one bistable multivibrator Stage is a
`plurlity of bistable multivibrator Stages respectively receiv
`ing one of the externally applied further command Signals.
`5. The Semiconductor memory device according to claim
`4, wherein said output of one of said plurality of bistable
`multivibrator Stages is passed to Said reset input of another
`of said plurality of bistable multivibrator stages.
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`6
`6. The Semiconductor memory device according to claim
`4, including an AND gate receiving the Supply Voltage Stable
`Signal and a signal output from Said output of one of Said
`plurality of bistable multivibrator stages, said AND gate
`outputting an output signal received at Said reset input of
`another of said plurality of bistable multivibrator stages.
`7. The Semiconductor memory device according to claim
`4, wherein Said plurality of bistable multivibrator Stages are
`each formed of an RS flip-flop constructed from one of at
`least two NOR and at least two NAND gates.
`8. The Semiconductor memory device according to claim
`1, wherein the identification of an initialization Sequence
`that is identified as the predetermined proper initialization
`Sequence by Said enable circuit and generates the enable
`Signal constitutes a command Sequence conforming to a
`JEDEC standard.
`9. The Semiconductor memory device according to claim
`1, wherein Said control circuit has output drivers remaining
`latched during the Switching-on operation until Said enable
`Signal is generated by Said enable circuit.
`10. The Semiconductor memory device according to claim
`1, wherein the predetermined proper initialization Sequence
`includes one of the following chronologically Successive
`command Sequences:
`a) firstly PRE, secondly ARF, thirdly MRS;
`b) firstly PRE, secondly MRS, thirdly ARF; and
`c) firstly MRS, secondly PRE, or thirdly ARF;
`where,
`PRE=the preparation command signal for word line
`activation,
`ARF=the refresh command Signal, and
`MRS=the loading configuration register command Signal.
`11. An improved method for initializing a dynamic Semi
`conductor memory device of a random access type via an
`initialization circuit controlling a Switching-on operation of
`the dynamic Semiconductor memory device and of its circuit
`components, the improvement which comprises:
`Supplying, via the initialization circuit, a Supply Voltage
`Stable Signal once a Supply Voltage has been Stabilized
`after the Switching-on operation of the dynamic Semi
`conductor memory device; and
`Supplying, via an enable circuit of the initialization
`circuit, an enable signal, the initialization circuit receiv
`ing the Supply Voltage Stable Signal and further com
`mand Signals externally applied to the dynamic Semi
`conductor memory device, after an identification of a
`predetermined proper initialization Sequence of the
`further command Signals the enable Signal being gen
`erated and effecting an unlatching of a control circuit
`provided for a proper operation of the dynamic Semi
`conductor memory device.
`12. The method according to claim 11, which comprises
`providing at least one of a preparation command Signal for
`word line activation, a refresh command Signal, and a
`loading configuration register command Signal as the further
`command Signals.
`13. The method according to claim 11, which comprises
`maintaining a latched condition of output drivers of the
`dynamic Semiconductor memory device during the
`Switching-on operation until the enable Signal is generated
`by the enable circuit.
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