Filed on behalf of: Polaris Innovations Limited
`
`By: David T. DeZern
`Registration No. 60,117
`NELSON BUMGARDNER CONROY P.C.
`2727 N. Harwood Street, Suite 250
`Dallas, TX 75201
`Telephone: (214) 446-4950
`Email: david@nelbum.com
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`________________
`
`XILINX, INC.,
`
`Petitioner
`
`v.
`
`POLARIS INNOVATIONS LIMITED,
`
`Patent Owner.
`
`________________
`
`Case IPR2023-00516
`
`U.S. Patent 6,157,589
`________________
`
`
`PATENT OWNER’S RESPONSE
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`
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`

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`TABLE OF CONTENTS
`
`INTRODUCTION ................................................................................................. 1
`
`THE ’589 PATENT AND THE CHALLENGED CLAIMS .......................................... 2
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`A. Overview of the ’589 Patent .................................................................. 2
`
`B.
`
`Challenged Claims ................................................................................ 8
`
`I.
`
`II.
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`
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`
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`III. LEVEL OF ORDINARY SKILL ............................................................................10
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`IV. CLAIM CONSTRUCTION ...................................................................................11
`
`
`A.
`
`“Externally Applied Further Command Signals” (Cl. 1) / “Further
`Command Signals Externally Applied” (Cl. 11) ................................11
`
`
`V. APPLICABLE LEGAL STANDARDS ....................................................................18
`
`
`A. Anticipation .........................................................................................18
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`B. Obviousness .........................................................................................19
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`VI. SUMMARY OF THE REFERENCES ......................................................................22
`
`
`1.
`
`2.
`
`3.
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`Claims cannot be found obvious if an element is absent. ..............19
`
`A petition must address the Graham factors. .................................20
`
`A petition must provide articulated reasoning with rational
`underpinning to combine and/or modify references. .....................21
`
`A. Overview of Primary Reference: Kocis ..............................................22
`
`B. Overview of Primary Reference: Lee .................................................24
`
`C. Overview of Secondary References ....................................................28
`
`1.
`
`2.
`
`JESD 21-C ......................................................................................28
`
`Iketani .............................................................................................29
`
`Patent Owner’s Response
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`
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`ii
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`

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`VII. THE CHALLENGED CLAIMS ARE PATENTABLE OVER THE ASSERTED
`GROUNDS ........................................................................................................30
`
`A. Grounds 3B, 4, 5, and 6: Lee and the Asserted Combinations
`Fail to Render the Challenged Claims Obvious. .................................32
`
`1.
`
`2.
`
`Lee Alone or in Combination with Iketani and/or
`JESD 21-C Fails to Render Obvious Receiving Or
`Identifying a Sequence of “Further Command
`Signals.” (Claim elements 1.2, 1.3, 11.2) ......................................32
`
`Lee Alone or in Combination with Iketani Fails to
`Render Obvious An Enable Signal “Effecting An
`Unlatching of [a/said] Control Circuit.” (Claim
`elements 1.3 and 11.2) ...................................................................36
`
`B. Ground 3A: Lee Does Not Anticipate Either of the Independent
`Claims. .................................................................................................43
`
`C. Grounds 1 and 2: Kocis Fails to Anticipate or Render Obvious the
`Challenged Claims. .............................................................................44
`
`1.
`
`2.
`
`Kocis Does Not Anticipate Either of the Independent Claims. .....44
`
`JESD 21-C Does Not Cure Any of the Issues Identified in the
`Independent Claims. .......................................................................44
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`D. Grounds 7 and 8: The Addition of Kocis to Lee or Lee in
`Combination with Iketani Fails to Render Obvious Dependent Claims
`9 and 13. ..............................................................................................45
`
`
`VIII. CONCLUSION ...................................................................................................47
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`Patent Owner’s Response
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`iii
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`

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`TABLE OF AUTHORITIES
`
`Cases
`
`CFMT, Inc. v. YieldUp Int’l Corp.,
` 349 F.3d 1333 (Fed. Cir. 2003) ...................................................................... 19-20
`
`Continental Can Co. USA, Inc. v. Monsanto Co.,
` 948 F.2d 1264 (Fed. Cir. 1991) ............................................................................19
`
`Eizo Corp. v. Barco N.V.,
` IPR2014-00358, Paper 11 (PTAB July 23, 2014) .......................................... 20-21
`
`Garmin Int’l, Inc. v. Patent of Cuozzo Speed Techs. LLC,
` IPR2012-00001, Paper 15 (PTAB Jan. 9, 2013) ..................................................20
`
`Graham v. John Deere Co.,
` 383 U.S. 1 (1966) ........................................................................................... 19, 20
`
`Hansgirg v. Kemmer,
` 102 F.2d 212 (CCPA 1939) ..................................................................................19
`
`In re Arkley,
` 455 F.2d 586 (CCPA 1972) ..................................................................................18
`
`In re Kahn,
` 441 F.3d 977 (Fed. Cir. 2006) ..............................................................................21
`
`In re Oelrich,
` 666 F.2d 578 (CCPA 1981) ..................................................................................19
`
`In re Rijckaert,
` 9 F.3d 1531 (Fed. Cir. 1993) ................................................................................20
`
`In re Royka,
` 490 F.2d 981 (CCPA 1974) ..................................................................................20
`
`InTouch Techs., Inc. v. VGo Comm’ns., Inc.,
` 751 F.3d 1327 (Fed. Cir. 2014) ............................................................................20
`
`KSR Int’l Co. v. Teleflex Inc.,
` 550 U.S. 398 (2007) ....................................................................................... 20, 21
`
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`Patent Owner’s Response
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`iv
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`LG Elecs., Inc. v. Cellular Commc’ns Equip. LLC,
` IPR2016-00197, Paper 7 (PTAB April 29, 2016) ................................................21
`
`N.V. v. Abbott Labs.,
` 512 F.3d 1363 (Fed. Cir. 2008) ............................................................................21
`
`Net MoneyIN, Inc. v. VeriSign, Inc.,
` 545 F.3d 1359 (Fed. Cir. 2008) ............................................................................18
`
`Rules, Regulations and Statutes
`
`35 U.S.C. § 102 ........................................................................................................18
`
`35 U.S.C. § 103 ........................................................................................................20
`
`35 U.S.C. § 103(a) ...................................................................................................19
`
`35 U.S.C. 282(b) ......................................................................................................11
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`37 C.F.R. § 42.100(b) ..............................................................................................11
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`Patent Owner’s Response
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`v
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`TABLE OF EXHIBITS
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`
`Exhibit
`
`Description
`
`2001 Declaration of Timothy D. Dorney, Ph.D. Pursuant to 37 C.F.R. § 1.68
`
`2002 Transcript of the Deposition Stephen W. Melvin, Ph.D.
`
`
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`Patent Owner’s Response
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`LISTING OF CHALLENGED CLAIMS
`
`Claim 1
`[1.P]
`
`[1.1]
`
`[1.2]
`
`[1.3]
`
`Claim 2
`[2]
`
`Claim 8
`[8]
`
`A dynamic semiconductor memory device of a random access type,
`comprising:
`an initialization circuit controlling a switching-on operation and supplying
`a supply voltage stable signal once a supply voltage has been stabilized
`after the switching-on operation,
`said initialization circuit having a control circuit for controlling operations
`and an enable circuit receiving the supply voltage stable signal and
`externally applied further command signals,
`said enable circuit outputting an enable signal after a predetermined proper
`initialization sequence of the externally applied further command signals
`being identified and the enable signal effecting an unlatching of said
`control circuit.
`
`The semiconductor memory device according to claim 1, wherein the
`externally applied further command signals forming the predetermined
`proper initialization sequence to be identified by said enable circuit
`includes at least one of a preparation command signal for word line
`activation, a refresh command signal, and a loading configuration
`register command signal.
`
`The semiconductor memory device according to claim 1, wherein the
`identification of an initialization sequence that is identified as the
`predetermined proper initialization sequence by said enable circuit and
`generates the enable signal constitutes a command sequence conforming
`to a JEDEC standard.
`
`
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`Claim 9
`[9]
`
`The semiconductor memory device according to claim 1, wherein said
`control circuit has output drivers remaining latched during the switching-
`on operation until said enable signal is generated by said enable circuit.
`Claim 10
`The semiconductor memory device according to claim 1, wherein the
`[10]
`predetermined proper initialization sequence includes one of the following
`chronologically successive command sequences:
`a) firstly PRE, secondly ARF, thirdly MRS;
`b) firstly PRE, secondly MRS, thirdly ARF; and
`c) firstly MRS, secondly PRE, or thirdly ARF;
`where,
`PRE=the preparation command signal for word line activation,
`ARF=the refresh command signal, and
`MRS=the loading configuration register command signal.
`Claim 11
`[11.P] An improved method for initializing a dynamic semiconductor memory
`device of a random access type via an initialization circuit controlling a
`switching-on operation of the dynamic semiconductor memory device and
`of its circuit components, the improvement which comprises:
`supplying, via the initialization circuit, a supply voltage stable signal once
`a supply voltage has been stabilized after the switching-on operation of the
`dynamic semiconductor memory device; and
`supplying, via an enable circuit of the initialization circuit, an enable
`signal, the initialization circuit receiving the supply voltage stable signal
`and further command signals externally applied to the dynamic
`semiconductor memory device, after an identification of a predetermined
`proper initialization sequence of the further command signals the enable
`signal being generated and effecting an unlatching of a control circuit
`provided for a proper operation of the dynamic semiconductor memory
`device.
`
`[11.1]
`
`[11.2]
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`Claim 12
`The method according to claim 11, which comprises providing at least one
`[12]
`of a preparation command signal for word line activation, a refresh
`command signal, and a loading configuration register command signal as
`the further command signals.
`Claim 13
`The method according to claim 11, which comprises maintaining a latched
`[13]
`condition of output drivers of the dynamic semiconductor memory device
`during the switching-on operation until the enable signal is generated by
`the enable circuit.
`
`
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`Patent Owner’s Response
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`ix
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`

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`I.
`
`INTRODUCTION
`Polaris Innovations Limited (“Patent Owner”) submits this Response to
`
`Xilinx, Inc.’s (“Petitioner”) Petition for Inter Partes Review (“Petition,” Paper 2),
`
`challenging Claims 1, 2, and 8-13 of U.S. Patent 6,157,589 (the “’589 Patent”) (Ex.
`
`1001).
`
`The ’589 Patent concerns methods and circuitry for powering on dynamic
`
`random-access memories (“DRAM”). The claims require circuitry to identify a
`
`sequence of command signals and then unlatch the DRAM for normal operation.
`
`Petitioner raises nine grounds to challenge these claims combining four different
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`references in various configurations in an attempt to reconstruct the claimed
`
`invention. The overall approach and an examination of the individual references and
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`assertions demonstrates that these arguments are nothing more than the application
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`of hindsight bias to cobble together prior art circuitry to achieve the ends and
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`requirements of the claimed inventions.
`
`The Board previously found that five of the grounds asserted in the petition
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`were not likely to be successful. The other four, obviousness combinations based on
`
`the primary Lee reference, fail to render the challenged claims obvious at least
`
`because they do not disclose identifying a sequence of command signals or
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`unlatching a DRAM as explained in more detail below. The remaining grounds that
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`Patent Owner’s Response
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`the Board previously found lacking should fail for the same reasons previously
`
`identified and additional ones provided herein.
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`
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`The Board should reject each of Petitioner’s proposed grounds for invalidity
`
`and confirm that Petitioner has failed to show unpatentability for the challenged
`
`claims.
`
`II. THE ’589 PATENT AND THE CHALLENGED CLAIMS
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`A. Overview of the ’589 Patent
`
`The ’589 Patent “relates to a dynamic semiconductor memory device of the
`
`random access type (DRAM/SDRAM) having an initialization circuit which
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`controls a switching-on operation of the semiconductor memory device.” Ex. 1001
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`at 1:9-13. “The invention [] relates to a method for initializing such a dynamic
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`semiconductor memory device, and [] the use of an enable circuit, that supplies an
`
`enable signal, for controlling the switching-on operation of the dynamic
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`semiconductor memory device.” Id. at 1:16-21.
`
`The
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`’589 Patent explains
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`that “during
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`the switch-on operation
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`(‘POWERUP’)” for “SDRAM semiconductor memories according to the JEDEC
`
`standard” “the internal control circuits” must be “held in a defined desired state, in
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`order to prevent undesirable activation” “or uncontrolled activation.” Id. at 1:22-30.
`
`“The solution to the problem turns out to be difficult on account of a fundamental
`
`unpredictability of the time characteristic of the supply voltage and of the voltage
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`level or levels at the external control inputs during the switch-on operation of the
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`semiconductor memory.” Id. at 1:30-35.
`
`The ’589 patent explains that “[a]ccording to the specifications of the
`
`manufacturer an SDRAM component should ignore all commands which are present
`
`chronologically before a defined initialization sequence.” Id. at Col. 1:35-38. “The
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`sequence consists of predetermined commands that must be applied in a defined
`
`chronological order.” Id. at Col. 1:38-40. The ’589 Patent provides an example of “a
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`recommended initialization sequence” from the JEDEC standard. Id. at 1:43-61. The
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`’589 Patent explains that “[a]fter the identification of such a defined initialization
`
`sequence, the memory module is normally in a so-called IDLE state, that is to say it
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`is precharged and prepared for proper operation.” Id. at Col. 1:62-65. “In the case of
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`SDRAM semiconductor memory modules that have been disclosed to date,” all the
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`control circuits of the component have been unlatched only with the POWERON
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`signal.” Id. at Col. 1:65-2:1. “The signal POWERON is active if the internal supply
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`voltages have reached the necessary values that are necessary for the proper
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`operation of the component.” Id. at Col. 2:1-4.
`
`The ’589 Patent addresses these issues by providing “an initialization circuit
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`controlling a switching-on operation.” Id. at Col. 2:15-21. The initialization circuit
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`includes an “enable circuit outputting an enable signal after a predetermined proper
`
`initialization sequence of the externally applied further command signals are
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`identified and the enable signal effecting an unlatching of the control circuit.” Id. at
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`Col. 2:20-28.
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`The ’589 Patent provides a block diagram of an initialization circuit according
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`to the invention in Figure 1:
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`Ex. 1001, Fig. 1.
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`
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`“The initialization circuit has an input circuit 1, to whose input 2 command
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`and clock signals [] are externally applied.” Id. at 3:51-53. “The command and clock
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`signals are amplified and conditioned before being received by a command decoder
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`3 . . . at whose output 4, inter alia, the command signals PRE or PRECHARGE
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`(preparation command for word line activation), ARF or AUTOREFRESH (refresh
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`command) and MRS or MODE-REGISTER-SET (loading configuration register
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`command) are output.” Id. at 3:54-61. “The initialization circuit further has a
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`circuit 5 for internal voltage regulation and/or detection” which “has a first output 7
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`outputting a POWERON signal and a second output 8 supplying stabilized internal
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`supply voltages.” Id. at 3:61-65.
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`The initialization circuit also has an enable circuit 9 that receives the
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`command signals from command decoder 3 and the POWERON signal from the
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`voltage regulation/detection circuit 5. Id. at 4:9-14. The enable circuit provides “[a]n
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`enable signal CHIPREADY” “after the identification of a predetermined proper
`
`initialization sequence of the command signals.” Id. at Col. 4:14-18. “The enable
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`signal effects unlatching of control circuits 13 provided for proper operation of the
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`semiconductor memory device.” Id. at Col. 4:18-20.
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`Figure 2 shows an exemplary embodiment of an enable circuit according to
`
`the invention:
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`Ex. 1001, Fig. 2.
`
`
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`The enable circuit in Figure 2 contains three bistable multivibrator stages each
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`with set and reset inputs. Id. at Col. 4:24-28. “The command signals PRE, ARF,
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`MRS applied to the respective set inputs S” and “[t]he POWERON signal is applied
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`directly to the reset inputs R.” Id. at Col. 4:37-48. With these connections and the
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`additional logic described in Figure 2, “activation of the enable signal CHIPREADY
`
`at [] the output 12 . . . is generated only when a predetermined chronological
`
`initialization sequence of the command signals PRE, ARF and MRS and activation
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`of the POWERON signal to the logic level HIGH are detected.” Id. at Col. 4:49-55
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`(emphasis added). “Only then are the control circuits 13 unlatched on account of the
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`activation of the enable signal CHIPREADY.” Id. at Col. 4:55-58.
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`The ’589 Patent further illustrates the operation of the enable circuit in the
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`schematic time sequence diagram of Figure 3. Id. at Col. 4:59-63.
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`Ex. 1001, Fig. 3.
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`
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`The ’589 Patent describes four potential sequences A through D and their results.
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`Id. at 4:63-5:21. For example in case A, PRE activates before the POWERON and
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`because “the proper initialization sequence requires a waiting time before the first
`
`command,” CHIPREADY does not activate. Id. at 4:63-5:1. In case B, “the
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`chronological order of the activation of the signal AUTOREFRESH [ARF] . . . is
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`incorrect since the proper initialization sequence prescribes a previous
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`PRECHARGE [PRE] command.” Id. at 5:3-10. In case C, “a correct chronological
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`order of the commands PRECHARGE [PRE], AUTOREFRESH [ARF], MODE-
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`REGISTER-SET [MRS] is present,” and therefore “an enable signal CHIPREADY
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`at logic HIGH is now supplied.” Id. at Col. 5:10-16. Case D provides another
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`conceivable sequence that is allowed in this example. Id. at Col. 5:15-21.
`
`
`
`Based on these disclosed inventions, the ’589 Patent claims, inter alia, an
`
`apparatus and method for switching on, or unlatching the control circuits of (see,
`
`e.g., id. at Col. 4:18-20), a DRAM based on identification of an acceptable
`
`initialization sequence. The next section provides more detail regarding the
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`specific claims at issue.
`
`B. Challenged Claims
`
`The Petition challenges claims 1, 2, and 8-13 of the ’589 Patent. See Petition
`
`at 3. Claims 1 and 11 are independent claims. Claims 2 and 8-10 depend from
`
`claim 1, and claims 12 and 13 depend from claim 11. The full text of these claims is
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`provided in the Listing of Challenged Claims preceding this response with the same
`
`indices as the Petition for ease of reference. See Pet. at v-vii.
`
`The independent claims are reproduced below with emphasis on the particular
`
`limitations that will be addressed in particular in this Response:
`
`Claim 1 recites:
`
`1. A dynamic semiconductor memory device of a random access
`type, comprising:
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`an initialization circuit controlling a switching-on operation and
`supplying a supply voltage stable signal once a supply voltage has been
`stabilized after the switching-on operation,
`said initialization circuit having a control circuit for controlling
`operations and an enable circuit receiving the supply voltage stable
`signal and externally applied further command signals,
`said enable circuit outputting an enable signal after a
`predetermined proper initialization sequence of the externally applied
`further command signals being identified and the enable signal
`effecting an unlatching of said control circuit.
`
`Claim 11 recites:
`
`initializing a dynamic
`for
`improved method
`11. An
`semiconductor memory device of a random access type via an
`initialization circuit controlling a switching-on operation of the
`dynamic semiconductor memory device and of its circuit components,
`the improvement which comprises:
`supplying, via the initialization circuit, a supply voltage stable
`signal once a supply voltage has been stabilized after the switching-on
`operation of the dynamic semiconductor memory device; and
`supplying, via an enable circuit of the initialization circuit, an
`enable signal, the initialization circuit receiving the supply voltage
`stable signal and further command signals externally applied to the
`dynamic semiconductor memory device, after an identification of a
`predetermined proper initialization sequence of the further command
`signals the enable signal being generated and effecting an unlatching
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`of a control circuit provided for a proper operation of the dynamic
`semiconductor memory device.
`
`The emphasized limitations in each independent claim require that the
`
`claimed inventions, in accordance with the other requirements of each claim, output
`
`an enable signal after identifying a “proper initialization sequence” of “further
`
`command signals” and that enable signal “effecting an unlatching” of the control
`
`circuit. As addressed further herein, none of the Petitioner’s references disclose these
`
`limitations nor does the Petition articulate a motivation to modify any of the
`
`references to meet these limitations. Because the remaining challenged claims all
`
`depend from these independent claims, it necessarily follows that the challenged
`
`dependent claims are likewise not disclosed or rendered obvious by the asserted
`
`references.
`
`III. LEVEL OF ORDINARY SKILL
`
`Petitioner asserts that a person of ordinary skill in the art (“POSITA”) at the
`
`time of the ’589 patent would have had a “Bachelor’s degree in Electrical
`
`Engineering or Computer Science and two years of experience working in the field
`
`of system design using semiconductor memories, or a person with equivalent
`
`education, work, or experience in this field. More education could substitute for
`
`experience, and vice versa.” See Pet. at 21. Patent Owner’s expert believes that a
`
`POSITA would have (1) a bachelor’s degree in computer engineering or electrical
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`engineering with two to three years of circuit design experience, or (2) a master’s
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`degree in computer engineering or electrical engineering with one year of circuit
`
`design experience at the time of filing of the ’589 Patent. See Ex. 2001 at ¶104. For
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`the purposes of this trial, Patent Owner contends that both Petitioner’s and its own
`
`expert’s description of the POSITA are consistent.
`
`IV. CLAIM CONSTRUCTION
`
`Claim terms subject to inter partes review are to be “construed using the same
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`claim construction standard that would be used to construe the claim in a civil action
`
`under 35 U.S.C. 282(b), including construing the claim in accordance with the
`
`ordinary and customary meaning of such claim as understood by one of ordinary
`
`skill in the art and the prosecution history pertaining to the patent.” 37 C.F.R. §
`
`42.100(b).
`
`A.
`
`“Externally Applied Further Command Signals” (Cl. 1) /
`“Further Command Signals Externally Applied” (Cl. 11)
`
`Patent Owner asserts that the term “externally applied further command
`
`
`
`signals” (claim 1) or “further command signals externally applied” (claim 11)
`
`requires construction in order to properly evaluate the scope of the claims and the
`
`asserted art raised by Petitioner. Following applicable claim construction standards,
`
`we analyze the language of the claims, the specification, and the prosecution history
`
`from the perspective of a POSITA. There were no statements in the prosecution
`
`history that would affect the construction of “command signals,” (Ex. 2001 at ¶48),
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`Patent Owner’s Response
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`and we must look to how a POSITA would have understood this term in the claims
`
`and specification.
`
`Looking first to the claims (set forth in full above in Section II.B), the
`
`independent claims provide:
`
`Claim 1. A dynamic semiconductor memory device of a random access
`type, comprising:
`an initialization circuit . . .
`said initialization circuit having a control circuit . . . and an
`enable circuit receiving . . . externally applied further command signals,
`said enable circuit outputting an enable signal after a
`predetermined proper initialization sequence of the externally applied
`further command signals being identified . . . .
`
`initializing a dynamic
`improved method for
`Claim 11. An
`semiconductor memory device of a random access type via an
`initialization circuit . . . which comprises:
`. . .
`supplying, via an enable circuit of the initialization circuit, an
`enable signal, the initialization circuit receiving . . . further command
`signals externally applied to the dynamic semiconductor memory
`device, after an identification of a predetermined proper initialization
`sequence of the further command signals the enable signal being
`generated . . . .
`
`Ex.. 1001, Cls. 1 and 11 (emphasis added). Thus, as it relates to this term, the claims
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`require that the claimed initialization circuit (or method for operating the same)
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`receives externally applied further command signals and then outputs an enable
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`signal after identifying a proper initialization sequence of such further command
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`signals.
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`To further understand what is meant by these “further command signals” in
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`the claims, we next look to the specification and its description of the embodiments
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`of the invention. The ’589 Patent describes command signals, e.g., with reference to
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`Figure 1:
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`Ex. 1001, Fig. 1.
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`Specifically, the ’589 Patent states:
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`The initialization circuit has an input circuit 1, to whose input 2
`command and clock signals that are externally applied in reference to
`the semiconductor memory are provided. The command and clock
`signals are amplified and conditioned before being received by a
`command decoder 3 connected downstream of the input circuit 1 and at
`whose output 4, inter alia, the command signals PRE or PRECHARGE
`(preparation command
`for word
`line activation), ARF or
`AUTOREFRESH (refresh command) and MRS or MODE-REGISTER-
`SET (loading configuration register command) are output.
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`Ex. 1001 at Col. 3:51-61 (emphasis added). That is, the ’589 Patent teaches that
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`“command signals” are applied externally to the input of the initialization circuit,
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`and those command signals (after amplification, conditioning and decoding) are
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`used within the initialization circuit as “command signals” such as PRECHARGE
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`(PRE), AUTOREFRESH (ARF), and MODE-REGISTER-SET (MRS). See also Ex.
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`2001 at ¶¶108-10.
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`The “command signals” PRE, ARF, and MRS would have been well known
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`to a POSITA at the time of the invention, and indeed the ’589 Patent specifically
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`references them as commands that were described in the JEDEC standard, an
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`industry standard for SDRAM semiconductor memories. See, e.g., Ex. 1001 at Col.
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`1:22-61. Petitioner’s expert agrees that “[a] POSITA would have been familiar with
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`JEDEC memory standards like JESD 21-C.” Ex. 1003 at ¶93. In the JEDEC
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`standards, such as JESD 21-C, these command signals are specified as particular
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`patterns of individual signals. For example, the excerpt below from JESD 21-C
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`describes the patterns for each of the commands PRE, ARF, and MRS:
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`Ex. 1006 at 479-80 (annotated).
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`The JESD 21-C truth table above identifies the “Action” that occurs from the
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`“Current State” (here, Idle) based on the pattern of individual signals applied to an
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`SDRAM. The individual signals are S bar, RE bar, CE bar, W bar, and An. S is what
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`is typically called Chip Select or Chip Enable, RE is row enable or RAS, and CE is
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`Column Enable sometimes called CAS. See Ex. 1006 at 27, 29 (defining CAS/CE
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`(2.1.12), RAS/RE (2.1.49), S/Chip Select (2.1.54); see also Ex. 2001 at ¶110; Ex.
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`2002 at 36:5-10 (Petitioner’s expert agreeing). W is write enable, and An refers to
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`the address inputs. See Ex. 1006 at 27 and 30 (W (2.1.61) and A(n) (2.1.2)).
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`Depending on the patterns of these various signals, different “Actions” are to
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`occur according to the standard, which the ’589 Patent refers to as “command
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`signals.” For example, the Actions highlighted within the red rectangles above
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`correspond to the specific commands discussed in the ’589 patent. That is,
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`“NOP4” corresponds to PRE or PRECHARGE according to footnote 4, Auto-refresh
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`corresponds to ARF or AUTOREFRESH, and Mode Register Access corresponds
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`to MRS or MODE-REGISTER-SET. Ex. 2001 at ¶110; see also Ex. 2002 at 37:12-
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`38:15, 39:8-40:3 (Petitioner’s expert discussing the actions corresponding to ARF
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`and MRS).
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`Accordingly, a POSITA would have understood that the command signals
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`described in the ’589 Patent (with PRE, ARF, and MRS given as examples) are not
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`the individual signals that comprise the pattern for those commands. Rather, one of
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`ordinary skill in the art would understand that “externally applied further command
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`signal” are “a pattern of individual external signals that as a group represent a
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`command.” Ex. 2001 at ¶111. And, thus, “externally applied further command
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`signals” or “further command signals externally applied” are “a plurality of
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`command signals.” Ex. 2001 at ¶112.
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`This distinction is important for evaluating the challenged claims and the prior
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`art as discussed in more detail below because identifying the appropriate sequence
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`of command signals presents different issues than a sequence of the constituent
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`individual signals. In particular, different command signals have different patterns
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`of the individual signals but they include those same individual signals. For example,
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`as shown in the table above, all of the different commands depend on the values of
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`S/chip select, RE/RAS, CE/CAS, and W/Write at a particular point in time. As
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`Petitioner’s expert has acknowledged:
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`14 Q. Okay. Yeah. The -- whichever command you
`15 have, it's going to be based on a -- a pattern of
`16 signals, right?
`17 A. Yes.
`18 Q. And both of those commands, Auto-Refresh
`19 and Mode Register, they require -- as part of the
`20 pattern of signals, it includes a RAS and CAS
`21 signal, right?
`22 A. Yes. They -- they require -- they -- in
`23 this case they require those to both be low.
`Ex. 2002 at 40:14-23. As Petitioner’s expert further explained:
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`21 . . . I think what
`22 you're asking is, would you expect AUTOREFRESH and
`23 MODE-REGISTER-SET to be asserted simultaneously.
`24 And you -- one wouldn't. One would expect the
`25 decoder would say, okay, this is AUTOREFRESH action
`1 that's occurring; and different pattern would cause
`2 MODE-REG