Filed on behalf of: Polaris Innovations Limited
`
`By: David T. DeZern
`Registration No. 60,117
`NELSON BUMGARDNER CONROY P.C.
`2727 N. Harwood Street, Suite 250
`Dallas, TX 75201
`Telephone: (214) 446-4950
`Email: david@nelbum.com
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`________________
`
`XILINX, INC.,
`
`Petitioner
`
`v.
`
`POLARIS INNOVATIONS LIMITED,
`
`Patent Owner.
`
`________________
`
`Case IPR2023-00516
`
`U.S. Patent 6,157,589
`________________
`
`
`PATENT OWNER’S PRELIMINARY RESPONSE
`
`
`
`
`
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`

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`TABLE OF CONTENTS
`
`I.
`II.
`
`INTRODUCTION ........................................................................................... 1
`THE ’589 PATENT AND THE CHALLENGED CLAIMS .......................... 3
`A. Overview of the ’589 Patent .................................................................. 3
`B.
`Challenged Claims ................................................................................ 9
`III. LEVEL OF ORDINARY SKILL ..................................................................11
`IV. CLAIM CONSTRUCTION ..........................................................................11
`V. APPLICABLE LEGAL STANDARDS ........................................................12
`A. Anticipation .........................................................................................12
`B. Obviousness .........................................................................................13
`1.
`Claims cannot be found obvious if an element is absent. ..............14
`2.
`A petition must address the Graham factors. .................................15
`3.
`A petition must provide articulated reasoning with rational
`underpinning to combine and/or modify references. .....................15
`VI. SUMMARY OF THE PRIOR ART REFERENCES ....................................16
`A. Overview of Primary Reference: Kocis ..............................................16
`B. Overview of Primary Reference: Lee .................................................18
`C. Overview of Secondary References: ...................................................21
`1.
`JESD 21-C ......................................................................................21
`2.
`Iketani .............................................................................................23
`VII. THE PETITION DOES NOT ESTABLISH A REASONABLE
`LIKELIHOOD OF SUCCESS ......................................................................24
`A. Ground 1: Kocis Does Not Disclose At Least One Limitation of Each
`Independent Claim. .............................................................................24
`B. Ground 2: The Petition Fails to Demonstrate Obviousness Over Kocis
`in Combination with JESD 21-C for Claims 2, 8, 10, and 12. ............30
`C. Ground 3A/3B: Lee Does Not Disclose At Least One Limitation of
`Each Independent Claim. ....................................................................32
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`Patent Owner’s Preliminary Response
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`F.
`
`E.
`
`D. Ground 4: The Combination of Lee with Iketani Does Not Cure the
`Deficiencies of Lee. .............................................................................36
`Ground 5: The Petition Fails to Demonstrate Obviousness Over Lee in
`Combination with JESD 21-C for Claims 2, 8, 10, and 12. ................37
`Ground 6: The Petition Fails to Demonstrate Obviousness Over Lee in
`Combination with Iketani and JESD 21-C for Claims 2, 8, 10, and 12.
` .............................................................................................................38
`G. Ground 7: The Petition Fails to Demonstrate Obviousness Over Lee in
`Combination with Kocis for Claims 9 and 13. ....................................39
`H. Ground 8: The Petition Fails to Demonstrate Obviousness Over Lee in
`Combination with Iketani and Kocis for Claims 9 and 13. .................39
`VIII. PATENT OWNER’S FINAL COMMENTS ................................................39
`IX. CONCLUSION ..............................................................................................40
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`Patent Owner’s Preliminary Response
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`iii
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`TABLE OF AUTHORITIES
`
`Cases
`CFMT, Inc. v. YieldUp Int’l Corp.,
` 349 F.3d 1333 (Fed. Cir. 2003) ............................................................................14
`
`Continental Can Co. USA, Inc. v. Monsanto Co.,
` 948 F.2d 1264 (Fed. Cir. 1991) ............................................................................13
`
`Cook Inc. v. Medtronic Vascular, Inc.,
` Case No. IPR2018-01570 (P.T.A.B. March 4, 2019) .................................... 32, 35
`
`Eizo Corp. v. Barco N.V.,
` Case No. IPR2014-00358 (P.T.A.B. 2014) ..........................................................15
`
`EMC Corporation v. Intellectual Ventures I LLC,
` Case No. IPR2017-00429 (P.T.A.B. 2017) ............................................................ 2
`
`Garmin Int’l, Inc. v. Patent of Cuozzo Speed Techs. LLC,
` Case No. IPR2012-00001 (P.T.A.B. 2013) ..........................................................14
`
`Graham v. John Deere Co.,
` 383 U.S. 1 (1966) ........................................................................................... 14, 15
`
`Hansgirg v. Kemmer,
` 102 F.2d 212 (CCPA 1939) ..................................................................................13
`
`In re Arkley,
` 455 F.2d 586 (CCPA 1972) ..................................................................................12
`
`In re Kahn,
` 441 F.3d 977 (Fed. Cir. 2006) ..............................................................................15
`
`In re Magnum Oil Tools Int’l Ltd.,
` 829 F.3d 1364 (Fed. Cir. 2016) ..................................................................... 32, 35
`
`In re Oelrich,
` 666 F.2d 578 (CCPA 1981) ..................................................................................13
`
`Patent Owner’s Preliminary Response
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`In re Rijckaert,
` 9 F.3d 1531 (Fed. Cir. 1993) ................................................................................14
`
`In re Royka,
` 490 F.2d 981 (C.C.P.A. 1974) ..............................................................................14
`
`InTouch Techs., Inc. v. VGo Comm’ns., Inc.,
` 751 F.3d 1327 (Fed. Cir. 2014) ............................................................................14
`
`KSR Int’l Co. v. Teleflex Inc.,
` 550 U.S. 398 (2007) ....................................................................................... 14, 15
`
`LG Elecs., Inc. v. Cellular Commc’ns Equip. LLC,
` Case No. IPR2016-00197 (P.T.A.B. 2016) ..........................................................16
`
`N.V. v. Abbott Labs.,
` 512 F.3d 1363 (Fed. Cir. 2008) ............................................................................15
`
`Net MoneyIN, Inc. v. VeriSign, Inc.,
` 545 F.3d 1359 (Fed. Cir. 2008) ............................................................................13
`
`Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc.,
` 200 F.3d 795 (Fed. Cir. 1999) ..............................................................................12
`
`Wellman, Inc. v. Eastman Chem. Co.,
` 642 F.3d 1355 (Fed. Cir. 2011) ............................................................................11
`
`Xerox Corp. v. Bytemark, Inc.,
` Case No. IPR2022-00624 (P.T.A.B. 2022 ............................................................31
`
`Statutes, Rules and Regulations
`35 U.S.C. § 103 ........................................................................................................14
`
`35 U.S.C. § 103(a) ...................................................................................................13
`
`35 U.S.C. § 313 .......................................................................................................... 1
`
`37 C.F.R. § 42.107 ..................................................................................................... 1
`
`Patent Owner’s Preliminary Response
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`37 C.F.R. § 42.108(c) ...............................................................................................12
`
`
`Other Authorities
`
`Office Patent Trial Practice Guide, 77 Fed. Reg. 48,756 (Aug. 14, 2012) .............12
`
`
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`I.
`
`INTRODUCTION
`
`Pursuant to 35 U.S.C. § 313 and 37 C.F.R. § 42.107, Polaris Innovations
`
`Limited (“Patent Owner”) submits this Preliminary Response to Xilinx, Inc.’s
`
`(“Petitioner”) Petition for Inter Partes Review (“Petition,” Paper 2), challenging
`
`Claims 1, 2, and 8-13 of U.S. Patent 6,157,589 (the “’589 Patent”) (Ex. 1001).
`
`The ’589 Patent concerns methods and circuitry for powering on dynamic
`
`random access memories (“DRAM”). The patent describes and claims particular
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`circuitry and methods of operating such circuitry in order to initialize and unlatch a
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`DRAM for operation.
`
`Petitioner alleges invalidity on eight or nine different grounds (numbered one
`
`through eight including both 3A and 3B). The grounds are based on four different
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`references in various combinations. Each of the primary references, Kocis and Lee1,
`
`fail to disclose or teach at least one limitation of the independent claims. The other
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`references fail to cure these deficiencies. Petitioner’s approach including the number
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`of grounds, alternative readings of the same circuitry, assertion that both primary
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`references are anticipating but also in need of numerous combinations to support
`
`
`1 The Japanese counterpart of Lee was considered by the Examiner during
`examination of the ’589 Patent. See infra Section VI.B.
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`obviousness, and the sheer number of words2 expended indicate the weakness of
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`Petitioner’s invalidity case. Petitioner picks and chooses circuits and signals from
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`prior art related to DRAM and attempts to knit them together using the asserted
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`claims as a roadmap. This is of course improper.
`
`
`
`The two primary references fail to disclose key limitations of the independent
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`claims. Kocis does not disclose any sequential logic like that described in the ’589
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`Patent’s specification and fails to disclose the independent claim’s requirements to
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`generate an enable signal based on a predetermined sequence of command signals.
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`Lee fails to disclose an enable signal that unlatches the control circuit for operation
`
`in a DRAM as required by the independent claims and instead describes a reset
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`signal provided as a back up for initializing a circuit when prior art power signals
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`malfunction. Petitioner’s attempts to overcome these flaws with conclusory
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`assertions repeated by its expert are insufficient to meet its burden to show
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`anticipation or obviousness, and the Board should not institute IPR.
`
`
`2 Petitioner’s certification under 37 C.F.R. § 42.24(d) asserts that the petition
`contains 13,975 words—25 less than the limit—while removing the space in
`exhibit cites (e.g., EX1001 of which there are 227), a practice to circumvent word
`limits that has been found to violate the Board’s rules. See EMC Corporation v.
`Intellectual Ventures I LLC, IPR2017-00429, Paper 11 at 27–29 (PTAB July 5,
`2017) (“Petitioner’s use of atypical citations amounts to formatting tricks designed
`to avoid the word count limit for petitions set forth in our rules.”).
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`Patent Owner’s Preliminary Response
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`II. THE ’589 PATENT AND THE CHALLENGED CLAIMS
`
`A. Overview of the ’589 Patent
`
`The ’589 Patent “relates to a dynamic semiconductor memory device of the
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`random access type (DRAM/SDRAM) having an initialization circuit which
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`controls a switching-on operation of the semiconductor memory device.” Ex. 1001
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`at 1:9-13. “The invention [] relates to a method for initializing such a dynamic
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`semiconductor memory device, and [] the use of an enable circuit, that supplies an
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`enable signal, for controlling the switching-on operation of the dynamic
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`semiconductor memory device.” Id. at 1:16-21.
`
`The
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`’589 Patent explains
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`that “during
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`the switch-on operation
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`(‘POWERUP’)” for “SDRAM semiconductor memories according to the JEDEC
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`standard” “the internal control circuits” must be “held in a defined desired state, in
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`order to prevent undesirable activation” “or uncontrolled activation.” Id. at 1:22-30.
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`“The solution to the problem turns out to be difficult on account of a fundamental
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`unpredictability of the time characteristic of the supply voltage and of the voltage
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`level or levels at the external control inputs during the switch-on operation of the
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`semiconductor memory.” Id. at 1:30-35.
`
`The ’589 patent explains that “[a]ccording to the specifications of the
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`manufacturer an SDRAM component should ignore all commands which are present
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`chronologically before a defined initialization sequence.” Id. at Col. 1:35-38. “The
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`sequence consists of predetermined commands that must be applied in a defined
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`chronological order.” Id. at Col. 1:38-40. The ’589 Patent provides an example of “a
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`recommended initialization sequence” from the JEDEC standard. Id. at 1:43-61. The
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`’589 Patent explains that “[a]fter the identification of such a defined initialization
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`sequence, the memory module is normally in a so-called IDLE state, that is to say it
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`is precharged and prepared for proper operation.” Id. at Col. 1:62-65. “In the case of
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`SDRAM semiconductor memory modules that have been disclosed to date,” all the
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`control circuits of the component have been unlatched only with the POWERON
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`signal.” Id. at Col. 1:65-2:1 (emphasis added). “The signal POWERON is active if
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`the internal supply voltages have reached the necessary values that are necessary for
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`the proper operation of the component.” Id. at Col. 2:1-4.
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`The ’589 Patent addresses these issues by providing “an initialization circuit
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`controlling a switching-on operation.” Id. at Col. 2:15-21. The initialization circuit
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`includes an “enable circuit outputting an enable signal after a predetermined proper
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`initialization sequence . . . and the enable signal effecting an unlatching of the control
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`circuit.” Id. at Col. 2:20-28.
`
`The ’589 Patent provides a block diagram of an initialization circuit according
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`to the invention in Figure 1:
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`Ex. 1001, Fig. 1.
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`
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`“The initialization circuit has an input circuit 1, to whose input 2 command
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`and clock signals [] are externally applied.” Id. at 3:51-53. “The command and clock
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`signals are amplified and conditioned before being received by a command decoder
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`3 . . . at whose output 4, inter alia, the command signals PRE or PRECHARGE
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`(preparation command for word line activation), ARF or AUTOREFRESH (refresh
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`command) and MRS or MODE-REGISTER-SET (loading configuration register
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`command) are output.” Id. at 3:54-61. “The initialization circuit further has a
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`circuit 5 for internal voltage regulation and/or detection” which “has a first output 7
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`outputting a POWERON signal and a second output 8 supplying stabilized internal
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`supply voltages.” Id. at 3:61-65.
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`The initialization circuit also has an enable circuit 9 that receives the
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`command signals from command decoder 3 and the POWERON signal from the
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`voltage regulation/detection circuit 5. Id. at 4:9-14. The enable circuit provides “[a]n
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`enable signal CHIPREADY” “after the identification of a predetermined proper
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`initialization sequence of the command signals.” Id. at Col. 4:14-18. “The enable
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`signal effects unlatching of control circuits 13 provided for proper operation of the
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`semiconductor memory device.” Id. at Col. 4:18-20.
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`Figure 2 shows an exemplary embodiment of an enable circuit according to
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`the invention:
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`Ex. 1001, Fig. 2.
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`
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`The enable circuit in Figure 2 contains three bistable multivibrator stages each
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`with set and reset inputs. Id. at Col. 4:24-28. “The command signals PRE, ARF,
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`MRS applied to the respective set inputs S” and “[t]he POWERON signal is applied
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`directly to the reset inputs R.” Id. at Col. 4:37-48. With these connections and the
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`additional logic described in Figure 2, “activation of the enable signal CHIPREADY
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`at [] the output 12 . . . is generated only when a predetermined chronological
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`initialization sequence of the command signals PRE, ARF and MRS and activation
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`of the POWERON signal to the logic level HIGH are detected.” Id. at Col. 4:49-55
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`(emphasis added). “Only then are the control circuits 13 unlatched on account of the
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`activation of the enable signal CHIPREADY.” Id. at Col. 4:55-58.
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`The ’589 Patent further illustrates the operation of the enable circuit in the
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`schematic time sequence diagram of Figure 3. Id. at Col. 4:59-63.
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`Ex. 1001, Fig. 3.
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`
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`The ’589 Patent describes four potential sequences A through D and their results.
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`Id. at 4:63-5:21. For example in case A, PRE activates before the POWERON and
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`because “the proper initialization sequence requires a waiting time before the first
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`command,” CHIPREADY does not activate. Id. at 4:63-5:1. In case B, “the
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`chronological order of the activation of the signal AUTOREFRESH [ARF] . . . is
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`incorrect since the proper initialization sequence prescribes a previous
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`PRECHARGE [PRE] command.” Id. at 5:3-10. In case C, “a correct chronological
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`order of the commands PRECHARGE [PRE], AUTOREFRESH [ARF], MODE-
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`REGISTER-SET [MRS] is present,” and therefore “an enable signal CHIPREADY
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`at logic HIGH is now supplied.” Id. at Col. 5:10-16. Case D provides another
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`conceivable sequence that is allowed in this example. Id. at Col. 5:15-21.
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`
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`Based on these disclosed inventions, the ’589 Patent claims, inter alia, an
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`apparatus and method for switching on, or unlatching the control circuits of (see,
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`e.g., id. at Col. 4:18-20), a DRAM based on identification of an acceptable
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`initialization sequence. The next section provides more detail regarding the
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`specific claims at issue.
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`B. Challenged Claims
`
`The Petition challenges claims 1, 2, and 8-13 of the ’589 Patent. See Petition
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`at 3. Claims 1 and 11 are independent claims. Claims 2 and 8-10 depend from claim
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`1, and claims 12 and 13 depend from claim 1.
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`The independent claims are reproduced below with emphasis on the particular
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`limitations that are at issue in this Preliminary Response:
`
`Claim 1 recites:
`
`1. A dynamic semiconductor memory device of a random access
`type, comprising:
`an initialization circuit controlling a switching-on operation and
`supplying a supply voltage stable signal once a supply voltage has been
`stabilized after the switching-on operation,
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`said initialization circuit having a control circuit for controlling
`operations and an enable circuit receiving the supply voltage stable
`signal and externally applied further command signals,
`said enable circuit outputting an enable signal after a
`predetermined proper initialization sequence of the externally applied
`further command signals being identified and the enable signal
`effecting an unlatching of said control circuit.
`
`
`Claim 11 recites:
`
`initializing a dynamic
`for
`improved method
`11. An
`semiconductor memory device of a random access type via an
`initialization circuit controlling a switching-on operation of the
`dynamic semiconductor memory device and of its circuit components,
`the improvement which comprises:
`supplying, via the initialization circuit, a supply voltage stable
`signal once a supply voltage has been stabilized after the switching-on
`operation of the dynamic semiconductor memory device; and
`supplying, via an enable circuit of the initialization circuit, an
`enable signal, the initialization circuit receiving the supply voltage
`stable signal and further command signals externally applied to the
`dynamic semiconductor memory device, after an identification of a
`predetermined proper initialization sequence of the further command
`signals the enable signal being generated and effecting an unlatching
`of a control circuit provided for a proper operation of the dynamic
`semiconductor memory device.
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`The emphasized limitations in each independent claim require that the
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`claimed inventions, in accordance with the other requirements of each claim, output
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`an enable signal after identifying a “proper initialization sequence” of “further
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`command signals” and that enable signal “effecting an unlatching” of the control
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`circuit. As addressed further herein, none of the Petitioner’s references disclose these
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`limitations nor does the Petition articulate a motivation to modify any of the
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`references to meet these limitations. Because the remaining challenged claims all
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`depend from these independent claims, should the Board accept Patent Owner’s
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`arguments that trial should not be instituted on these claims, it necessarily follows
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`that trial should not be instituted on the dependent claims.
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`III. LEVEL OF ORDINARY SKILL
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`For the limited purpose of this Preliminary Response, Patent Owner does not
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`contest Petitioner’s definition of a person of ordinary skill in the art, but it reserves
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`the right to do so in the event that trial is instituted.
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`IV. CLAIM CONSTRUCTION
`
`Patent Owner submits that the Board need not construe any claim term in a
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`particular manner to arrive at the conclusion that the Petition is substantively
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`deficient. See Wellman, Inc. v. Eastman Chem. Co., 642 F.3d 1355, 1361 (Fed. Cir.
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`2011) (“need only be construed ‘to the extent necessary to resolve the controversy’”
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`(quoting Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir.
`
`1999))).
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`V. APPLICABLE LEGAL STANDARDS
`
`The Board may only grant a petition for inter partes review where “the
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`information presented in the petition … shows that there is a reasonable likelihood
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`that the petitioner would prevail with respect to at least 1 of the claims challenged
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`in the petition.” 35 U.S.C. § 314(a); 37 C.F.R. § 42.108(c). Petitioner bears the
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`burden of showing that this statutory threshold has been met. See Office Patent Trial
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`Practice Guide, 77 Fed. Reg. 48,756 (Aug. 14, 2012) (“The Board … may institute
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`a trial where the petitioner establishes that the standards for instituting the requested
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`trial are met ….”).
`
`A. Anticipation
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`“[R]ejections under 35 U.S.C. § 102 are proper only when the claimed subject
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`matter is identically disclosed or described in ‘the prior art. . . .’ The [prior art]
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`reference must clearly and unequivocally disclose the claimed [invention] or direct
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`those skilled in the art to the [invention] without any need for picking, choosing, and
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`combining various disclosures not directly related to each other by the teachings of
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`the cited reference.” In re Arkley, 455 F.2d 586, 587 (CCPA 1972). Thus, “unless a
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`reference discloses within the four corners of the document not only all of the
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`limitations claimed but also all of the limitations arranged or combined in the same
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`way as recited in the claim, it cannot be said to prove prior invention of the thing
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`claimed and, thus, cannot anticipate under 35 U.S.C. § 102.” Net MoneyIN, Inc. v.
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`VeriSign, Inc., 545 F.3d 1359, 1371 (Fed. Cir. 2008).
`
`“To serve as an anticipation when the reference is silent about the asserted
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`inherent characteristic, such gap in the reference may be filled with recourse to
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`extrinsic evidence. Such evidence must make clear that the missing descriptive
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`matter is necessarily present in the thing described in the reference, and that it would
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`be so recognized by persons of ordinary skill.” Continental Can Co. USA, Inc. v.
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`Monsanto Co., 948 F.2d 1264, 1268 (Fed. Cir. 1991) (citing In re Oelrich, 666 F.2d
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`578, 581 (CCPA 1981)). “Inherency, however, may not be established by
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`probabilities or possibilities. The mere fact that a certain thing may result from a
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`given set of circumstances is not sufficient.” Id. at 1268–69 (quoting Hansgirg v.
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`Kemmer, 102 F.2d 212, 214 (CCPA 1939)).
`
`B. Obviousness
`
`Section 103 of the Patent Act provides that “[a] patent may not be obtained
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`. . . if the differences between the subject matter sought to be patented and the prior
`
`art are such that the subject matter as a whole would have been obvious at the time
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`the invention was made to a person having ordinary skill in the art to which said
`
`subject matter pertains.” 35 U.S.C. § 103(a). The obviousness analysis requires
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`several threshold inquiries: the level of ordinary skill in the art must be established;
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`the scope and content of the prior art must be determined; and any differences
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`between the prior art and the claims at issue must be ascertained. Graham v. John
`
`Deere Co., 383 U.S. 1, 17–18 (1966).
`
`1. Claims cannot be found obvious if an element is absent.
`If a single element of the claim is absent from the prior art, the claim cannot
`
`be considered obvious. See CFMT, Inc. v. YieldUp Int’l Corp., 349 F.3d 1333, 1342
`
`(Fed. Cir. 2003) (“Obviousness requires a suggestion of all limitations in a claim.”)
`
`(citing In re Royka, 490 F.2d 981, 985 (C.C.P.A. 1974)); In re Rijckaert, 9 F.3d
`
`1531, 1534 (Fed. Cir. 1993) (reversing obviousness rejection where prior art did not
`
`teach or suggest all claim limitations); Garmin Int’l, Inc. v. Patent of Cuozzo Speed
`
`Techs. LLC, IPR2012-00001, Paper 15 at 15 (PTAB Jan. 9, 2013) (refusing to
`
`institute an inter partes review under 35 U.S.C. § 103 where prior art did not disclose
`
`all claim limitations).
`
`
`
`Additionally, it is improper to use the challenged claim as a roadmap to piece
`
`together disparate disclosure using hindsight bias. See InTouch Techs., Inc. v. VGo
`
`Comm’ns., Inc., 751 F.3d 1327, 1351 (Fed. Cir. 2014) (reversing obviousness where
`
`“[i]t appears that [the expert] relied on the [] patent itself as her roadmap for putting
`
`what she referred to as pieces of a ‘jigsaw puzzle’ together.”); KSR Int’l Co. v.
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`Teleflex Inc., 550 U.S. 398, 421 (2007) (“A factfinder should be aware, of course, of
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`the distortion caused by hindsight bias and must be cautious of arguments reliant
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`upon ex post reasoning.”).
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`2. A petition must address the Graham factors.
`Obviousness is resolved on a number of factual determinations “including (1)
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`the scope and content of the prior art, (2) any differences between the claimed subject
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`matter and the prior art, and (3) the level of ordinary skill in the art.” See Graham,
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`383 U.S. at 17-18. Petitions for inter partes reviews “must address the Graham
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`factors.” Eizo Corp. v. Barco N.V., IPR2014-00358, Paper 11 at 29-30 (PTAB July
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`23, 2014).
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`3. A petition must provide articulated reasoning with rational
`underpinning to combine and/or modify references.
`The conclusion of obviousness based on a combination of references must
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`also be supported with explicit analysis of a reason to combine those references. KSR
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`Int’l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). The Federal Circuit has stated
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`that such reasons must be more than “mere conclusory statements; instead, there
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`must be some articulated reasoning with some rational underpinning to support the
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`legal conclusion of obviousness.” In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006);
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`accord Innogenetics, N.V. v. Abbott Labs., 512 F.3d 1363, 1374 (Fed. Cir. 2008)
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`(agreeing with the district court’s reasoning that “some kind of motivation must be
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`shown from some source, so that the jury can understand why a person of ordinary
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`skill would have thought of either combining two or more references or modifying
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`one to achieve the patented method”); see also LG Elecs., Inc. v. Cellular Commc’ns
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`Equip. LLC, IPR2016-00197, Paper 7 at 7-11 (PTAB April 29, 2016) (faulting a
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`petition’s obviousness analysis for lack of sufficient articulated reasons with rational
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`underpinnings for modifying references to achieve particular elements required in
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`the claims).
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`VI. SUMMARY OF THE PRIOR ART REFERENCES
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`Petitioner requests relief on eight or nine grounds. Petition at 3 (grounds 1
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`through 8 with 3A and 3B). The Kocis or Lee reference serves as the primary
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`reference in each of these grounds, and the two references are used together for
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`dependent claims in one ground (#7). Id. These two primary references and the other
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`secondary references are summarized below.
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`A. Overview of Primary Reference: Kocis
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`Petitioner relies on U.S. Patent No. 5,559,753 to Kocis as the primary
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`reference in Grounds 1 and 2, and the Petition combines Kocis with Lee in Ground 7.
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`See, e.g., Petition at 3. Kocis “relates to a system for preventing contention on the
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`memory bus between conflicting data signals from two or more DRAM banks.” Ex.
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`1004 at Col. 1:12-15.
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`Kocis describes “a circuit for disabling DRAM data output signals, which
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`counts the number of RAS (and/or CAS) signals received by the DRAM circuit.” Id.
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`at Col. 3:42-44. “When seven RAS signals have been detected after a threshold
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`voltage is achieved, the DRAM data output lines are enabled.” Id. at 3:44-47.
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`Petitioner relies on Figure 5 which Kocis describes as “a circuit. . . for
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`disabling DRAM data output drivers until power supply voltages are satisfactory and
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`all enable conditions are met.” Id. at Col. 4:23-26.
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`Ex. 1004, Fig. 5.
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`Figure 5 includes “a plurality of tri-state output drivers 31, 32, 33, 34, 35 for driving
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`data lines D0-Dn of a DRAM circuit 100, a counter 50, and an AND gate 55.” Id. at
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`4:33-38. “[T]he tri-state buffers transmit the associated data signal only when
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`enabled by the ENABLE line” emanating from AND gate 55. Id. at 4:60-61. “The
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`AND gate 55 receives the following input signals in the preferred embodiment: (1)
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`an inverted Pwrup signal from the output of the voltage detection circuit of FIG. 4A;
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`(2) an output signal (Keep Off) from counter 50; and (3) other enable signals.” Id. at
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`5:3-7.
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`In Kocis’s preferred embodiment, “the counter 50 counts the number of RAS
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`signals received from the memory controller 8 (of FIG. 1).” Id. at Col. 5:40-42. The
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`counter generates “an output signal (Keep Off)” after counting a number of RAS
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`and/or CAS signals. Id. at Col. 5:42-49. The “Keep Off” signal is supplied to AND
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`gate 55 which also receives “an inverted Pwrup signal” and “other enable signals.”
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`Id. at Col. 5:1-8. The tri-state buffers 31-35 are disabled while “AND gate 55 keeps
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`the ENABLE line low.” Id. at Col. 5:22-28. Notably, for purposes of this Preliminary
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`Response, neither the ENABLE signal nor the “Keep Off” signal is dependent on
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`the sequence in which any other signals are received. The “Keep Off” signal counts
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`the number of a particular signal, but not the sequence, and the sequence in which
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`the AND gate 55 providing the ENABLE line (or any AND gate) receives its inputs
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`does not have any effect on its output.
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`B. Overview of Primary Reference: Lee
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`Petitioner relies on U.S. Patent No. 5,774,402 to Lee as the primary reference
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`in six or seven of the grounds it asserts (#3A/3B through 8). See, e.g., Petition at 3.
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`The Japanese counterpart to Lee (JP 9-106668 to Tetsuka) is cited on the face of the
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`’589 Patent and was marked as considered by the Examiner. See Petition at 73; Ex.
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`1002 at 75; 93-98.
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`Lee “relates generally to initialization circuits for semiconductor memory
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`devices and more particularly to initialization circuits which operate in response to
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`an external control signal,
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`thereby providing reliable
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`initialization when
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`conventional power supply reset circuits malfunction.” Ex. 1005 at 1:11-16
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`(emphasis added).
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`Lee describes how “[t]he typical power on reset circuit operates by sensing
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`the level of the power supply voltage VCC and generating an initialization signal for
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`a predetermined length of time when the power supply voltage reaches a
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`predetermined level.” Id. at 1:25-29; see also id. at 1:30-2:3. Lee identifies “[a]
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`problem with” such a ty