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`Preface
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`xiii
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`Chapter 12 discusses in depth the different memory classes and their implementation.
`Whenever large amounts of data storage are needed, the digital designer resorts to special cir(cid:173)
`cuit modules, called memories. Semiconductor memories achieve very high storage density
`by compromising on some of the fundamental properties of digital gates. Instrumental in the
`design of reliable and fast memories is the implementation of the peripheral circuitry, such as
`the decoders, sense amplifiers, drivers, and control circuitry, which are extensively covered.
`Finally, as the primary issue in memory design is to ensure that the device works consis(cid:173)
`tently under all operating circumstances, the chapter concludes with a detailed discussion of
`memory reliability. This chapter as well as the previous one are optional for undergraduate
`courses.
`
`Acknowledgments
`The authors would like to thank all those who contributed to the emergence, creation and correc(cid:173)
`tion of this manuscript. First of all, thanks to all the graduate students that helped over the years
`to bring the text to where it is today. Thanks also to the students of the eecsl41 and eecs241
`courses at Berkeley and the 6.374 course at MIT, who suffered through many of the experimen(cid:173)
`tal class offerings based on this book. The feedback from instructors, engineers, and students
`from all over the world has helped tremendously in focusing the directions of this new edition,
`and in fine-tuning the final text. The continuous stream of e-mails indicate to us that we are on
`the right track.
`In particular, we would like to acknowledge the contributions of Mary-Jane Irwin, Vijay
`Narayanan, Eby Friedman, Fred Rosenberger, Wayne Burleson, Sekhar Borkar, Ivo Bolsens,
`Duane Boning, Olivier Franza, Lionel Kimerling, Josie Ammer, Mike Sheets, Tufan Karalar,
`Huifang Qin, Rhett Davis, Nathan Chan, Jeb Durant, Andrei Vladimirescu, Radu Zlatanovici,
`Yasuhisa Shimazaki, Fujio Ishihara, Dejan Markovic, Vladimir Stojanovic, SeongHwan Cho,
`James Kao, Travis Simpkins, Siva Narendra, James Goodman, Vadim Gutnik, Theodoros Kon(cid:173)
`stantakopoulos, Rex Min, Vikas Mehrotra, and Paul-Peter Sotiriadis. Their help, input, and feed(cid:173)
`back are greatly appreciated. Obviously, we remain thankful to those who helped create and
`develop the first edition.
`I am extremely grateful to the staff at Prentice Hall, who have been instrumental in turning
`a rough manuscript into an enjoyable book. First of all, I would like to acknowledge the help and
`constructive feedback of Tom Robbins, Publisher, Daniel Sandin, Production Editor, and David
`George, Managing Editor. A special word of thanks to Brenda Vanoni at Berkeley, for her invalu(cid:173)
`able help in the copy editing and the website creation process. The web expertise of Carol Sitea
`came in very handy as well.
`I would like to highlight to role of computer aids in developing this manuscript. All drafts
`were completely developed on the FrameMaker publishing system (Adobe Systems). Graphs
`were mostly created using MATLAB. Microsoft Frontpage is the tool of choice for the web-page
`creation. For circuit simulations, we used HSPICE (Avant!). All layouts were generated using
`the Cadence physical design suite.
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`Contents
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`4.5
`
`4.6
`4.7
`
`SPICE Wire Models
`4.5.1 Distributed re Lines in SPICE
`4.5.2 Transmission Line Models in SPICE
`4.5.3 Perspective: A Look into the Future
`Summary
`To Probe Further
`References
`
`Part2
`
`A Circuit Perspective
`
`5.4
`
`5.5
`
`Chapters The CMOS Inverter
`5.1
`Introduction
`5.2
`The Static CMOS Inverter-An Intuitive Perspective
`5.3
`Evaluating the Robustness of the CMOS Inverter:
`The Static Behavior
`5.3.1 Switching Threshold
`5.3.2 Noise Margins
`5.3.3 Robustness Revisited
`Performance of CMOS Inverter: The Dynamic Behavior
`5.4.1 Computing the Capacitances
`5.4.2 Propagation Delay: First-Order Analysis
`5.4.3 Propagation Delay from a Design Perspective
`Power, Energy, and Energy Delay
`5.5.1 Dynamic Power Consumption
`5.5.2 Static Consumption
`5.5.3 Putting It All Together
`5.5.4 Analyzing Power Consumption Using SPICE
`Perspective: Technology Scaling and its Impact
`on the Inverter Metrics
`Summary
`To Probe Further
`References
`Chapter6 Designing Combinational Logic Gates in CMOS
`6.1
`Introduction
`6.2
`Static CMOS Design
`6.2.1 Complementary CMOS
`6.2.2 Ratioed Logic
`6.2.3 Pass-Transistor Logic
`6.3 Dynamic CMOS Design
`6.3.1 Dynamic Logic: Basic Principles
`6.3.2 Speed and Power Dissipation of Dynamic Logic
`
`5.6
`
`5.7
`5.8
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`xvii
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`170
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`180
`180
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`184
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`188
`191
`193
`194
`199
`203
`213
`214
`22'.3
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`Contents
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`7 .9
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`To Probe Further
`References
`
`Part 3
`
`A System Perspective
`
`Chapter 8
`
`Implementation Strategies for Digital ICS
`8.1
`Introduction
`8.2
`From Custom to Semicustom and Structured-Array
`Design Approaches
`Custom Circuit Design
`8.3
`8.4 Cell-Based Design Methodology
`8.4.1 Standard Cell
`8.4.2 Compiled Cells
`8.4.3 Macrocells, Megacells and Intellectual Property
`8.4.4 Semicustom Design Flow
`8.5 Array-Based Implementation Approaches
`8.5.1 Prediffused (or Mask-Programmable) Arrays
`8.5.2 Prewired Arrays
`Perspective-The Implementation Platform of the Future
`Summary
`To Probe Further
`References
`Design Methodology Insert E Characterizing Logic
`and Sequential Cells
`References
`Design Methodology Insert F Design Synthesis
`References
`Chapter9 Coping with Interconnect
`9.1
`Introduction
`9.2 Capacitive Parasitics
`9.2.I Capacitance and Reliability~Cross Talk
`9 .2.2 Capacitance and Performance in CMOS
`Resistive Parasitics
`9 .3 .1 Resistance and Reliability-Ohmic Voltage Drop
`9.3.2 Electromigration
`9.3.3 Resistance and Perlormance-RC Delay
`Inductive Parasitics*
`9.4.1
`Inductance and Reliability- Voltage Drop
`9.4.2
`Inductance and Perlormance_.:.Transmission-line Effects
`Advanced Interconnect Techniques
`
`8.6
`8.7
`8.8
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`9.3
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`9 .4
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`9.5
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`1
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`xix
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`382
`383
`384
`385
`390
`392
`396
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`427
`434
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`l
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`Contents
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`11.4
`
`Chapter 11 Designing Arithmetic Building Blocks
`11.1
`Introduction
`11.2 Datapaths in Digital Processor Architectures
`11.3 The Adder
`11.3.1 The Binary Adder: Definitions
`11.3.2 The Full Adder: Circuit Design Considerations
`11.3.3 The Binary Adder: Logic Design Considerations
`The Multiplier
`11.4.1 The Multiplier: Definitions
`11.4.2 Partial-Product Generation
`11.4.3 Partial-Product Accumulation
`11.4.4 Final Addition
`11.4.5 Multiplier Summary
`11.5 The Shifter
`11.5.1 Barrel Shifter
`11.5.2 Logarithmic Shifter
`11.6 Other Arithmetic Operators
`11. 7 Power and Speed Trade-offs in Datapath Structures*
`11.7.1 Design Time Power-Reduction Techniques
`11. 7 .2 Run-Time Power Management
`11. 7.3 Reducing the Power in Standby ( or Sleep) Mode
`11.8 Perspective: Design as a Trade-off
`11.9 Summary
`11.10 To Probe Further
`References
`Chapter 12 Designing Memory and Array Structures
`12.1
`Introduction
`12.1.1 Memory Classification
`12.1.2 Memory Architectures and Building Blocks
`12.2 The Memory Core
`12.2.1 Read-Only Memories
`12.2.2 Nonvolatile Read-Write Memories
`12.2.3 Read-Write Memories (RAM)
`12.2.4 Contents-Addressable or Associative Memory (CAM)
`12.3 Memory Peripheral Circuitry*
`12.3.1 The Address Decoders
`12.3.2 Sense Amplifiers
`12.3.3 Voltage References
`12.3.4 Drivers/Buffers
`12.3.5 Timing and Control
`
`xxi
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`560
`560
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`561
`564
`571
`586
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`587
`589
`593
`594
`594
`595
`596
`596
`600
`601
`611
`617
`618
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`620
`621
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`634
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`670
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`CHAPTER
`
`The Manufacturing Process
`
`Introduction
`2.1
`2.2 Manufacturing CMOS Integrated Circuits
`2.2.1
`The Silicon Wafer
`2.2.2 Photolithography
`2.2.3 Some Recurring Process Steps
`2.2.4 Simplified CMOS Process Flow
`2.3 Design Rules-Between the Designer and the Process Engineer
`Packaging Integrated Circuits
`2.4
`2.4.1 Package Materials
`2.4.2
`Interconnect Levels
`2.4.3 Thermal Considerations in Packaging
`Perspective-Trends in Process Technology
`2.5.1 Short-Term Developments
`2.5.2
`In the Longer Term
`Summary
`To Probe Further
`
`2.6
`2. 7
`
`2.5
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`2.2 Manufacturing CMOS Integrated Circuits
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`39
`
`a graphical overview of the different operations involved in a typical photolithographic process.
`The following steps can be identified:
`
`I. Oxidation layering-this optional step deposits a thin layer of Si02 over the complete
`wafer by exposing it to a mixture of high-purity oxygen and hydrogen at approximately
`1000°C. The oxide is used as an insulation layer and also forms transistor gates.
`2. Photoresist coating-a light-sensitive polymer (similar to latex) is evenly applied to a
`thickness of approximately I µm by spinning the wafer. This material is originally soluble
`in an organic solvent, but has the property that the polymers cross-link when exposed to
`light, making the affected regions insoluble. A photoresist of this type is called negative. A
`positive photoresist has the opposite properties; originally insoluble, but soluble after
`exposure. By using both positive and negative resists, a single mask can sometimes be
`used for two steps, making complementary regions available for processing. Since the cost
`of a mask is increasing quite rapidly with the scaling of technology, reducing the number
`of masks surely is a high priority.
`3. Stepper exposure-a glass mask (or reticle) containing the patterns that we want to trans(cid:173)
`fer to the silicon is brought in close proximity to the wafer. The mask is opaque in the
`regions that we want to process, and transparent in the others (assuming a negative photo(cid:173)
`resist). The glass mask can be thought of as the negative of one layer of the microcircuit.
`The combination of mask and wafer is now exposed to ultraviolet light. Where the mask is
`transparent, the photoresist becomes insoluble.
`4. Photoresist development and bake-the wafers are developed in either an acid or base
`solution to remove the nonexposed areas of photoresist. Once the exposed photoresist is
`removed, the wafer is "soft baked" at a low temperature to harden the remaining
`photoresist.
`5. Acid etching-material is selectively removed from areas of the wafer that are not covered
`by photoresist. This is accomplished through the use of many different types of acid, base
`and caustic solutions as a function of the material that is to be removed. Much of the work
`with chemicals takes place at large wet benches where special solutions are prepared for
`specific tasks. Because of the dangerous nature of some of these solvents, safety and envi(cid:173)
`ronmental impact is a primary concern.
`6. Spin, rinse, and dry-a special tool (called SRD) cleans the wafer with deionized water
`and dries it with nitrogen. The microscopic scale of modern semiconductor devices means
`that even the smallest particle of dust or dirt can destroy the circuitry. To prevent this from
`happening, the processing steps are performed in ultraclean rooms where the number of
`dust particles per cubic foot of air ranges between 1 and 10. Automatic wafer handling and
`robotics are used whenever possible. This explains why the cost of a state-of-the-art
`fabrication facility easily reaches multiple billions of dollars. Even then, the wafers must
`be constantly cleaned to avoid contamination and to remove the leftover of the previous
`process steps.
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`2.2 Manufacturing CMOS Integrated Circuits
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`41
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`becomes more and more difficult. So far, electrical engineering has extended the lifetime of this
`process at least until the 100 nm (or 0.1 µm) process generation. Techniques such as optical mask
`correction (OPC) prewarp the drawn patterns to account for the diffraction phenomena, encoun(cid:173)
`tered when printing close to the wavelength of the available optical source. This adds substan(cid:173)
`tially to the cost of mask making. In the foreseeable future, other solutions that offer a finer
`resolution, such as extreme ultraviolet (EUV), X ray, or electron beam, may be needed. These
`techniques, while fully functional, are currently less attractive from an economic viewpoint.
`
`2.2.3 Some Recurring Process Steps
`
`Diffusion and Ion Implantation
`Many steps of the integrated circuit manufacturing process require a change in the dopant con(cid:173)
`centration of some parts of the material. Examples include the creation of the source and drain
`regions, well and substrate contacts, the doping of the polysilicon, and the adjustments of the
`device threshold. Two approaches exist for introducing these dopants-diffusion and ion
`implantation. In both techniques, the area to be doped is exposed, while the rest of the wafer is
`coated with a layer of buffer material, typically Si02.
`In diffusion implantarion, the wafers are placed in a quartz tube embedded in a heated fur(cid:173)
`nace. A gas containing the dopant is introduced in the tube. The high temperatures of the fur(cid:173)
`nace, typically 900 to II 00 °C, cause the dopants to diffuse into the exposed surface both
`vertically and horizontally. The final dopant concentration is the greatest at the surface and
`decreases in a gaussian profile deeper in the material.
`In ion implantation, dopants are introduced as ions into the material. The ion implantation
`system directs and sweeps a beam of purified ions over the semiconductor surface. The accelera(cid:173)
`tion of the ions determines how deep they will penetrate the material, while the beam current
`and the exposure time determine the dosage. The ion implantation method allows for an inde(cid:173)
`pendent control of depth and dosage. This is the reason that ion implantation has largely dis(cid:173)
`placed diffusion in modem semiconductor manufacturing.
`Ion implantation has some unfortunate side effects~ however, the most important one being
`lattice damage. Nuclear collisions during the high energy implantation cause the displacement
`of substrate atoms, leading to material defects. This problem is largely resolved by applying a
`subsequent annealing step, in which the wafer is heated to around 1000°C for 15 to 30 minutes,
`and then allowed to cool slowly. The heating step thermally vibrates the atoms, which allows the
`bonds to reform.
`
`Deposition
`Any CMOS process requires the repetitive deposition of layers of a material over the complete
`wafer, to either act as buffers for a processing step, or as insulating or conducting layers. We
`have already discussed the oxidation process, which allows a layer of Si02 to be grown. Other
`materials require different techniques. For instance, silicon nitride (Si3N4) is used as a sacrificial
`buffer material during the formation of the field oxide and the introduction of the stopper
`
`I i
`I I
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`42
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`Chapter 2 • The Manufacturing Process
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`implants. This silicon nitride is deposited everywhere using a process called chemical vapor
`deposition or CVD. This process is based on a gas-phase reaction, with energy supplied by heat
`at around 850°C.
`Polysilicon, on the other hand, is deposited using a chemical deposition process, which
`flows silane gas over the heated wafer coated with Si02 at a temperature of approximately
`650°C. The resulting reaction produces a noncrystalline or amorphous material called poly sili(cid:173)
`con. To increase the conductivity of the material, the deposition has to be followed by an implan(cid:173)
`tation step.
`The Aluminum interconnect layers typically are deployed using a process known as sput(cid:173)
`tering. The aluminum is evaporated in a vacuum, with the heat for the evaporation delivered by
`electron-beam or ion-beam bombarding. Other metallic interconnect materials such as Copper
`require different deposition techniques.
`
`Etching
`Once a material has been deposited, etching is used selectively to form patterns such as wires
`and contact holes. We already discussed the wet etching process, which makes use of acid or
`basic solutions. Hydrofluoric acid buffered with ammonium fluoride typically is used to etch
`Si02, for example.
`In recent years, dry or plasma etching has advanced substantially. A wafer is placed into
`the etch tool's processing chamber and given a negative electrical charge. The chamber is heated
`to 100°C and brought to a vacuum level of 7.5 Pa, then filled with a positively charged plasma
`(usually a mix of nitrogen, chlorine, and boron trichloride). The opposing electrical charges
`cause the rapidly moving plasma molecules to align themselves in a vertical direction, forming a
`microscopic chemical and physical "sandblasting" action which removes the exposed material.
`Plasma etching has the advantage of offering a well-defined directionality to the etching action,
`creating patterns with sharp vertical contours.
`
`Planarization
`To reliably deposit a layer of material onto the semiconductor surface, it is essential that the sur(cid:173)
`face be approximately flat. If special steps were not taken, this would definitely present prob(cid:173)
`lems in modern CMOS processes, where multiple patterned metal interconnect layers are
`superimposed onto each other. Therefore, a chemical-mechanical planarization (CMP) step is
`included before the deposition of an extra metal layer on top of the insulating Si02 layer. This
`process uses a slurry compound-a liquid carrier with a suspended abrasive component such as
`aluminum oxide or silica-to microscopically plane a device layer and to reduce the step
`heights.
`
`2.2.4 Simplified CMOS Process Flow
`The gross outline of a potential CMOS process flow is given in Figure 2-6. The process starts
`with the definition of the active regions-these are the regions where transistors will be con(cid:173)
`structed. All other areas of the die will be covered with a thick layer of silicon dioxide (Si02)
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`2.2 Manufacturing CMOS Integrated Circuits
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`43
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`Define active areas
`Etch and fin trenches
`t
`
`Implant well regions
`
`t
`Deposit and pattern
`polysilicon !ayer
`
`+
`
`Implant source and drain
`regions and substrate contacts
`t
`Create contact and via windows
`Deposit and pattern metal layers
`
`Figure 2-6 Simplified process sequence for the manufacturing of an-dual-well CMOS circuit.
`
`called the field oxide. This oxide acts as the insulator between neighboring devices, and it is
`either grown (as in the process of Figure 2-1) or deposited in etched trenches (Figure 2-2)(cid:173)
`hence, the name trench insulation. Further insulation is provided by the addition of a reverse(cid:173)
`biased up-diode, formed by adding an extra p+ region called the channel-stop implant (or field
`implant) underneath the field oxide. Next, lightly doped p- and 11-wells are formed through ion
`implantation. To construct an NMOS transistor in a p-well, heavily doped 11-type source and
`drain regions are implanted ( or diffused) into the lightly doped p-type substrate. A thin layer of
`Si02 called the gate oxide separates the region between the source and drain, and is itself cov(cid:173)
`ered by conductive polycrystalline silicon (or polysilicon, for short). The conductive material
`forms the gate of the transistor. Plv10S transistors are constructed in an n-well in a similar fash(cid:173)
`ion (just reverse n's and p's). Multiple insulated layers of metallic (most often Aluminum) wires
`are deposited on top of these devices to provide for the necessary interconnections between the
`transistors.
`A more detailed breakdown of the flow into individual process steps and their impact on
`the semiconductor material is shown graphically in Figure 2-7. While most of the operations
`should be self-explanatory in light of the previous descriptions. some comments on individual
`operations are worthwhile. The process starts with a p-substrate surfaced with a lightly doped p(cid:173)
`epitaxial layer (a). A thin layer of Si02 is then deposited, which will serve as the gate oxide for
`the transistors, followed by a deposition of a thicker sacrificial silicon nitride layer (b). A
`plasma etching step using the complementary of the active area mask creates the trenches used
`for insulating the devices (c). After providing the channel stop implant, the trenches are filled
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`48
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`Chapter 2 • The Manufacturing Process
`
`For these and other reasons, scalable design rules normally are avoided by industry.2 As circuit
`density is a prime goal in industrial designs. most semiconductor companies tend to use micron
`rules, which express the design rules in absolute dimensions and therefore can exploit the fea(cid:173)
`tures of a given process to a maximum degree. Scaling and porting designs between technolo(cid:173)
`gies under these rules is more demanding and has to be performed either manually or using
`advanced CAD tools.
`For this book, we have selected a "vanilla" 0.25 µm CMOS process as our preferred
`implementation medium. The rest of this section is devoted to a short introduction and overview
`of the design rules of this process, which fall in the micron-mies class. A complete design-mle
`set consists of the following entities: a set of layers, relations between objects on the same layer,
`and relations between objects on different layers. We discuss each of them in sequence.
`
`Layer Representation
`The layer concept translates the intractable set of masks currently used in CMOS into a simple
`set of conceptual layout levels that are easier to visualize by the circuit designer. From a
`designer's viewpoint, all CMOS designs are based on the following entities:
`
`• Substrates and/or wells, which are p-type (for NMOS devices) and n-type (for PMOS)
`• Diffusion regions (11+ and p+), which define the areas where transistors can be formed.
`These regions are often called the active areas. Diffusions of an inverse type are needed to
`implement contacts to the wells or to the substrate. These are called select regions.
`• One or more po/ysilicon layers, which are used to form the gate electrodes of the transis(cid:173)
`tors (but serve as interconnect layers as well).
`• A number of metal intercmmect layers.
`• Contact and via layers, which provide interlayer connections.
`
`A layout consists of a combination of polygons, each of which is attached to a certain layer. The
`functionality of the circuit is determined by the choice of the layers, as well as the interplay
`between objects on different layers. For example, an MOS transistor is formed by the cross sec(cid:173)
`tion of the diffusion layer and the polysilicon layer. An interconnection between two metal lay(cid:173)
`ers is formed by a cross section between the two metal layers and an additional contact layer. To
`visualize these relations, each layer is assigned a standard color (or stipple pattern for a black(cid:173)
`and-white representation). The different layers used in our CMOS process are represented in
`Colorplate I (color insert).
`
`Intralayer Constraints
`A first set of rules defines the minimum dimensions of objects on each layer, as well as the min(cid:173)
`imum spacings between objects on the same layer. All distances are expressed in µm. These con(cid:173)
`straints are presented in pictorial fashion in Colorplate 2.
`
`2While not entirely accurate, lambda rules are still useful to estimate the impact of a technology scale on the area of a design.
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`2.3 Design Rules-Between the Designer and the Process Engineer
`
`49
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`Interlayer Constraints
`Interlayer rules tend to be more complex. Because multiple layers are involved, it is harder to
`visualize their meaning or functionality. Understanding layout requires the capability of translat(cid:173)
`ing the two-dimensional picture of the layout drawing into the three-dlmensiona1 reality of the
`actual device. This takes some practice.
`\Ve present these rules in a set of separate groupings:
`
`1. Transistor Rules (Colmplate 3). A transistor is fo1med by the overlap of the active and the pol(cid:173)
`ysilicon layers. From the intralayer design rules, it is already clear that the minimum length of
`a transistor equals 0.24 µm (the minimum width of polysilicon). while its width is at least 0.3
`µm (the minimum width of diffusion). Extra rules include the spacing between the active area
`and the well boundary, the gate overlap of the active area, and the active overlap of the gate.
`2. Contact and Via Rules (Colorplates 2 and 4). A contact (which forms an interconnection
`between metal and active or polysilicon) or a via (which connects two metal layers) is
`formed by overlapping the two interconnecting layers and providing a contact hole, filled
`with metal, between the two. In our process, the minimum size of the contact hole is 0.3
`µm. while the polysilicon and diffusion layers have to extend at least 0.14 µm beyond the
`area of the contact hole. This sets the minimum area ofa contactto 0.44 .llm x 0.44 µm. This
`is larger than the dimensions of a minimum-size transistor! Excessive changes between
`interconnect layers in routing should therefore be avoided. The figure, furthe1more, points
`out the minimum spacings between contact and via holes, as well as their relationship with
`the smTounding layers.
`3. Well and Substrate Contacts (Colorplate 5). For robust digital circuit design, it is important for
`the well and substrate regions to be adequately connected to the supply voltages. Failing to do
`so results in a resistive path between the substrate contact of the transistors and the supply rails,
`and can lead to possibly devastating parasitic effects, such as latchup. It is therefore advisable
`to provide numerous substrate (well) contacts spread over the complete region. To establish an
`ohmic contact between a supply rail, implemented in metall, and ap-type material, ap+ diffu(cid:173)
`sion region must be provided. This is enabled by the select layer. which reverses the type of dif(cid:173)
`fusion. A number of rules regarding the use of the select layer are illustrated in Colorplate 5.
`
`Consider an n-well process, which implements the PMOS transistors into an n-type well
`diffused in a p-type material. The nominal diffusion is p". To invert the polarity of the diffusion,
`an n-select layer is provided that helps to establish the 11+ diffusions for the well contacts in the
`n-region, as wen as the ,-t source and drain regions for the NMOS transistors in the substrate.
`Verifying the Layout
`Ensuring that none of the design rules are violated is a fundamental requirement of the design
`process. Failing to do so will almost surely lead to a nonfunctional design. Doing so for a com(cid:173)
`plex design that can contain millions of transistors is no simple task either, especially given the
`complexity of some design-rule sets. \.Vhile design teams in the past used to spend numerous
`
`Dell Ex. 1025
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`

`

`

`

`2.4 Packaging Integrated Circuits
`
`51
`
`2.4 Packaging Integrated Circuits
`The IC package plays a fundamental role in the operation and performance of a component.
`Besides providing a means of bringing signal and supply wires in and out of the silicon die, it
`also removes the heat generated by the circuit and provides mechanical support. Finally. it also
`protects the die against environmental conditions such as humidity.
`In addition, the packaging technology has a major impact on the performance and power
`dissipation of a microprocessor or signal processor. This influence is getting more pronounced
`as time progresses due to the reduction in internal signal delays and on-chip capacitance result(cid:173)
`ing from technology scaling. Currently, up to 50% of the delay of a high-performance computer
`is due to packaging delays, and this number is expected to rise. The search for higher perfor(cid:173)
`mance packages with fewer inductive or capacitive parasitics has accelerated in recent years.
`The increasing complexity of what can be integrated on a single die also translates into a need
`for ever more input/output pins, as the number of connections going off-chip tends to be roughly
`proportional to the complexity of the circuitry on the chip. This relationship was first observed
`by E. Rent of IBM (published in [Landman71]), who translated it into an empirical formula that,
`appropriately, is called Rent's rule. This formula relates the number of input/output pins to the
`comp]exity of the circuit, as measured by the number of gates. It is written as
`P = KxG~
`where K is the average number of I/Os per gate, G the number of gates, J3 the Rent exponent, and
`P the number of l/0 pins to the chip. J3 varies between 0.1 and 0.7. Its value depends strongly
`upon the appHcation area, architecture, and organization of the circuit, as demonstrated in
`Table 2-1. Clearly, microprocessors display a very different input/output behavior compared to
`memories.
`The observed rate of pin-count increase for integrated circuits varies from 8% to 11 % per
`year, and it has been projected that packages with more than 2000 pins will be required by 2010.
`For all these reasons, traditional dual-in-line, through-hole mounted packages have been
`replaced by other approaches, such as surface-mount, ball-grid array, and multichip module
`
`(2.1)
`
`Table 2-1 Rent's constant tor various classes of systems ([Bakoglu90])
`
`Application
`
`Static memory
`
`Microprocessor
`
`Gate array
`
`High-speed computer (chip)
`
`High-speed computer (board)
`
`~
`
`0.12
`
`0.45
`
`0.5
`
`0.63
`
`0.25
`
`K
`
`6
`
`0.82
`
`1.9
`
`J.4
`
`82
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`52
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`Chapter 2 • The Manufacturing Process
`
`techniques. It is useful for the circuit designer to be aware of the available options and their pros
`and cons.
`Due to its multifunctionality, a good package must comply with a large variety of
`requirements:
`
`• Electrical requirements-Pins should exhibit low capacitance (both interwire and to the
`substrate), resistance, and inductance. A large characteristic impedance should be tuned to
`optimize transmission line behavior. Observe that intrinsic integrated-circuit impedances
`are high.
`• Mechanical and thermal properties-The heat removal rate should be as high as possi(cid:173)
`ble. Mechanical reliability requires a good matching between the thermal properties of the
`die and the chip carrier. Long-term reliability requires a strong connection from die to
`package, as well as from package to board.
`• Lo,v Cost-Cost is one of the more important properties to consider in any project. For
`example, while ceramics have a superior performance over plastic packages, they are also
`substantially more expensive. Increasing the heat removal capacity of a package also tends
`to raise the package cost. The least expensive plastic packaging can dissipate up to 1 \V.
`Slightly more expensive, but still of somewhat low quality, plastic packages can dissipate
`up to 2 W. Higher dissipation requires more expensive ceramic packaging. Chips dissipat(cid:173)
`ing over 20 Vl require special heat sink attachments. Even more extreme techniques such
`as fans and blowers, liquid cooling hardware, or heat pipes are needed for higher dissipa(cid:173)
`tion levels.
`Packing density is a major factor in reducing board cost. The increasing pin count either
`requires an increase in the package size or a reduction in the pitch between the pins. Both
`have a profound effect on the packaging economics.
`
`Packages can be classified in many different ways: by their main material, the number of
`interconnection levels, and the means used to remove heat. In this brief section, we provide only
`sketches of each of those issues.
`
`2.4.1 Package Materials
`
`The most common materials used for the package body are ceramic and polymers (plastics).
`The latter have the advantage of being substantially cheaper, but they suffer from inferior
`thermal properties. For example, the ceramic Al20 3 (alumina) conducts heat better than Si02
`and the polyimide plastic by factors of 30 and 100, respectively. Furthermore, its thermal
`expansion coefficient is substantially closer to the typical interconnect metals. The disadvan(cid:173)
`tage of alumina and other ceramics is their high