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`By eliminating redundancy and providing a reduced fault coverage, it is possible to test
`most combinational logic blocks with a limited set of input vectors. This does not solve the
`sequential problem, however. To test a given fault in a state machine, it is not sufficient to apply
`the correct input excitation; the engine must be brought to the desired state first. This requires
`that a sequence of inputs be applied. Propagating the circuit response to one of the output pins
`might require another sequence of patterns. In other words, testing for a single fault in an FSM
`requires a sequence of vectors. Once again, this might make the process prohibitively expensive.
`One way to address the problem ls to turn the sequential network into a combinational one
`by breaking the feedback loop in the course of the test. This is one of the key concepts behind
`the scan-test methodology described later. Another approach is to let the circuit test itself. Such
`a test does not require external vectors and can proceed at a higher speed. The concept of self(cid:173)
`test will be discussed in more detail later. When considering the testability of designs, two prop(cid:173)
`erties are of foremost importance:
`
`1. Controllability, which measures the ease of bringing a circuit node to a given condition
`using only the input pins. A node is easily controllable if it can be brought to any condition
`with only a single input vector. A node (or circuit) with low controllability needs a long
`sequence of vectors to be brought to a desired state. It should be clear that a high degree of
`conu·ollability is desirable in testable designs.
`2. Observability, which measures the ease of observing the value of a node at the output
`pins. A node with a high observability can be monitored directly on the output pins. A
`node with a low observability needs a number of cycles before its state appears on the out(cid:173)
`puts. Given the complexity of a circuit and the limited number of output pins, a testable
`circuit should have a high observability. This is exactly the purpose of the test techniques
`discussed in the se<:tions that follow.
`
`Combinational circuits fall under the class of easily observable and controllable circuits, since
`any node can be controlled and observed in a single cycle.
`Design-for-test approaches for the sequential modules can be classified in three categories:
`ad hoc test, scan-based test, and self-test.
`
`H.3.2 Ad Hoc Testing
`As suggested by the title, ad hoc testing combines a collection of tricks and techniques that can
`be used to increase the observability and controllability of a design and that are generally
`applied in an application-dependent fashion.
`An example of such a technique is illustrated in Figure H-3a, which shows a simple pro(cid:173)
`cessor with its data memory. Under normal configuration, the memory is only accessible
`through the processor. Writing and reading a data value into and out of a single memory position
`requires a number of clock cycles. The controllability and observability of the memory can be
`dramatically improved by adding multiplexers on the data and address busses (Figure H-3b).
`
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`mode. Setting Test high selects the Sccmln input and connects the registers into the scan chain.
`The output of the register Out connects to the fan-out logic, but also doubles as the ScanOut pin
`that connects to the Sca11b1 of the neighboring register. The overhead in both area and perfor(cid:173)
`mance is smal1 and can be limited to less than 5%.
`
`Problem H.1 Scan-Register Design
`
`Modify the static, two-phase master-slave register of Figure 7-IO to support serial scan.
`
`Figure H-6 depicts the timing sequence that would be employed for the circuit in
`Figure H-4 under the assumption of a two-phase clocking approach. For a scan chain N registers
`deep, the Test signal is raised, and N dock pulses arc issued, loading the registers. Test is low(cid:173)
`ered, and a single clock sequence is issued, latching the results from the combinational logic into
`the registers under normal circuit-operation conditions. Fina11y, N extra pulses (with Test= I)
`transfer the obtained result to the output. Note again that the scan-out can overlap with the enter(cid:173)
`ing of the next vector.
`:f\.1any variants of the serial-scan approach can be envisioned. A very popular one, which
`was actually the pioneering approach, was introduced by IBM and is cal1ed level-sensitive scan
`design (LSSD) [Eichelberger78]. The basic building block of the LSSD approach is the shift(cid:173)
`register latch (SRL) shown in Figure H-7. lt consists of two latches LI and Ll, the latter being
`
`,h,~
`
`I
`
`I
`
`~
`~I r--=- ----~L__µL_ ---· J~
`
`~2 ~ _____ Jl __ Jl_;_Jl_ ____ _JlJ
`
`N cycles
`scan-in
`
`l cycle
`evaluation
`
`N cycles
`scan-out
`
`Figure H-6 Timing diagram of test-sequence. N represents the number of registers
`in the test chain.
`
`D
`C
`SI
`A
`
`'-~-----Q
`
`LJ
`
`' - - -
`
`b--+------Q
`so
`
`L2
`
`B
`
`Figure H-7 Shift-register latch.
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`Insert H • Validation and Test of Manufactured Circuits
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`733
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`FSl,1
`
`Data-in
`
`address&
`R/Wcontrol
`
`Memory
`Under Test
`
`I
`I
`
`Data-out
`
`i Signature
`I Analysis
`
`Figure H-14 Memory self-test.
`
`be used as a normal register and scan register, depending on the values of the control signals B0
`and B, (Figure H-l 3b ). This test approach, which combines all the different techniques, is
`known as built-in logic block observation, or BILBO [Koeneman79]. Figure H-13c illustrates the
`typical use of BILBO. Using the scan option, the seed is shifted into the BILBO register A while
`BILBO register B is initialized. Next, registers A and B are operated in the random pattern-gen(cid:173)
`eration and signature-analysis modes, respectively. At the end of the test sequence~ the signature
`is read from B using the scan mode.
`Finally, it is worth mentioning that self-test is extremely beneficial when testing regular
`structures such as memories. It is not easy to ensure that a memory. which is a sequential circuit,
`is fault free. The task is complicated by the fact that the data value read from or written into a
`cell can be influenced by the values stored in the neighboring cells because of cross coupling and
`other parasitic effects. fi'1emory tests, therefore, include the reading and writing of a number of
`different patterns into and from the memory using alternating addressing sequences. Typical pat(cid:173)
`terns can be aH zeros or ones, or checkerboards of zeros and ones. Addressing schemes can
`include the writing of the complete memory, followed by a complete read-out or various alter(cid:173)
`nating read-write sequences. VVith a minimal overhead compared with the size of a memory, this
`test approach can be built into the integrated circuit itself, as illustrated in Figure H-14. This
`approach significantly improves the testing time and minimizes the external control. Applying
`self-test is bound to become more important with the increasing complexity of integrated com(cid:173)
`ponents and the growing popularity of embedded memories.
`
`The advent of the systems-on-a-chip era does not make the test job any easier. A single IC may contain
`micro- and signal processors, multiple embedded memories, ASIC modules, FPGAs and on-chip busses
`and networks. Each of these modules has its own preferred way of being tested, and combining those into a
`coherent strategy is quite a challenge. Built-in self-test is really the only way out. A structured test-method(cid:173)
`ology for systems-on-a-chip, based on BIST is shown in Figure H-15. Each of the modules composing the
`system connects to the on-chip network through a "wrapper." This is a customized interface between the
`block and the network, supporting functions such as synchronization and communication. This wrapper can
`be extended to include a test support module. For instance, for an ASIC module that includes a scan chain,
`the lest support module provides the interface to the scan chain and a buffer for the test patterns. This buffer
`can be directly written and read through the system bus. Similarly, a memory module can be equipped with
`a pattern generator and signature analysis. All of this would still not suffice if there were no general test
`orchestrator. Fortunately, most of these SOCs. include a programmable processor which can be used at start(cid:173)
`up time to direct the test and the verificalion of the other modules. Test patterns and signatures can be stored
`
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`737
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`This example is extremely simple. and the derivation of a minimum test-vector set for
`more complex circuits is substantially more complex. A number of excellent approaches to
`address this problem have been developed. Landmark efforts in this domain are the D [Roth66]
`and PODEM algorithms [GoeI81], which underlie many current ATPG tools. It suffices to say
`that ATPG is currently in the mainstream of design automation, and powerful tools are available
`from many vendors.
`
`H.4.3 Fault Simulation
`A fault simulator measures the quality of a test program. It determines the fault coverage, which
`is defined as the total number of faults detected by the test sequence divided by two times the
`number of nodes in the network-each node can give rise to an saO and sal fault. Naturally, the
`obtained coverage number is oniy as good as the fau]t model employed. In an saO-sal model.
`some of the bridge and short faults are not covered and will not appear in the coverage statistics.
`The most common approach to fault simulation is the parallel fault-simulation technique,
`in which the correct circuit is simulated concurrently with a number of faulty ones, each of
`which has a single fault injected. The results are compared, and a fault is labeled as detected for
`a given test vector set if the outputs diverge. This description is overly simplistic, and most sim(cid:173)
`ulators employ a number of techniques, such as selecting the faults with a higher chance of
`detection first, to expedite the simulation process. Hardware fault- simulation accelerators, based
`on parallel processing and providing a substantial speedup over pure software-based simulators,
`are available as well [Agrawal88, pp. 159-240].
`
`H.5 To Probe Further
`For an in-depth treatment of the Design-for-Testability topic, please refer to [Agrawal88] and
`[Abramovic9 l]. A great overview of the testing challenges and solutions for high-performance
`microprocessors can be found in [BhavsarO I].
`
`References
`[Abramovic91] M, Abra.movie, M. Breuer, and A Friedman, Digital Systems Tcstiug and Testable Desig11, IEEE Press,
`Piscataway, NJ, 1991.
`tAgrawal88] V. Agrawal and S. Seth, Eds. Test Generation for VLSI Chips, IEEE Computer Society Press, 1988.
`[BhavsarOJ] D. Bhavsar, "Testing of High-Performance Microprocessors,'' in Design of High-Pe1fomw11ce Micropro(cid:173)
`cessorCircuirs. A. Chandrnkasan et nl., Ed., pp. 523--44, IEEE Press, 2001
`[Eichelberger78] E. Eichelberger and T. Williams, "A Logic Design Structure for VLSI Testubi!ity," Jounwl an Design
`Automation of Fault-Tolerant Compuring, vol. 2, pp. 165-78, May 1978.
`[GoelSl] P. Goel, "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits," IEEE
`Trans. on Computers, vol. C-30, no. 3, pp. 26-268, June 198.L
`[IEEEl 149] IEEE Standard 1149.l, "IEEE Standard Test Access Port and Boundary-Scan Architecture," IEEE Stan(cid:173)
`dards Board, New York.
`[Koeneman79] B. Koeneman, J. Mucha. and 0. Zwiehoff, "Built-in Logic-Block Observation Techniques," in Digest
`1979 Test Coufere11(;e, pp. 37-4-1, October 1979.
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`[Kornegay92} K. Kornegay, Automated Tesiing in an Jnregmted System Design Environment, Ph. D dissertation .. Mem.
`No. UCB/ERL M921104, Sept. 1992.
`[KrsticOl] A. Krstic, W. Lai, L. Chen, K. Cheng, and S. Dey, "Embedded Software-Based Self-Testing for SOC Design,"
`hup:/Avww.gigascale.org!pubs/139.html, December 2001.
`{Roth66] J, Roth, "Diagnosis of Automata Failures: A Calculus and a Method," IBM Journal of Research and Develop(cid:173)
`meru, vol. 10, pp. 278--291, 1966.
`[Wang86] L. Wang and E. McCluskey, "Complete Feedback Shift-Register Design for Built-in Self Test," Prac. !CCAD
`/986, pp. 56-59, November, 1986.
`[Weste93l N. Wes!e and K. Eshraghian, Principles of CMOS VLSI Design-A Systems Perspective, Addison~Wesley,
`1993.
`[Wi11iams83] T. Williams and K. Parker, "Design for Testability-A Survey," Proceedings IEEE, vol. 71. pp. 98-t 12,
`fan. 1983.
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