`
`UNITED STATES DISTRICT COURT
`WESTERN DISTRICT OF TEXAS
`WACO DIVISION
`
`Greenthread, LLC
`
`
`
`Plaintiff,
`
`Civil Action No. 6:22-cv-105-ADA
`
`v.
`
`Intel Corporation;
`Dell Inc.; and
`Dell Technologies Inc.
`
`Defendants.
`
`
`
`JURY TRIAL DEMANDED
`
`GREENTHREAD’S RESPONSIVE CLAIM CONSTRUCTION BRIEF
`
`
`
`
`
`
`
`
`
`Dell Ex. 1020
`Page 1
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`Case 6:22-cv-00105-ADA Document 96 Filed 10/31/22 Page 2 of 46
`
`TABLE OF CONTENTS
`
`TABLE OF AUTHORITIES .......................................................................................................... ii
`
`TABLE OF EXHIBITS ................................................................................................................. iv
`
`EXEMPLARY CLAIMS 195:1 & 842:1 .........................................................................................v
`
`DISPUTED CLAIM CONSTRUCTIONS .................................................................................... vi
`
`AGREED CLAIM CONSTRUCTIONS ..................................................................................... viii
`
`
`
`
`
`INTRODUCTION ...............................................................................................................1
`
`BACKGROUND .................................................................................................................2
`
`A.
`
`B.
`
`C.
`
`D.
`
`Dopants ....................................................................................................................2
`
`Overview of Dr. Rao’s Invention.............................................................................2
`
`Exemplary Claim 195:1 ...........................................................................................5
`
`Exemplary Claim 842:1 ...........................................................................................8
`
`
`
`DISPUTED CLAIM TERMS ..............................................................................................8
`
`A.
`
`Claim Terms Found in Exemplary Claim 195:1 ......................................................9
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`“surface layer” terms (195:1; 502:7; 222:44) ..............................................9
`
`“substrate” (195:1; 502:7; 842:1, 9; 481:1, 20; 222:1,
`21, 39, 41, 42, 44; 014:1, 21) .....................................................................15
`
`“active region” (195:1; 502:7; 842:1, 9; 481:1, 20;
`222:1, 21, 39, 41, 42, 44; 014:1, 21) ..........................................................19
`
`“unidirectional electric drift field” terms (195:1;
`502:7; 222:44) ............................................................................................20
`
`“to aid the movement” terms (195:1; 502:7; 842:1, 9;
`481:1, 20; 222:1, 21, 39, 41, 42, 44; 014:1, 21) .........................................25
`
`“well region” (195:1; 502:7; 842:1, 9; 481:1, 20;
`222:1, 21, 39, 41, 42, 44; 014:1, 21) ..........................................................30
`
`B.
`
`Claim Term Found in Exemplary Claim 842:1 .....................................................31
`
`7.
`
`“active region…within which transistors can be
`formed” (842:1, 9; 481:1, 20; 222:1, 21, 39, 41, 42;
`014:1, 21) ...................................................................................................31
`
`
`
`CONCLUSION ..................................................................................................................35
`
`
`
`
`
`i
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`Dell Ex. 1020
`Page 2
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`Case 6:22-cv-00105-ADA Document 96 Filed 10/31/22 Page 3 of 46
`
`
`CASES
`
`TABLE OF AUTHORITIES
`
`Page(s)
`
`Acumed LLC v. Stryker Corp.,
`483 F.3d 800 (Fed. Cir. 2007)..................................................................................................19
`
`Adams Respiratory Therapeutics, Inc. v. Perrigo Co.,
`616 F.3d 1283 (Fed. Cir. 2010)................................................................................................13
`
`Cordis Corp. v. Boston Sci. Corp.,
`561 F. 3d 1319 (Fed. Cir. 2009)...............................................................................................21
`
`Datamize, LLC v. Plumtree Software, Inc.,
`417 F.3d 1342 (Fed. Cir. 2005)................................................................................................28
`
`Enzo Biochem, Inc. v. Applera Corp.,
`599 F.3d 1325, 1336 (Fed. Cir. 2010) .....................................................................................26
`
`Evicam Int'l, Inc. v. Enf't Video, LLC,
`No. 4:16-CV-105, 2016 WL 6470967 (E.D. Tex. Nov. 2, 2016) ............................................29
`
`Hill-Rom Servs., Inc. v. Stryker Corp.,
`755 F.3d 1367 (Fed. Cir. 2014)................................................................................................17
`
`Interval Licensing LLC v. AOL, Inc.
`766 F.3d 1364 (Fed. Circ. 2014 ...............................................................................................28
`
`JobDiva, Inc. v. Monster Worldwide, Inc.
`No. 13-CV-8229 KBF, 2014, WL 5034674 (S.D.N.Y. Oct. 3, 2014) .....................................29
`
`Nabors Drilling Techs. USA, Inc. v. Helmerich & Payne Int'l Drilling Co.,
`No. 3:20-CV-03126-M, 2022 WL 1689444 (N.D. Tex. May 26, 2022) .................................29
`
`Nautilus, Inc. v. Biosig Instruments,
`572 U.S. 898 (2014) .................................................................................................................10
`
`NTP, Inc. v. Research in Motion, Ltd.,
`418 F.3d 1282 (Fed. Cir. 2005)................................................................................................19
`
`O2 Micro Int’l Ltd. v. Beyond Innovation Tech. Co.,
`521 F.3d 1351 (Fed. Cir. 2008)................................................................................................31
`
`Perfectvision Mftg., Inc. v. PPC Broadband, Inc.,
`No. 4:12CV00623 JLH, 2014 WL 4285786 (E.D. Ark. Aug. 29, 2014) .................................28
`
`SynQor, Inc. v. Artesyn Techs., Inc.,
`709 F.3d 1365 (Fed. Cir. 2013)................................................................................................13
`
`ii
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`Dell Ex. 1020
`Page 3
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`Case 6:22-cv-00105-ADA Document 96 Filed 10/31/22 Page 4 of 46
`
`Tehrani v. Hamilton Medical, Inc.,
`331 F.3d 1355 (Fed. Cir. 2003)................................................................................................14
`
`W. Union Co. v. MoneyGram Int'l, Inc.,
`2008 U.S. Dist. LEXIS 108129 (W.D. Tex. Nov. 6, 2008) .....................................................31
`
`
`
`
`
`iii
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`Dell Ex. 1020
`Page 4
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`Case 6:22-cv-00105-ADA Document 96 Filed 10/31/22 Page 5 of 46
`
`TABLE OF EXHIBITS1
`
`Exhibit
`
`Description
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`Declaration of Dr. Konstantinos P. Giapis (“Giapis declaration”)
`
`U.S. Patent No. 8,421,195 to G.R. Mohan Rao (GREENTHREAD-WDTX-000027-
`000040) (“195 patent”)
`
`U.S. Patent No. 10,510,842 to G.R. Mohan Rao (GREENTHREAD-WDTX-000070-
`000084) (“842 patent”)
`
`Excerpts from Chen, J. Y., CMOS Devices and Technology for VLSI, Prentice-Hall
`(1990) (GREENTHREAD-WDTX-007426–007682) (“Chen”)
`
`Greenthread, LLC v. Samsung Elecs. Co., Ltd., No. 2:19-cv-00147-JRG, Dkt. 67
`(Claim Construction Memorandum Opinion and Order), E.D. Tex. Apr. 20, 2020
`(GREENTHEAD-WDTX-002761-002792) (“EDTX Markman Order”)
`
`Samsung Elecs. Co., Ltd. v. Greenthread, LLC, IPR2020-00289, Ex. 1003 (Apr. 14,
`2020) (GREENTHREAD-WDTX-003869–003959) (“Smith declaration”)
`
`The American Heritage Dictionary of the English Language, Third Edition (2002), at
`1792 (defining “substrate”) (GREENTHREAD-WDTX-007794–007797)
`
`Excerpts from Webster’s Third New International Dictionary of the English Language
`Unabridged, Merriam-Webster, Inc. (1992) (GREENTHREAD-WDTX-002826–
`002834, GREENTHREAD-WDTX-007793)
`
`Excerpts from Baker, R. J., CMOS Circuit Design, Layout, and Simulation, IEEE
`(1998) (GREENTHREAD-WDTX-002674–002715) (“Baker”)
`
`Defendants’ Preliminary Claim Constructions, No. 6:22-cv-105-ADA (W.D. Tex.)
`(served Sept. 19, 2022)
`
`File History of U.S. Patent No. 10,510,842 (GREENTHREAD-WDTX-001059-1246)
`(“842 file history”)
`
`Excerpts from Howe, R. T., Microelectronics: An Integrated Approach, Prentice-Hall
`(1997) (“Howe”) (GREENTHREAD-WDTX-002793–2813)
`
`Excerpts from Wolf S., Silicon Processing for the VLSI Era Volume 2: Process
`Integration, Lattice Press (1990)
`
`Excerpts from Wolf S., Silicon Processing for the VLSI Era Volume 3: The
`Submicron MOSFET, Lattice Press (1995) (GREENTHREAD-WDTX-002877–2883)
`
`
`
`
`
`
`1 When possible, Greenthread has cited to the exhibits previously attached to Defendants’ Opening
`Markman Brief (Dkt. 82). Unless otherwise indicated, all docket numbers refer to the present case,
`Greenthread, LLC v. Intel Corp. et al., No. 6:22-cv-105-ADA (W.D. Tex.), and all citations to
`page numbers of CM/ECF documents refer to the page number at the top of the page in the
`CM/ECF header.
`
`iv
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`Dell Ex. 1020
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`Case 6:22-cv-00105-ADA Document 96 Filed 10/31/22 Page 6 of 46
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`EXEMPLARY CLAIMS 195:1 & 842:1
`
`Term
`
`U.S. Patent No. 8,421,195, Claim 1 (195:1)
`
`A CMOS Semiconductor device comprising:
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`a surface layer;
`
`a substrate;
`
`an active region including a source and a drain, disposed on one surface of said
`surface layer;
`
`a single drift layer disposed between the other surface of said surface layer and
`said substrate, said drift layer having a graded concentration of dopants
`extending between said surface layer and said substrate, said drift layer
`further having a first static unidirectional electric drift field
`
`to aid the movement of minority carriers from said surface layer to said
`substrate; and
`
`at least one well region disposed in said single drift layer, said well region
`having a graded concentration of dopants and a second static unidirectional
`electric drift field to aid the movement of minority carriers from said surface
`layer to said substrate.
`
`Term
`
`U.S. Patent No. 10,510,842, Claim 1 (842:1)
`
`
`
`
`
`
`
`
`
`
`A semiconductor device, comprising:
`
`a substrate of a first doping type at a first doping level having first and second
`surfaces;
`
`a first active region disposed adjacent the first surface of the substrate with a
`second doping type opposite in conductivity to the first doping type and
`within which transistors can be formed;
`
`a second active region separate from the first active region disposed adjacent to
`the first active region and within which transistors can be formed;
`
`transistors formed in at least one of the first active region or second active
`region; and
`
`at least a portion of at least one of the first and second active regions having at
`least one graded dopant concentration to aid carrier movement from the first
`surface to the second surface of the substrate.
`
`v
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`Case 6:22-cv-00105-ADA Document 96 Filed 10/31/22 Page 7 of 46
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`DISPUTED CLAIM CONSTRUCTIONS
`
`Claim(s)
`
`Terms2
`
`Greenthread
`
`Defendants
`
`195:1
`502:7
`222:44
`
`“surface layer” and
`related terms
`
`“substrate”
`
`Plain and ordinary
`meaning, where the
`plain and ordinary
`meaning is “a layer at
`the surface”
`
`Plain and ordinary
`meaning, where the
`plain and ordinary
`meaning is an
`“underlying layer”
`
`Indefinite
`
`“the initial material
`within which or on which
`the semiconductor device
`is fabricated”
`
`#
`
`1
`
`2
`
`3
`
`4
`
`195:1
`502:7
`842:1, 9
`481:1, 20
`222:1, 21, 39,
`41, 42, 44
`014:1, 21
`
`195:1
`502:7
`842:1, 9
`481:1, 20
`222:1, 21, 39,
`41, 42, 44
`014:1, 21
`
`195:1
`502:7
`222:44
`
`“active region”
`
`Plain and ordinary
`meaning
`
`“region that forms the
`current path of a device”
`
`“said [drift layer
`further/well region …]
`having a [first/second]
`static unidirectional
`electric drift field”
`
`Plain and ordinary
`meaning
`
`“said [drift layer
`further/well region …]
`having a [first/second]
`static electric drift field
`that is unidirectional over
`the [drift layer/well
`region”
`
`“said [drift layer
`further/well region]
`having a graded
`concentration of dopants
`generating a [first/second]
`static electric drift field
`that is unidirectional over
`the [drift layer/well
`region]”
`
`“said [drift layer
`further/well region]
`having a graded
`concentration of
`dopants generating a
`[first/second] static
`unidirectional electric
`drift field”
`
`
`
`
`
`
`2 All 7 terms were identified by Defendants.
`
`vi
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`Dell Ex. 1020
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`Case 6:22-cv-00105-ADA Document 96 Filed 10/31/22 Page 8 of 46
`
`Claim(s)
`
`195:1
`502:7
`842:1, 9
`481:1, 20
`222:1, 21,
`39,
`41, 42, 44
`014:1, 21
`
`195:1
`502:7
`842:1, 9
`481:1, 20
`222:1, 21,
`39,
`41, 42, 44
`014:1, 21
`
`842:1, 9
`481:1, 20
`222:1, 21,
`39,
`41, 42
`014:1, 21
`
`
`
`#
`
`5
`
`6
`
`7
`
`
`
`
`DISPUTED CLAIM CONSTRUCTIONS (continued)
`
`Terms
`
`Greenthread
`
`Defendants
`
`Plain and ordinary
`meaning
`
`Indefinite
`
`Alternative construction:
`“to sweep the minority
`carriers from … to …
`
`
`
`Indefinite
`
`Alternative construction:
`“to sweep the carriers from
`… [to/towards] …
`
`
`
`Plain and ordinary
`meaning, where
`portions of a well are
`not well regions.
`
`“A well, whether formed
`by single or multiple
`implants. Portions of a
`well are not well regions.”
`
`Plain and ordinary
`meaning
`
`Indefinite
`
`“to aid the movement
`of minority carriers
`from ... to …”
`
`
`
`“to aid carrier
`movement from ...
`[to/towards]”
`
`“well region”
`
`“active region …
`within which
`transistors can be
`formed”
`
`
`
`vii
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`Case 6:22-cv-00105-ADA Document 96 Filed 10/31/22 Page 9 of 46
`
`AGREED CLAIM CONSTRUCTIONS
`
`Claim(s)
`
`Terms
`
`Agreed Construction
`
`“a substrate of a first
`doping type”
`
`“a substrate with either p-type
`doping or n-type doping”
`
`“disposed adjacent”
`
`Plain and ordinary meaning
`
`“isolation region”
`
`Plain and ordinary meaning
`
`842:1, 9
`481:1, 20
`222:1, 21, 39, 41, 42
`014:1, 21
`
`842:1, 9
`481:1, 20
`222:1, 21, 39, 41, 42
`014:1, 21
`
`842:7, 15
`481:6, 26
`222:6, 27
`014:6, 27
`
`#
`
`8
`
`9
`
`10
`
`
`
`viii
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`Case 6:22-cv-00105-ADA Document 96 Filed 10/31/22 Page 10 of 46
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`
`
`INTRODUCTION
`
`Greenthread’s complaint asserts six patents
`
`that
`
`improve
`
`the performance of
`
`semiconductor devices. All six patents claim priority to an application filed by Dr. Mohan Rao on
`
`September 3, 2004. Dr. Rao is one of the pioneers in the semiconductor industry. He is an award
`
`winning inventor, and his inventions are featured in the Smithsonian museum. When he filed his
`
`application in 2004, he used terms that those skilled in the art would readily understand. He did
`
`not coin any new terms, and he did not disclaim the full scope of the plain meaning. Therefore, it
`
`is not surprising that plain meaning is the proper construction for all seven disputed claim terms.
`
`For terms 2-4 and 6, Defendants attempt to limit the full scope of the plain meaning by
`
`reading in unnecessary limitations. As is often the case, Defendants are attempting to manufacture
`
`noninfringement arguments, when there was no clear disavowal, disclaimer, or estoppel.
`
`Defendants criticize Greenthread for proposing “plain meaning.” Yet for two of the three agreed
`
`constructions, it was Defendants that proposed “plain meaning.” Thus, Defendants recognize that
`
`not all terms need to be construed, and “plain meaning” is often the best construction.
`
`For the remaining terms, Defendants argue that certain phrases are indefinite. But when
`
`these terms are read in light of the specification and prosecution history, they are abundantly clear.
`
`The superficiality of Defendants’ arguments is highlighted by Greenthread’s previous litigation
`
`against Samsung. There Samsung was represented by the same counsel as here. In the Samsung
`
`litigation, Defendants’ counsel did not argue that “to aid the movement of minority carriers” or
`
`“surface layer” were indefinite or not disclosed by the specification. Instead Intel’s counsel agreed
`
`with Greenthread that the terms did not need construction. Moreover, Samsung filed IPRs where
`
`Samsung’s expert testified that he understood the terms and they should be given their ordinary
`
`meaning. The fact that Samsung’s expert understood the terms confirms they are not indefinite.
`
`1
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`Dell Ex. 1020
`Page 10
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`Case 6:22-cv-00105-ADA Document 96 Filed 10/31/22 Page 11 of 46
`
`
`
`BACKGROUND
`
`A.
`
`Dopants
`
`Silicon is an example of a semiconductor. In its pure form it is typically an insulator but it
`
`can become an electrical conductor when impurities called “dopants” are added into the silicon
`
`crystal. These dopants are usually phosphorous or boron atoms that have one more or one less
`
`valence electron than a silicon atom. If the dopant has one less valence electron, then it creates
`
`what is called a “hole,” which is a positive unit of charge. The extra electrons or holes disturb the
`
`local charge equilibrium in the silicon and can become mobile in response to electric fields. Thus,
`
`the electrons and holes are called “charge carriers.” Ex. 1 (Giapis declaration), ¶15; id., ¶¶1-14.
`
`These dopants can also change the net electrical charge distribution in the surrounding
`
`silicon, which can influence the motion of other charge carriers passing by. When the dopant
`
`concentration is graded in a particular direction, other charge carriers will move in the gradient
`
`direction (or opposite direction) depending on the charge carrier’s polarity. This phenomenon is
`
`called “carrier drift.” Id., ¶16.
`
`B.
`
`Overview of Dr. Rao’s Invention
`
`At the time of Dr. Rao’s invention, most semiconductor devices relied on uniform
`
`concentrations of dopants. Ex. 2 (195 patent), Abstract; 1:36-40, 50-51. Dr. Rao recognized,
`
`however, that graded concentrations of dopants can be used to improve the performance of
`
`transistors and other semiconductor devices. Id., Abstract; 3:3-13, 33-35. His invention is clearly
`
`disclosed in Figs. 5B-C of his patents, and the corresponding parts of the specification. Ex. 1, ¶17.
`
`A surface-channel MOSFET is a common type of transistor capable of controlling current
`
`flow at or along the surface of the semiconductor substrate. Ex. 4 (Chen), 27 (“carriers propagate
`
`2
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`Dell Ex. 1020
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`Case 6:22-cv-00105-ADA Document 96 Filed 10/31/22 Page 12 of 46
`
`at the semiconductor surface”). Figure 5B shows an n-channel MOS (NMOS)3 transistor that is
`
`formed in a p-type surface layer. The transistor comprises (1) a gate; (2) a thin oxide separating
`
`the gate from the surface layer; and (3) two doped regions called the source and drain (shaded red).
`
`Ex. 2, 3:10-11 (“electrons can be swept from source to drain”); 3:42-43 (“accelerate majority
`
`carriers towards the drain”). In Fig. 5B, the N+ means these regions are heavily doped with an n-
`
`type dopant that creates a surplus of negative carriers (i.e., electrons).4 The specification explains
`
`that the NMOS transistor in Fig. 5B can be a surface-channel MOSFET. Ex. 1, ¶¶18-21.
`
`Ex. 1, ¶21 (explaining Fig. 5B above); Ex. 2:41-43. Meanwhile, the p-type silicon between the
`
`source and drain (shaded blue) has an abundance of positively charged holes (green circles). When
`
`the holes separate the source’s electrons from the drain’s electrons, current cannot flow through
`
`
`
`the transistor, and the transistor is in an “off” state. Ex. 1, ¶¶21-22.
`
`When a positive voltage is applied to the gate, an electric field forms in the oxide. Id. This
`
`electric field repels the holes downwards, while the electrons (red circles) are attracted to move
`
`into the blue surface layer. When enough electrons have accumulated in the surface layer below
`
`
`3 MOS stands for “metal oxide semiconductor,” where metal and oxide layers are formed on a
`semiconductor (e.g., silicon). Ex. 1, ¶21 n.3; Ex. 4, 10.
`
`4 An “N” region or layer has more electrons, and thus a “negative charge.” A “P” layer has more
`holes, and a “positive charge.” A “+” or “-” means heavily or lightly doped. Ex. 1, ¶21 n.4.
`
`3
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`Case 6:22-cv-00105-ADA Document 96 Filed 10/31/22 Page 13 of 46
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`the oxide, they form a conductive channel between the source and the drain, and current can begin
`
`to flow through the transistor.
`
`
`Ex. 1. ¶22.5 In order to turn the transistor “off,” the positive voltage is removed from the gate and
`
`the channel disappears as the holes return to the surface layer. Id.
`
`POSITAs normally use the term “well region” to describe the doped silicon that surrounds
`
`the source and drain. Id., ¶23. Dr. Rao recognized that by using graded concentrations of dopants
`
`in the well region and a drift layer (shaded pink), it is possible to “pull” carriers from the silicon’s
`
`surface. Ex. 2, Fig. 5B. In this example, pulling the holes from the surface layer when a positive
`
`voltage is applied to the gate, allows the transistor to turn “on” more quickly. This improves the
`
`speed and performance of the transistor. Ex. 1, ¶24; Ex. 2, 3:8-13.
`
`As its name suggests, the channel in a surface channel MOSFET forms along the surface.
`
`But it is slightly more complicated than that. The figure below shows that the n-channel starts at
`
`the source (on the left) and expands towards the drain (on the right) as the voltage applied to the
`
`gate increases. There is a thin layer below the surface (shaded red) where the channel actually
`
`forms. Ex. 1, ¶25.
`
`
`5 Because the channel is formed by electrons with a negative charge, the MOSFET is referred to
`as an n-channel MOSFET. In an n-channel MOSFET, the electrons are referred to as the “majority
`carriers,” and the “minority carriers” are holes. Ex. 1, ¶22 n.5.
`
`4
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`Dell Ex. 1020
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`Case 6:22-cv-00105-ADA Document 96 Filed 10/31/22 Page 14 of 46
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`Ex. 1, ¶25; Ex. 4, 19 (shaded). The cross-hatched region underneath is known as the depletion
`
`region. As shown above, the n-channel does not actually form on the surface but rather in the layer
`
`
`
`just below the surface (i.e., the surface layer). Ex. 1, ¶25.
`
`C.
`
`Exemplary Claim 195:1
`
`Six of the seven disputed claim terms can be found in exemplary claim 195:1. These six
`
`claim terms are numbered and color coded below.
`
`Term
`
`U.S. Patent No. 8,421,195, Claim 1 (195:1)
`
`A CMOS Semiconductor device comprising:
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`a surface layer;
`
`a substrate;
`
`an active region including a source and a drain, disposed on one surface of said surface layer;
`
`a single drift layer disposed between the other surface of said surface layer and said substrate,
`said drift layer having a graded concentration of dopants extending between said surface
`layer and said substrate, said drift layer further having a first static unidirectional electric
`drift field
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`to aid the movement of minority carriers from said surface layer to said substrate; and
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`at least one well region disposed in said single drift layer, said well region having a graded
`concentration of dopants and a second static unidirectional electric drift field to aid the
`movement of minority carriers from said surface layer to said substrate.
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`Far from being indefinite, claim 195:1 lines up exactly with Fig. 5B and the corresponding parts
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`of the specification. Ex. 1, ¶¶26-27. Fig. 5B confirms exactly what is meant by each claim term.
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`As the preamble states, Fig. 5B illustrates a CMOS device with metal and oxide layers on a silicon
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`substrate. Ex. 2, 2:27-31; 3:41-43. The specification specifically mentions that the device may be
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`a surface channel MOSFET. Id., 3:41-43; see also 1:43-45.
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`As seen below, the CMOS device comprises a surface layer (blue) and a substrate (gray).
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`Id., 3:30-45. The substrate is lightly doped with holes (P-), and the surface layer is a layer at the
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`surface of the silicon. As explained below, the invention is concerned with moving minority
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`carriers from this surface layer to the substrate.
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`Ex. 1, ¶28.6 The surface layer has at least two surfaces, which claim 195:1 refers to as the “one
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`surface of said surface layer” and “the other surface of said surface layer.”
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`Ex. 1, ¶29; Ex. 2, 4:16-19. Next, the claim specifies an active region with a source and drain. Id.,
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`4:16-17. Fig. 5B shows how the active region is “disposed on one surface of said surface layer.”
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`6 As explained below, “substrate” is a relative term, and Dr. Rao sometimes used it to refer to the
`bottom layer, and other times he used it to refer to the wells that are underneath the surface layer
`and active region. In both cases, the “substrate” is an “underlying layer.” Ex. 1, ¶28 n.6.
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`6
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`Ex. 1, ¶30. The “active region” is a doped region where a transistor can be formed. Id., ¶31; Ex.
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`2, 1:61-63; 2:18-23; 3:1-3, 30-33. Next, the claim specifies there is a single drift layer disposed
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`between “the other surface of said surface layer” and the substrate. The single drift layer has a
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`
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`graded concentration of dopants. Ex. 1, ¶32.
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`The graded dopants create an electric field that aids the movement of minority carriers (holes in
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`the example shown in Fig. 5B) from the surface layer to the substrate. Ex. 1, ¶¶32-33; Ex. 2, 3:17-
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`20, 30-37. Finally, the claim specifies there is a well region disposed in the single drift layer, and
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`
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`this well region creates a second electric field that also aids the movement of minority carriers.
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`Ex. 1, ¶34; Ex. 2, 2:27-28; 3:37-40.
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`7
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`D.
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`Exemplary Claim 842:1
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`According to claim 195:1, the “active region” includes the heavily doped regions called
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`the “source” and the “drain.” Exemplary claim 842:1 sheds additional light on the “active region”
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`when it specifies the “active region” is a region “within which transistors can be formed.”
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`Term
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`
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`U.S. Patent No. 10,510,842, Claim 1 (842:1)
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`A semiconductor device, comprising:
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`a substrate of a first doping type at a first doping level having first and second surfaces;
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`a first active region disposed adjacent the first surface of the substrate with a second doping type
`opposite in conductivity to the first doping type and within which transistors can be formed;
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`
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`a second active region separate from the first active region disposed adjacent to the first active
`region and within which transistors can be formed;
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`transistors formed in at least one of the first active region or second active region; and
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`at least a portion of at least one of the first and second active regions having at least one graded
`dopant concentration to aid carrier movement from the first surface to the second surface of
`the substrate.
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`According to claim 842:1, there may be multiple active regions (i.e., the first and second
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`active regions), where a transistor is formed in at least one of them (i.e., transistors formed in at
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`least one of the active regions). Ex. 1, ¶¶35-36; Ex. 3, 4:48-56.
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` DISPUTED CLAIM TERMS
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`For terms 2-4 and 6, Defendants ignore the well-accepted plain and ordinary meaning of
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`the terms. The terms—substrate, active region, unidirectional, and well region—are simple terms
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`that don’t need construction. Instead of giving them the full scope of their plain meaning,
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`Defendants seek to add self-serving limitations that are inconsistent with the intrinisic record.
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`Defendants’ indefiniteness arguments ignore the specification and misapply the law. When
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`the specification is properly read through the eyes of a POSITA7, Defendants cannot meet their
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`7 Dr. Giapis explains the qualifications for a POSITA. Ex. 1, ¶¶1-14. When Dr. Rao conceived
`his inventions, he had not one, but two Ph.D.s and had been working in the industry for more than
`forty years. Dkt. 1, ¶¶37-39.
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`heavy burden of proving the terms are indefinite. In fact, Intel’s counsel argued in the Samsung
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`litigation that many of these terms should be given their plain meaning, and Samsung’s expert
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`opined that he understood the terms.
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`A.
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`Claim Terms Found in Exemplary Claim 195:1
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`1.
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`“surface layer” terms (195:1; 502:7; 222:44)
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`Greenthread
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`Plain and ordinary meaning, where the plain and ordinary
`meaning is “a layer at the surface”
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`Defendants
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`Indefinite
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`Far from being indefinite, “surface layer” is a lay term that is understood by skilled artisans
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`and lay people alike. Ex. 1, ¶¶46-63. Whether it is the surface layer of the ocean, skin, soil in a
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`backyard garden, or a semiconductor device, it is referring to the same thing: a layer at the surface.
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`Even the Wolf textbooks cited by Defendants confirm that a “surface layer” is a layer at the surface
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`of the semiconductor device where the active region is located. Id., ¶46.
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`Ex. 1, ¶46; Dkt. 82-17 (Wolf Vol. 3), 11 (describing MOSFET with source and drain); Dkt. 82-18
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`
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`(Wolf Vol. 4), 7, 10 (describing “surface layer” of MOSFET as doped silicon near surface).
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`Defendants’ indefiniteness arguments are fundamentally flawed because (1) they ignore
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`the realities of surface-channel MOSFETs and the preferred embodiment disclosed in Fig. 5B, and
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`(2) they wrongly assume the surface layer is “disposed under the active region.” Ex. 1, ¶47. Dkt.
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`82, 14 (emphasis in original). The claims never use the words “disposed under.” It is a fiction
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`Defendants created. When Defendants say it is “paradoxical” that the “surface layer” is not at the
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`surface of the semiconductor device, it is not paradoxical; it is simply wrong.
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`The test for indefiniteness is whether the claims, viewed in light of the specification and
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`prosecution history, inform those skilled in the art about the scope of the invention with reasonable
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`certainty. Nautilus, Inc. v. Biosig Instruments, 572 U.S. 898, 910 (2014). The test is not whether
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`the words “surface layer” appear in the specification, but whether a POSITA would have known
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`what was meant by the term after reading the intrinsic record. Here, the claims, specification, and
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`prosecution history confirm that the “surface layer” is the layer at the surface of the silicon. This
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`is not surprising given this is how the term is normally used in the art. Ex. 1, ¶¶47-48.
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`The claim language confirms that the “surface layer” is a layer at the surface of the
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`semiconductor device. First, a POSITA would readily understand that a “surface layer” is a layer
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`at the surface of the semiconductor device. Id., ¶48. This is because it is customary to refer to
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`layers by their relative position. For example, a “bottom layer” is at the bottom; a “middle layer”
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`is at the middle; and a “surface layer” is at the surface. Defendants do not contend that it is unclear
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`what is meant by the “surface” of a CMOS device. It is the doped silicon where the active region
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`is located, and where the channel forms in a surface-channel MOSFET. Therefore, it should go
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`without saying that a “surface layer” is a layer at the surface of the semiconductor device.
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`Second, the claim specifies that the “surface layer” has two surfaces and that the “active
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`region” is “disposed on one surface of the said surface layer.” From this claim language,
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`Defendants create the “straw man” shown below.
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`Defendants’ “Straw Man”
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`Correct Interpretation
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`10
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`Dkt. 82, 11. Defendants’ rendering ignores that the “active region” is part of the “surface layer,”
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`just like the “well region” is part of the “single drift layer.” When the claim says the “active
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`region” is “disposed on one surface of said layer,” it is not saying it is a separate layer on top of
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`the “surface layer.” Rather it is specifying where in the “surface layer” the “active region” is
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`located. Instead of being anywhere in the surface layer, the “active region” is disposed on the top
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`surf