United States Patent (19)
`Gupta
`
`USOO6163877A
`Patent Number:
`11
`(45) Date of Patent:
`
`6,163,877
`*Dec. 19, 2000
`
`54
`
`(75)
`73)
`
`METHOD AND APPARATUS FOR
`OPTIMIZING TRANSISTOR CELL LAYOUT
`WITH INTEGRATED TRANSISTOR
`FOLDING
`
`Inventor: Avaneendra Gupta, Ann Arbor, Mich.
`Assignee: Intel Corporation, Santa Clara, Calif.
`Notice:
`This patent issued on a continued pros
`ecution application filed under 37 CFR
`1.53(d), and is subject to the twenty year
`patent term provisions of 35 U.S.C.
`154(a)(2).
`
`Appl. No.: 08/744,199
`Filed:
`Nov. 5, 1996
`Int. Cl. .............................................. H01L23/50
`U.S. Cl. ................................................................... 716/8
`Field of Search ..................................... 364/488, 489,
`364/490, 491; 716/8
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,737,236 4/1998 Maziasz et al. ........................ 364/490
`OTHER PUBLICATIONS
`A. Gupta, S. The, P. Hayes, “XPRESS: A Cell Layout
`Generator with Integrated Transistor Folding', The Euro
`pean Design & Test Conference 1996, pp. 393-400.
`Primary Examiner Paul R. Lintz
`ASSistant Examiner Thuan Do
`Attorney, Agent, or Firm Blakely, Sokoloff, Taylor &
`Zafman LLP
`ABSTRACT
`57
`A computer implemented method for generating a layout for
`a Set of transistors on a Semiconductor chip. The method
`comprises the Step of folding transistors of the Set whose
`sizes exceed a predetermined maximum size. Then a list of
`implicitly enumerated diffusion Sharing arrangements of the
`transistors of the Set is created. The method also comprises
`the Step of choosing an arrangement from the list that uses
`the least horizontal Space on the chip and generating a layout
`of the Set of transistors on the chip according to the chosen
`arrangement. Embodiments of the invention generate diffu
`Sion Sharing arrangements that are unique with respect to
`transistor folds, transistor orientations, and transistor fold
`interlacing arrangements.
`
`5,675,501 10/1997 Aoki ........................................ 364/490
`5,701,255 12/1997 Fukui ...................................... 364/491
`
`29 Claims, 14 Drawing Sheets
`
`FORSET OF PIN PARS
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`916
`
`UNPAIRED DEVICES
`
`NO
`
`920
`
`918
`
`
`
`YES
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`REDEFINE SET OF PIN PARSTO
`INCLUDE ONLY CHANS IN CAND
`UNPARED DEVICES
`
`TECHNOLOGY MAPPING
`
`922
`
`CELLLAYOUT
`
`Dell Ex. 1014
`Page 1
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`

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`U.S. Patent
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`Dec. 19, 2000
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`Sheet 1 of 14
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`6,163,877
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`Dell Ex. 1014
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`U.S. Patent
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`Dec. 19, 2000
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`Sheet 2 of 14
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`6,163,877
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`Y
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`Dell Ex. 1014
`Page 3
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`U.S. Patent
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`Dec. 19, 2000
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`Sheet 3 of 14
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`6,163,877
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`Dell Ex. 1014
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`U.S. Patent
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`Dec. 19, 2000
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`Sheet 4 of 14
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`Dell Ex. 1014
`Page 5
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`U.S. Patent
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`Dec. 19, 2000
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`Sheet S of 14
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`6,163,877
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`EB- 0O 8 W/E- 0 O 8 \!
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`Dell Ex. 1014
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`U.S. Patent
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`Dec. 19, 2000
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`Sheet 6 of 14
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`6,163,877
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`616
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`U.S. Patent
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`Dec. 19, 2000
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`Sheet 7 of 14
`N3
`-71 N.
`A B C C B A
`A B C
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`704 Y
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`6,163,877
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`Dell Ex. 1014
`Page 8
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`

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`U.S. Patent
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`6,163,877
`
`N
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`U.S. Patent
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`Dec. 19, 2000
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`Sheet 9 of 14
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`6,163,877
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`ENTER CIRCUIT
`
`902
`
`DENTIFY LOGICAL CLUSTERS
`
`9 04
`
`GENERATE ALL TRANSISTOR CHAINS
`FOR SET OF P/N PARS
`
`910
`
`GENERATE CHAIN COVERS
`
`SELECT BEST COVER C
`
`912
`
`914
`
`916
`NO
`
`UNPAIRED DEVICES
`
`918
`
`
`
`YES
`
`REDEFINE SET OF PIN PARS TO
`INCLUDE ONLY CHAINS IN CAND
`UNPAIRED DEVICES
`
`920
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`922
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`Dell Ex. 1014
`Page 10
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`

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`U.S. Patent
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`Dec. 19, 2000
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`Sheet 10 of 14
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`6,163,877
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`
`
`-
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`Ul
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`-
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`Y-
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`SN 2
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`OL 2
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`U.S. Patent
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`Dec. 19, 2000
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`Sheet 11 of 14
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`6,163,877
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`PAIR
`
`REASON FOR PARING
`
`TRANSMISSION GATE
`
`COMMON
`GATE NET
`
`PAIR7 (P7, N7)
`PAIR8 (P8, N8)
`PAIR9 (P9, Ng)
`
`
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`COMMON DIFFUSION
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`
`
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`U.S. Patent
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`Dec. 19, 2000
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`Sheet 12 of 14
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`6,163,877
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`LOET
`
`LGT
`§~~ ~)
`
`CD// CD
`
`-:-zá-El
`
`PAIR2
`
`PAIRS: (P, N) AND
`P2, N2)
`(
`EG - A
`
`1100 N.
`
`
`
`No. ZZZ `
`
`LGBT
`LOET
`
`PAIR
`
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`
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`U.S. Patent
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`Dec. 19, 2000
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`Sheet 13 of 14
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`6,163,877
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`1202
`
`PAIR: 5, 9
`PAR: 3, 5, 6, 7, 8
`2. 3, o, O, f,
`Y PAIRs 2,5,6,7,8
`PAIR4: 6,6
`PAIR5: 1,2,3,6,7,8
`PAIR6: 2, 3, 4,4,5,7,8
`PAIR7: 2, 3, 5, 6, 8, 9
`PAIR8: 2, 3, 5, 6, 7
`PAIRg 1,7
`ADJACENCY LIST IN THE FORM
`< PAR: LIST OF PARS THAT CAN
`SHARE DIFFUSION >
`
`1204
`
`CHAINLENGTH NO OF CHAINS
`
`
`
`
`
`72(TOTAL)
`CLASSIFICATION OF CHAINS
`BYLENGTH
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`F
`
`- A
`
`CLIOUE
`i
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`
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`
`
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`CHAINS (ORDEREDLIST OF PAIRS)
`CHAIN #1
`CHAIN #2
`
`
`
`INTERCONNECT
`COST
`
`
`
`40
`37
`29
`27
`20
`14
`
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`U.S. Patent
`
`Dec. 19, 2000
`
`Sheet 14 of 14
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`6,163,877
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`
`
`PROCESSOR
`
`FOLD
`
`GENERATE
`CHAINS
`
`SELECT
`BEST COVER
`
`FORM
`P/N PARS
`
`GENERATE
`CHAIN COVERS
`
`MAP
`
`REDEFINE SET
`OF PIN PARS
`
`PRODUCE
`LO
`
`APPLICATION 1306
`
`Dell Ex. 1014
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`

`

`1
`METHOD AND APPARATUS FOR
`OPTIMIZING TRANSISTOR CELL LAYOUT
`WITH INTEGRATED TRANSISTOR
`FOLDING
`
`FIELD OF THE INVENTION
`The present invention relates to the field of complimen
`tary metal oxide semiconductor (CMOS) circuits, and more
`particularly to automatically producing layouts for CMOS
`circuits.
`
`BACKGROUND OF THE INVENTION
`Today's very large Scale integrated circuits typically use
`CMOS technology. CMOS technology is advantageous in
`very large Scale integrated circuit applications because of its
`relatively small power dissipation. CMOS devices include
`combinations of n-channel MOS (NMOS) and p-channel
`MOS (PMOS) transistors on adjacent regions of a semicon
`ductor chip. FIG. 1 is a simplified illustration of a cross
`section of a semiconductor chip 100. Regions of n-type
`material and p-type material are shown for p-channel device
`102 and n-channel device 104. Regions of p-type or n-type
`material are also known as diffusion areas. Diffusion refers
`to the net motion of charge carriers from regions of high
`carrier concentration to regions of low carrier concentration.
`Diffusion represents the charge transport process in Semi
`conductors.
`AS Semiconductor chips become ever larger, incorporat
`ing ever more devices, it becomes increasingly important to
`minimize Semiconductor area used by a given number of
`devices. Conservation of Semiconductor area is a primary
`goal in Semiconductor chip development because even a
`Small added Semiconductor area potentially translates into
`millions of dollars. Another goal of Semiconductor devel
`opment is to improve device performance. Device
`performance, simply Stated, is the ability of the circuit to
`operate correctly with as great a speed as possible. The goal
`of Saving Semiconductor area and the goal of increasing
`device performance are usually interrelated. For instance, if
`devices are placed on a Semiconductor chip closer together,
`the length charge must travel is reduced and greater Speed is
`realized.
`Various design factors complicate the task of designing a
`circuit for a Semiconductor chip So as to minimize area
`usage. For example, transistor Sizes vary in practical circuit
`designs, resulting in non-uniform transistor heights, which
`can lead to wasted Semiconductor area.
`Several techniques have been developed to address the
`problem of achieving optimal layout, where optimal layout
`refers to an arrangement of devices on a Semiconductor chip
`So as to minimize area and maximize performance. One
`technique conserves area by placing transistorS So as to share
`diffusion area. FIG. 2 illustrates this technique. Transistor
`layout 203 is a representation of a layout of a transistor
`whose Schematic representation is 202. Similarly, transistor
`layout 205 represents a possible layout of a transistor
`represented by schematic 204. Because of the orientation of
`a drain diffusion area to the left of layout 205 and to the right
`of layout 203, the two transistors can be placed such that
`they share the drain diffusion area.
`Another technique for conserving Semiconductor area is
`known as transistor folding. Transistor folding is a proceSS
`of converting a transistor into Smaller, multiple transistors
`called folds, or legs, which are connected in parallel and
`must be placed together on a Semiconductor chip. Transis
`tors are folded in order to meet predetermined maximum
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`height requirements. FIG. 3 shows a transistor before and
`after folding. Schematic 302 shows one transistor before
`folding. Schematic 306 is equivalent to schematic 302.
`Schematic 306 represents the transistor of schematic 302
`after folding into two legs or folds. Layout 304 represents a
`layout of schematic 302. Layout 308 is one possible layout
`of schematic 306. Layout 310 is an alternate possible layout
`of schematic 306. Layout 308 is referred to as an unflipped
`orientation, and layout 310 is referred to as a flipped
`orientation.
`The orientation of transistors after folding can have an
`effect on area usage. For example, note that two layouts 308
`or two layouts 310 can be abutted so that a diffusion area is
`shared. However, a layout 308 and layout 310 cannot be
`abutted because the Source and drain diffusion areas are not
`electrically equivalent.
`Transistors which are abutted in a layout form transistor
`chains. It is desirable to produce a layout with a maximum
`number of transistors chained So as to minimize diffusion
`gapS.
`Thus, a variety of available design techniques Such as
`chaining of transistors, folding of transistors and flipping of
`folded transistors are available to the layout designer. This
`variety makes the transistor circuit layout process extremely
`complex. For this reason, design of transistor circuit layouts
`is a major contribution to design cycle time and cost.
`Software tools currently exist which automatically gen
`erate layouts of a given circuit based upon cells, where a cell
`is an arrangement of transistors without multiple levels of
`hierarchy. Such tools are known as cell Synthesis tools. Cell
`Synthesis tools typically take a circuit description as input in
`the form of a net list or a Schematic and output a graphical
`layout showing arrangement of transistors as an arrangement
`of diffusion areas on a Semiconductor chip. Cell Synthesis
`tools make layout design faster, but benefits of prior Syn
`thesis tools are limited by their inability to fully consider
`design constraints or to take full advantage of techniques
`which Save Semiconductor area and increase circuit perfor
`CC.
`One limitation of Some prior art cell Synthesis tools is that
`they make Several impractical Simplifying assumptions
`about the circuit. For example, they assume an equal number
`of p-type devices and n-type devices, uniform transistor Size,
`and no transistor folding. Some prior art cell Synthesis tools
`can perform transistor folding, but only perform Simple
`transistor folding in a way that Significantly decreases the
`effectiveness of the folding technique in producing
`improved layouts. Typically, prior art cell Synthesis tools
`receive a circuit description and then map the circuit to a
`Semiconductor chip. Mapping, also known as placing, is the
`process of Specifying transistor locations on a physical
`device. After placement, simple folding is then performed
`without consideration of all possible orientations of transis
`tors. Significantly, prior cell Synthesis tools also fail to
`consider all possible combinations of transistors to produce
`chains. This results in a Sub-optimal circuits with respect to
`area and performance. For example, because different ori
`entations of transistors are not considered (flipped and
`unflipped), unnecessary diffusion gaps usually exist as
`explained previously with respect to FIG. 3.
`For these reasons, graphical layouts produced using prior
`art cell Synthesis tools usually require extensive manual
`rearrangement to improve performance and decrease area.
`This manual rearrangement adds to the overall cost of
`development and production. In addition, with manual
`optimization, there is no guarantee that device arrangements
`
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`3
`have been exhaustively Sampled to produce an optimum
`achievable layout that meets all physical design rules.
`AS will be shown, the present invention provides an
`improved method and apparatus that more advantageously
`uses optimization techniques to produce a cell layout of
`minimum area that meets design constraints and physical
`design rules.
`
`SUMMARY OF THE INVENTION
`A computer implemented method for generating a layout
`for a set of transistors on a Semiconductor chip is described.
`The method comprises the Step of folding those transistors
`of the Set whose sizes exceed a predetermined maximum
`size. Then a list of implicitly enumerated diffusion sharing
`arrangements of the transistors of the Set is created. The
`method also comprises the Steps of choosing an arrangement
`from the list that uses the least horizontal Space on the chip
`and generating a layout of the Set of transistors on the chip
`according to the chosen arrangement.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a simplified croSS-Sectional view of a Semicon
`ductor chip;
`FIG. 2 is an illustration of diffusion sharing;
`FIG. 3 is an illustration of a transistor before and after
`folding showing flipped and unflipped layouts;
`FIG. 4 is an illustration of transistor chains with a
`diffusion gap,
`FIG. 5 is an illustration of the effect of folding on
`diffusion sharing;
`FIG. 6 is an illustration of the effect of folding a transistor
`into an odd or an even number of folds on the terminals that
`appear at the ends of folded transistors,
`FIG. 7a is a Schematic diagram of a transistor circuit,
`FIG. 7b is a layout of a schematic;
`FIG. 7c is a layout of a schematic with fold interlacing;
`FIG. 7d a layout of a schematic with no fold interlacing
`and diffusion gaps,
`FIG. 7e a layout of a schematic with fold interlacing and
`no diffusion gaps,
`FIG. 8a is a left justified transistor layout;
`FIG. 8b is a centered transistor layout;
`FIG. 8c is a right justified transistor layout;
`FIG. 9 is a flow chart of an embodiment of the present
`invention;
`FIG. 10a is a Schematic diagram of a transistor circuit;
`FIG. 10b is a table of P/N pairs;
`FIG.11a is a transistor layout of a particular P/N pairing;
`FIG.11b is a transistor layout of a particular P/N pairing;
`FIG.12a is a list of P/N pairs with their classification by
`length;
`FIG.12b is a table of cliques according to an embodiment
`of the present invention; and
`FIG. 13 is a simplified block diagram of a computer
`System implementing one embodiment of the present inven
`tion.
`
`DETAILED DESCRIPTION
`AS will be shown, the present invention produces better
`layouts by considering transistor folding before placement.
`The present invention also takes fuller advantage of design
`techniques other than transistor folding during the formation
`
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`of transistor chains. In addition, the present invention
`improves layouts with the novel technique of transistor fold
`interlacing, which will be described below.
`In the following detailed description of the present
`invention, numerous Specific details are Set forth in order to
`provide a thorough understanding of the present invention.
`However, it will be apparent to one skilled in the art that the
`present invention may be practiced without these specific
`details. In other instances, well know methods, procedures,
`components, and circuits have not been described in detail
`to avoid obscuring the present invention.
`FIG. 4 is an illustration of a layout style known as one
`dimensional layout style. The present invention will be
`described as producing a layout of the one dimensional Style,
`but other embodiments could be used to produce layouts of
`other Styles. For example, other embodiments could produce
`layouts in gate matrix layout Style. Gate matrix layout Style
`is characterized by equally Spaced vertical polysilicon col
`umns that Serve as transistor gates and general interconnects.
`Gate matrix layout Style is also characterized by rows of
`diffusion and metal, with the intersection of horizontal
`diffusion and Vertical polysilicon forming transistors.
`Referring to FIG. 4, one dimensional layout 402 includes
`two horizontal diffusion rows for the placement of P and N
`transistors. PMOS transistors are placed in top row 418 and
`NMOS transistor are placed in bottom row 420. If two
`adjacent transistors have electrically equivalent terminals,
`they are abutted So as to share a diffusion area, forming a
`chain. Otherwise, they require a diffusion gap between them.
`NMOS and PMOS transistors are paired to form chains.
`FIG. 4 shows transistor chain 400 and transistor chain 402
`with diffusion gap 404 between them.
`Transistor 408 is typical of PMOS transistors in PMOS
`row 418. Transistor 409 is typical of an NMOS transistor in
`NMOS row 420. Transistors 408 and 409 form a P/N pair.
`P diffusion/metal contact 410 is part of PMOS transistor 408.
`N diffusion/metal contact 412 is part of NMOS transistor
`409. P/N channel 406 is located between rows 418 and 420.
`Polysilicon area 414 is typical of polysilicon areas in P/N
`channel 406. First metal layer 416 is typical of a first metal
`layer connecting diffusion-metal contacts of members of a
`P/N pair.
`FIG. 5 illustrates the effect of folding on diffusion sharing,
`as well as the advantage of folding before placement.
`Schematic 500 is an example of a transistor circuit. The
`circuit of schematic 500 includes a power terminal Vcc, and
`a ground terminal G. The circuit of schematic 500 includes
`transistors A, B, C, D, E and F. The transistors of Schematic
`500 can be arranged in a variety of chains. For example,
`layout 502 is a layout of the circuit using a chain A, B, C,
`D, E, and single transistor F. In FIG. 5, a representation of
`a transistor in a layout is shown as the outline of the
`transistor. For example, transistor F of layout 502 is an
`outline of a transistor without Source, gate and drain explic
`itly labeled as in FIG. 3. Layout 502 illustrates that the
`transistorSA through F are of variable sizes. Because of the
`electrical nature of the respective terminals, or nets on the
`left and right ends of chain ABCDE and of transistor F,
`transistor F cannot share diffusion in layout 502 with chain
`ABCDE, and therefore a gap exists between them. Layout
`504 is produced by folding transistor F of layout 502 into
`two folds, as required by predetermined height require
`ments. A diffusion gap Still exists between E and Finlayout
`504. Layout 504 is an example of folding performed after
`layout without consideration of relative positions of transis
`tors in a chain.
`
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`S
`Layout 506 is a layout of transistors A through Farranged
`in the order A, B, C, D, F, and single transistor E. A diffusion
`gap exists between transistors E and F. However, as illus
`trated in layout 508, the diffusion gap can be eliminated by
`folding transistor F in its location of layout 506 into two
`folds. Thus it is shown that if folding and relative placement
`of transistors are taken into consideration before layout, as
`in the present invention, diffusion gaps can be eliminated.
`FIG. 6 illustrates the effects that folding a transistor into
`an odd or an even number of folds has on the terminals that
`appear at the ends of folded transistors. Schematic 602 is a
`representation of a transistor including Source, gate and
`drain nets S, g, and d respectively. Layout 604 is a repre
`sentation of the transistor of Schematic 602. Schematic 606
`represents the transistor of schematic 602 folded into three
`folds. Schematic 606 represents the folded transistor as three
`parallel transistorS all sharing a Source net and a drain net.
`Layout 608 and 610 are alternate layouts of schematic 606.
`As shown, a transistor folded into an odd number of folds
`retains the same terminals at the two ends of the layout
`irrespective of its orientation (flipped or unflipped). A ter
`minal S and a terminal d appear at ends of both unflipped
`layout 608 and flipped layout 610. Terminals appears on the
`left in layout 608, and terminals appears on the right in
`layout 610.
`With an even number of folds, however, the terminals at
`the ends of a layout depend upon a transistors orientation.
`This is illustrated in layouts 614 and 616 which are various
`orientations of transistor 602 as folded into two folds.
`Schematic 612 shows the transistor of 602 as two parallel
`transistors sharing a Source net and a drain net. Schematic
`612 can be laid out So as to include a Source terminal at
`either end of the layout as shown in layout 614, or so as to
`include drain terminals at either end as shown in layout 616.
`Both orientations should be considered for possible abut
`ment with other transistors. The present invention, unlike
`prior layout methods, considers both even and odd number
`of folds, where appropriate, and all orientations of transistor
`layouts before forming of chains or placement.
`A disadvantage of prior art layout methods is that folding
`a transistor into an even numbers of folds always introduces
`a diffusion gap between chains. The present invention over
`comes this disadvantage and actually exploits even number
`of folds to eliminate diffusion gaps as explained earlier with
`respect to FIG. 5. The present invention incorporates fold
`interlacing into an automatic process for producing layouts.
`Previously, fold interlacing was only performed manually,
`after a layout was produced. Referring to FIGS. 7a through
`7e, the effects of fold interlacing on layout can be seen. FIG.
`7a includes Schematic 700 with three transistors, N1, N2,
`and N3 arranged in Series. A, B and C are gate terminals of
`transistors N1, N2, and N3, respectively. Terminal X is a
`power terminal of the circuit of schematic 700. Terminals Y
`and Z are shared between N1, N2, and N3, respectively. For
`example, terminal Y serves as the drain terminal of N1 and
`the Source terminal of N2. Terminal Z serves as the drain
`terminal of N2 and the Source terminal of N3. Terminal W
`is the ground terminal for the circuit of schematic 700.
`Terminals X and W carry power and ground Signals in this
`embodiment, but in other embodiments could carry any
`other Signals.
`FIG. 7b shows layout 702, one possible layout of the
`circuit of schematic 700 in which transistors N1, N2, and N3
`are laid out consecutively as one chain. For layout 702, each
`transistor N1, N2, and N3 is folded into three folds.
`FIG. 7c shows layout 704. Layout 704 is a layout of
`transistors N1, N2, and N3, each folded into three folds, but
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`interlaced. Layout 704 illustrates that when transistors are
`folded into an odd number of folds, the nets that appear on
`the left and right ends of the layout are the same, in this case
`X and W, irrespective of interlacing. When the devices are
`folded into an even number of folds, however, the nets at the
`ends of the placement differ based on whether the devices
`are interlaced or not.
`FIG. 7d illustrates layout 706, of transistors N1, N2, and
`N3 each folded into two folds. Without interlacing, one
`diffusion gap appears between transistorS N1 and N2, and
`another diffusion gap appears between transistorS N2 and
`N3. One of the diffusion gaps could be eliminated by
`flipping one of the transistors, but without fold interlacing,
`both diffusion gaps cannot be eliminated. Layout 708 of
`FIG. 7e shows that both of the diffusion gaps, even with an
`even numbers of folds, can be eliminated by fold interlacing.
`The present invention, unlike prior art methods, Supports all
`possible interlacing regardless of the number of folds per
`transistor, while producing an optimal final placement.
`Fold interlacing also provides the following layout area
`and performance advantages over non-interlaced place
`ments. First, unlike non-interlaced layouts, internal nets,
`such as nets Y and Z in FIGS. 7a through 7e in the interlaced
`layout do not need to be Strapped because they share
`diffusion. Therefore, the corresponding devices can be
`placed closer together. This allows denser layout and Saves
`layout area. In addition because layouts can be denser, the
`diffusion area on the internal nets is reduced. This leads to
`better electrical (Switching) properties, which equates with
`better circuit performance. For these reasons, fold interlac
`ing must be considered in developing layouts for compo
`nents like high performance microprocessors, where area
`and performance concerns are critical. In large Scale pro
`duction of high performance components, performing fold
`interlacing manually is not feasible. The present invention
`allows the use of fold interlacing in large Scale production by
`incorporating it into an automatic process.
`FIGS. 8a through 8c illustrate another technique used by
`the present invention to optimize placement for P/N pairs
`having transistors with unequal numbers of folds. FIG. 8a
`shows a layout 800 including a PMOS transistor 806 and an
`NMOS transistor 808 paired together. PMOS transistor 806
`has fewer folds than does NMOS transistor 808. Layout 800
`is an example of a left-justified layout. FIG. 8b shows layout
`802 including PMOS transistor 806 and NMOS transistor
`808. Layout 802 is an example of a centered layout. FIG. 8c
`shows layout 804 including transistors 806 and 808. Layout
`804 is an example of a right-justified layout. Because the
`different layouts 800, 802 and 804 represent different ori
`entations of nets and therefore different diffusion sharing
`arrangements between P/N pairs, all of the relative place
`ments represented by layouts 800, 802 and 804 should be
`evaluated for diffusion sharing with other transistors or
`pairs. The present invention considers every orientation of
`pairs with unequal numbers of folds. Because every orien
`tation of pairs with unequal numbers of folds is considered
`before chaining or placement, the present invention takes
`fullest advantage of this technique to create an optimal
`layout.
`FIG. 9 is a flowchart illustrating steps of a method of
`creating a transistor cell layout according to one embodi
`ment of the present invention. FIG. 9 will be described with
`reference to FIGS. 10a–12b, which illustrate details of
`method steps illustrated in FIG. 9. At step 902 a user enters
`a description of a circuit for which a layout is to be
`produced. A circuit description can be in the form of a
`Schematic diagram, a net list of the circuit diagram, or a
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`description of the circuit in a hardware description language.
`Typically, the circuit description exists as a file Stored in the
`memory Subsystem of a computer System implementing the
`present invention. The file could also be stored externally
`with respect to the computer System, yet accessible to the
`computer System. Entering the circuit description typically
`comprises entering a name and location of the file into the
`computer System using a keyboard or mouse So that the
`circuit description can be accessed by the present invention.
`At step 904 logical clusters of transistors are identified.
`Logical clusters are recognized by the present invention as
`closely connected transistors groups. These groups typically
`form logic gates such as NANDS, NORS, inverters, etc.
`Referring now to FIG. 10a, a schematic 1000 is shown.
`Schematic 1000 is an example of a circuit schematic which
`could be input by a user at step 902. The circuit of schematic
`100 will be used as a running example of creating a
`transistor layout according to the embodiment of FIG. 9.
`Schematic 1000 represents a circuit which functions as a
`typical D-latch. The D-latch circuit includes a DATA input,
`an active low clock input CLK BAR, a RESET input, and
`data outputs Q and Q BAR. The D-latch circuit is realized
`by using p-type and n-type transistors. The p-type transistors
`include P1, P2, P3, P4, P5, P6, P7, P8 and P9. The n-type
`transistors include transistors N1, N2, N3, N4, N5, N6, N7,
`N8 and N9.
`Transistors P7, P9, N9 and N7 form an example of a
`logical cluster. If these transistors were placed far apart from
`each other in a layout, long nets would be required to
`connect them. This would result in slower performance than
`if they were located closer together.
`Referring again to FIG. 9, at step 906 large transistors are
`folded. Large transistors are defined by the user as transis
`tors exceeding a certain height. Large transistors thus
`defined are folded at this stage as many times as necessary
`in order for individual folds to be under a maximum height
`Specified by the user. According to this embodiment, tran
`Sistors can be folded at this Stage into either an even number
`of folds or an odd number of folds.
`At step 908 P/N pairs are formed to create a set of P/N
`pairs. The set of P/N pairs is defined as all paired devices.
`At this Step, unpaired devices may exist. Unpaired devices
`are transistors for which there are no corresponding devices.
`For example, a p-type transistor for which there is no n-type
`transistor with which to pair it is an unpaired device. In the
`present embodiment, the Set of P/N pairs is formed using a
`Set of prioritized criteria. The criteria may include common
`gate Signals, least difference in the number of folds, mem
`bership in the Same cluster, and common diffusion terminals.
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`Pairing constrains the Subsequent Stages of the proceSS
`because each pair is treated as a unit for diffusion sharing, or
`chain formation, which will be described below. In addition,
`it should be noted that if transistor folding is not considered
`during pairing or before pairing, pairs with large differences
`in the number of folds of the p and n transistors can result,
`producing large, unused areas on the integrated circuit.
`FIG. 10b is a table showing the 9P/N pairs of schematic
`1000 that result from pairing step 908. The table of FIG. 10b
`lists the pairs by number from pair 1 through pair 9, as well
`as the particular p-type and n-type transistors in each pair.
`Table 10b also lists reasons for pairing particular transistors.
`FIGS. 11a and 11b show the impact of transistor folding
`on the formation of P/N pairs. Layout 1100 of FIG.11a is the
`result of a particular pairing. Layout 1100 includes two pairs
`where the pairs comprise P1 and N1 and P2 and N2
`respectively. Layout 1102 of FIG. 11b is an example of a
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`different pairing. Layout 1102 also includes two pairs of
`transistors. However, these transistor pairs include transis
`tors P1 and N2 and P2 and N1 respectively. As can be seen,
`the pairing of layout 1100 wastes area equivalent to three
`transistors. With the pairing of layout 1102 the area of three
`transistors can be Saved. Because the present invention
`considers transistor folding during pairing, unnecessarily
`wasteful pairings are avoided.
`Referring again to FIG. 9, step 910 generates all transistor
`chains for the Set of paired devices. Note that chains are
`created at this Stage using only paired devices. The present
`invention generates transistor chains from the Set of paired
`transistors by implicitly enumerating all Such chains.
`Implicit enumeration refers to intelligently avoiding the
`enumeration of any chain which would be equivalent to
`another in terms of area usage and end terminal arrange
`ment. Thus, only the chains having unique effects on area
`used or end terminal arrangement are enumerated, and
`chains that are redundant are not enumerated.
`Given a set of P/N pairs, the generation of transistor
`chains is based on pairwise diffusion Sharing in which two
`pairs can be abutted together only if the p-type and n-type
`transistors of the pairs can share their diffusions. For this
`embodiment of the present invention, pairwise abutmen