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`DECLARATION OF MARTIN L. KNOTT
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`(cid:1)
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`Dell Ex. 1011
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`Declaration of Martin L. Knott Regarding
`Authentication and Public Accessibility of Publication
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`I, Martin L. Knott, declare as follows:
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`I am a librarian and Metadata and Linked Data Strategist within the
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`University of Michigan Library’s Technical Services Department, located at 913 S.
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`University, Ann Arbor, MI 48109-1190. I hold a Master of Science in Information from
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`the University Library in August of 1992. Through the course of my employment and
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`following:
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`This Declaration relates to the dates of receipt and public availability of the
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`integrated circuits(cid:2)(cid:2): a design perspective. (2nd ed.). Upper Saddle
`River, N.J.(cid:2): Pearson Education.
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`Rabaey, J. M., Chandrakasan, A. P., & Nikolić, B. (2003). Digital
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`Standard operating procedures for materials at the University of Michigan
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`Libraries. During the early 2000s and through the present, when a journal volume or
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`other publication was or is received by the University Library, it would be checked in,
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`ActiveUS 164103427v.1
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`Declaration of Martin L. Knott Regarding
`Authentication and Public Accessibility of Publication
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`borrowing as soon after its arrival as possible. This procedure normally took a few days
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`or as long as 4 months when there were high numbers of new materials in the workflow.
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`4.(cid:1)
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`The image attached to this Declaration is a true and accurate copy of
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`Digital integrated circuits with a University Library date inscription of January 20,
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`2003 from the University of Michigan Library collection. The date inscription on the
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`page following the title page indicates that Digital integrated circuits was received by
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`Graduate Library on January 20, 2003. Digital integrated circuits was purchased for
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`several University of Michigan campus libraries, for user access.
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`5.(cid:1)
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`Based on the information in the attached image, it is clear that Digital
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`integrated circuits was received by the Art, Architecture & Engineering Library on
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`these statements were made with the knowledge that willful false statements and the like
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`so made are punishable by fine or imprisonment, or both, under Section 1001 of Title 18
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`Declaration of Martin L. Knott Regarding
`Authentication and Public Accessibility of Publication
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`Date: March 19, 2019
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`University of Michigan Library
`913 S. University
`Ann Arbor, MI 48109-1190
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`ActiveUS 164103427v.1
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`________________________________
`Martin L. Knott
`Metadata and Linked Data Strategist
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`NOTICE CONCERNING
`COPYRIGHT RESTRICTIONS
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`The material copied here may be protected by copyright
`law in the United States and/or in other jurisdictions. This
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`is provided to you for the purposes of private study,
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`Dell Ex. 1011
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`Prentice Hall Electronics and VLSI Series
`
`Charles S. Sodini, Series Editor
`
`LEE, SHUR, FIELDLY, YTTERDAL Semiconductor Devices Modeling for VLSI
`
`LEUNG VLSIfor Wireless Communications
`PLUMMER, DEAL, GRIFFIN. Silicon VLSI Technology: Fundamentals, Practice, and Modeling
`RABAEY, CHANDRAKASAN, NIKOLIC Digital Integrated Circuits: A Design Perspective, Second Edition
`
`Dell Ex. 1011
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`Page 6
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`Dell Ex. 1011
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`DIGITAL
`
`INTEGRATED
`CIRCUITS
`
`
`A DESIGN PERSPECTIVE
`
`SECOND EDITION
`
`JAN M. RABAEY
`ANANTHA CHANDRAKASAN
`BORIVOJE NIKOLIC
`
`PRENTICE HALL ELECTRONICS AND VLSI SERIES
`CHARLESG. SODINI, SERIES EDITOR
`
`
`
`Pearson Education, Inc.
`
`Upper Saddle River, New Jersey 07458
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`
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`Library of Congress Cataloging-in-Publication Data onfile.
`
`Vice President and Editorial Director, ECS: Marcia J. Horton
`Publisher: Tom Robbins
`Editorial Assistant: Eric Van Ostenbridge
`Vice President and Director of Production and Manufacturing, ESM: David W. Riccardi
`Executive Managing Editor: Vince O'Brien
`Managing Editor: David A. Gearge
`Production Editor: Daniel Sandin
`Director of Creative Services: Paul Belfanti
`Creative Director: Carole Anson
`Art and Cover Director: Jayne Conte
`Art Editor: Greg Dulles
`Manufacturing Manager: Trudy Pisciotti
`Manufacturing Buyer: Lisa McDowell
`Marketing Manager: Holly Stark
`
`About the Cover: Detail of "Wet Orange," by Joan Mitchell (American, 1925-1992). Oil on canvas, 112 x 245in.
`(284.5 X 622.3 cm). Carnegie Museum of Art, Pittsburgh, PA. Gift of Kaufmann's Department Store and the
`National Endowmentfor the Arts, 74.11. Photograph by Peter Harholdt, 1995.
`
`© 2003, 1996 by Pearson Education,Inc.
`Pearson Education, Inc.
`Upper Saddle River, NJ 07458
`
`The authorand publisherofthis book have used their best efforts in preparing this book. These efforts include the devel-
`opment, research, and testing of the theories and programs to determine their effectiveness, The author and publisher
`shall not be liable in any event for incidental and consequential damages in connection with, or arising out of, the fur-
`nishing, performance, or use of these programs.
`
`All rights reserved. No part of this book may be reproduced, in any form or by any means,
`without permission in writing from the publisher.
`
`Printed in the United States of America
`
`09 8 7654321
`
`ISBN 0-13-597444-5
`
`Pearson Education Ltd., London
`Pearson Education Australia Pty, Ltd., Sydney
`Pearson Education Singapore, Pte. Ltd.
`Pearson Education North Asia Ltd., Hong Kong
`Pearson Education Canada Inc., Toronte
`Pearson Educacién de Mexico, S.A. de C.V.
`Pearson Education—Japan, Tokyo
`Pearson Education Malaysia, Pte. Ltd.
`Pearson Education Inc., Upper Saddle River, New Jersey
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`
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`and our Parents
`
`To Kathelijn, Karthiyayani, Krithivasan,
`
`:
`
`“Qu’est-ce que l'homme dans la nature?
`Un néant a l’égard de l’infini,
`un tout al l’égard du néant,
`un milieu entre rien et tout.”
`
`“Whatis man in nature?
`Nothing in relation to the infinite,
`everything in relation to nothing,
`a mean between nothing and everything.”
`
`Blaise Pascal, Pensées, n. 4, 1670.
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` Contents
`
`Preface
`
`The Fabrics
`
`Introduction
`1.1
`A Historical Perspective
`1.2
`Issues in Digital Integrated Circuit Design
`1.3.
`Quality Metrics of a Digital Design
`1.3.1 Cost of an Integrated Circuit
`1.3.2. Functionality and Robustness
`1.3.3 Performance
`1.3.4 Power and Energy Consumption
`Summary
`To Probe Further
`Reference Books
`References
`
`1.4
`1.5
`
`2.3.
`
`The Manufacturing Process
`2.1
`Introduction
`2.2 Manufacturing CMOSIntegrated Circuits
`2.2.1
`TheSilicon Wafer
`2.2.2 Photolithography
`2.2.3 Some Recurring Process Steps
`2.2.4
`Simplified CMOS Process Flow
`Design Rules—The Contract between Designer
`and Process Engineer
`Packaging Integrated Circuits
`2.4.1
`Package Materials
`2.4.2
`Interconnect Levels
`2.4.3 Thermal Considerations in Packaging
` Perspective—Trends in Process Technology
`2.5.1
`Short-Term Developments
`‘2.5.2.
`In the Longer Term
`2.6
`Summary
`
`2.4
`
`2.5
`
`15
`16
`18
`27
`30
`31
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`31
`32
`33
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`35
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`36
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`37
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`at
`4]
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`42
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`47
`51
`52
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`53
`39
`61
`61
`63
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`Contents
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`2.7.
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`To Probe Further
`References
`
`Design Methodology Insert A IC LAYOUT
`A.1
`To Probe Further
`References
`
`Chapter 3 The Devices
`3.1
`Introduction
`3.2.
`The Diode
`3.2.1 A First Glance at the Diode—The Depletion Region
`3.2.2 Static Behavior
`3.2.3. Dynamic, or Transient, Behavior
`3.2.4 The Actual Diode—Secondary Effects
`3.2.5 The SPICE Diode Model
`The MOS(FET)Transistor
`3.3.1
`<A First Glance at the Device
`3.3.2. The MOSTransistor under Static Conditions
`3.3.3. The Actual MOS Transistor—Some Secondary Effects
`3.3.4 SPICE Models for the MOS Transistor
`A Word on Process Variations
`Perspective—Technology Scaling
`Summary
`To Probe Further
`References
`
`3.4
`3.5.
`3.6
`3.7
`
`3.3.
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`Design Methodology Insert B_ Circuit Simulation
`References
`
`Chapter4 The Wire
`ee
`4.1
`Introduction
`4.2
`A First Glance
`4.3
`Interconnect Parameters—Capacitance, Resistance,
`and Inductance
`4.3.1 Capacitance
`4.3.2 Resistance
`4.3.3
`Inductance
`Electrical Wire Models
`4.4.1 The Ideal Wire
`4.4.2 The Lumped Model
`4.4.3 The Lumped RC Model
`4.4.4 The Distributed rc Line
`4.4.5 The Transmission Line
`
`44
`ql
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`64
`64
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`67
`71
`71
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`73
`74
`74
`fp)
`77
`80
`84
`85
`87
`87
`88
`114
`117
`120
`122
`128
`129
`130
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`131
`134
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` 4.5
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`SPICE Wire Models
`4.5.1 Distributed rc Lines in SPICE
`4.5.2 Transmission Line Models in SPICE
`4.5.3
`Perspective: A Lookinto the Future
`Summary
`To Probe Further
`References
`
`4.6
`4.7.
`
`A Circuit Perspective
`
`The CMOSInverter
`
`5.1
`5.2
`5.3.
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`5.4
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`4
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`;
`,
`.
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`"
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`5.5
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`5.6
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`5.7.
`5.8
`
`Introduction
`The Static CMOSInverter—An Intuitive Perspective
`Evaluating the Robustness of the CMOSInverter:
`The Static Behavior
`5.3.1
`Switching Threshold
`5.3.2 Noise Margins
`5.3.3 Robustness Revisited
`Performance of CMOSInverter: The Dynamic Behavior
`5.4.1 Computing the Capacitances
`5.4.2 Propagation Delay: First-Order Analysis
`5.4.3 Propagation Delay from a Design Perspective
`Power, Energy, and Energy Delay
`5.5.1 Dynamic Power Consumption
`5.5.2 Static Consumption
`5.5.3 Putting [t All Together
`5.5.4 Analyzing Power Consumption Using SPICE
`Perspective: Technology Scaling andits Impact
`on the Inverter Metrics
`Summary
`To Probe Further
`References
`
`Chapter6 Designing Combinational Logic Gates in CMOS
`TG 6.1
`Introduction
`r
`6.2
`Static CMOS Design
`q
`6.2.1 Complementary CMOS
`6.2.2 Ratioed Logic
`6.2.3. Pass-Transistor Logic
`Dynamic CMOSDesign
`6.3.1 Dynamic Logic: Basic Principles
`6.3.2
`Speed and Power Dissipation of Dynamic Logic
`
`6.3.
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`xvii
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`170
`170
`170
`171
`174
`174
`174
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`177
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`179
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`180
`180
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`184
`185
`188
`19]
`193
`194
`199
`203
`e123
`214
`223
`225
`227
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`229
`232
`233
`233
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`235
`236
`236
`237
`263
`269
`284
`284
`287
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`Contents
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`6.3.3 Signal Integrity Issues in Dynamic Design
`6.3.4 Cascading Dynamic Gates
`Perspectives
`6.4.1 How to Choose a Logic Style?
`6.4.2 Designing Logic for Reduced Supply Voltages
`Summary
`To Probe Further
`References
`
`6.4
`
`6.5
`6.6
`
`Design Methodology Insert C How to Simulate Complex
`Logic Circuits
`C.1
`Representing Digital Data as a Continuous Entity
`C.2
`Representing Dataas a Discrete Entity
`C.3
`Using Higher-Level Data Models
`References
`
`290
`295
`303
`303
`303
`306
`307
`308
`
`309
`310
`310
`315
`317
`
`7.2
`
`Design Methodology Insert D Layout Techniques for Complex Gates 319
`Chapter7 Designing Sequential Logic Circuits
`325
`7.1
`Introduction
`326
`7.1.1 Timing Metrics for Sequential Circuits
`327
`7.1.2 Classification of Memory Elements
`328
`Static Latches and Registers
`330
`7.2.1 The Bistability Principle
`330
`7.2.2 Multiplexer-Based Latches
`332
`7.2.3. Master-Slave Edge-Triggered Register
`333
`7.24 Low-Voltage Static Latches
`339
`7.2.5
`Static SR Flip-Flops—Writing Data by Pure Force
`341
`Dynamic Latches and Registers
`344
`7.3.1 Dynamic Transmission-Gate Edge-triggered Registers
`344
`7.3.2
`C?7MOS—AClock-Skew Insensitive Approach
`346
`7.3.3 True Single-Phase Clocked Register (TSPCR)
`350
`Alternative Register Styles”
`354
`7.4.1 Pulse Registers
`354
`7.4.2 Sense-Amplifier-Based Registers
`356
`Pipelining: An Approach to Optimize Sequential Circuits
`358
`7.5.1 Latch- versus Register-Based Pipelines
`360
`7.5.2 NORA-CMOS—ALogicStyle for Pipelined Structures
`361
`Nonbistable Sequential Circuits
`364
`7.6.1 The Schmitt Trigger
`364
`7.6.2 Monostable Sequential Circuits
`367
`7.6.3. Astable Circuits
`368
`Perspective: Choosing a Clocking Strategy
`370
`Summary
`371
`
`7.3.
`
`7.4
`
`7.5
`
`7.6
`
`7.7
`7.8
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`.
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`Implementation Strategies for Digital ICS
`8.1
`Introduction
`8.2
`From Custom to Semicustom and Structured-Array
`Design Approaches
`Custom Circuit Design
`Cell-Based Design Methodology
`8.4.1
`Standard Cell
`8.4.2 Compiled Cells
`8.4.3. Macrocells, Megacells and Intellectual Property
`8.4.4 Semicustom Design Flow
`Array-Based Implementation Approaches
`8.5.1
`Prediffused (or Mask-Programmable) Arrays
`F
`8.5.2. Prewired Arrays
`e
` Perspective—The Implementation Platform of the Future
`|
`Summary
`4
`To Probe Further
`e
`References
`
`Design Methodology Insert E Characterizing Logic
`and Sequential Cells
`
`References
`
`435
`Design Methodology Insert F Design Synthesis
`443
`Rt
`References
`
`445
`C apter9 Coping with Interconnect
`
`
`P| 9.1—Introduction 446
`pou
`9.2
`Capacitive Parasitics
`446
`*
`9.2.1 Capacitance and Reliability—Cross Talk
`446
`9.2.2 Capacitance and Performance in CMOS
`449
`Resistive Parasitics
`460
`9.3.1 Resistance and Reliability—Ohmic Voltage Drop
`460
`9.3.2 Electromigration
`462
`9.3.3 Resistance and Performance—RC Delay
`464
`Inductive Parasitics”
`469
`9.4.1
`Inductance and Reliability— Voltage Drop
`469
`9.4.2
`Inductance and Performance—Transmission-line Effects
`475
`Advanced Interconnect Techniques
`480
`
`7.9
`
`To Probe Further
`References
`
`A System Perspective
`
`xix
`
`372
`aT
`
`375
`
`8.3
`8.4
`
`8.5
`
`8.6
`8.7
`8.8
`
`9.3
`f\
`
`9.4
`
`/
`
`9.5
`
`377
`378
`
`382
`383
`384
`385
`390
`392
`396
`399
`399
`404
`420
`423
`423
`424
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`427
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`
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`480
`486
`487
`488
`489
`489
`
`491
`492
`492
`492
`493
`493
`494
`495
`495
`502
`308
`516
`519
`519
`522
`526
`531
`534
`534.
`538
`
`9.5.1 Reduced-Swing Circuits
`9.5.2 Current-Mode Transmission Techniques
`Perspective: Networks-on-a-Chip
`Summary
`To Probe Further
`References
`
`9.6
`9.7
`9.8
`
`Chapter 10 Timing Issues in Digital Circuits
`10.1
`Introduction
`10.2 Timing Classification of Digital Systems
`10.2.1 Synchronous Interconnect
`10.2.2 Mesochronous interconnect
`10.2.3 Plesiochronous Interconnect
`10.2.4 Asynchronous Interconnect
`10.3 Synchronous Design—An In-depth Perspective
`10.3.1 Synchronous Timing Basics
`10.3.2 Sources of Skew andJitter
`10.3.3 Clock-Distribution Techniques
`10.3.4 Latch-Based Clocking”
`10.4 Self-Timed Circuit Design’
`10.4.1 Self-Timed Logic—An Asynchronous Technique
`10.4.2 Completion-Signal Generation
`10.4.3 Self-Timed Signaling
`10.4.4 Practical Examples of Self-Timed Logic
`10.5 Synchronizers and Arbiters*
`10.5.1 Synchronizers—Concept and Implementation
`10.5.2 Arbiters
`10.6 Clock Synthesis and Synchronization Using
`a Phase-Locked Loop"
`10.6.1 Basic Concept
`10.6.2 Building Blocks of a PLL
`10.7 Future Directions and Perspectives
`10.7.1 Distributed Clocking Using DLLs
`10.7.2 Optical Clock Distribution
`10.7.3 Synchronous versus Asynchronous Design
`10.8 Summary
`10.9 To Probe Further
`References
`
`Xx
`
`Contents
`
`
`
`539
`540
`|
`542
`546
`546
`548
`549
`550
`551
`551
`
`Design Methodology InsertG Design Verification
`References
`
`553 4
`SF |
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`|
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`NA
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`11.4
`
`£15
`
`11.6
`11.7
`
`Chapter 11 Designing Arithmetic Building Blocks
`’
`11.1
`Introduction
`P
`11.2
`Datapaths in Digital Processor Architectures
`The Adder
`11.3
`11.3.1 The Binary Adder: Definitions
`11.3.2 The Full Adder: Circuit Design Considerations
`11.3.3 The Binary Adder; Logic Design Considerations
`The Multiplier
`11.4.1 The Multiplier: Definitions
`11.4.2 Partial-Product Generation
`11.4.3 Partial-Product Accumulation
`11.4.4 Final Addition
`11.4.5 Multiplier Summary
`The Shifter
`11.5.1 Barrel Shifter
`11.5.2 Logarithmic Shifter
`Other Arithmetic Operators
`Powerand Speed Trade-offs in Datapath Structures”
`11.7.1 Design Time Power-Reduction Techniques
`11.7.2 Run-Time Power Management
`11.7.3 Reducing the Power in Standby (or Sleep) Mode
`11.8
`Perspective: Design as a Trade-off
`119
`Summary
`11.10 To Probe Further
`References
`
`+
`
`
`ae) iW
`
`Chapter 12 Designing Memory and Array Structures
`Introduction
`ER
`12.1.1 Memory Classification
`12.1.2 Memory Architectures and Building Blocks
`The Memory Core
`12.2.1 Read-Only Memories
`12.2.2 Nonvolatile Read-Write Memories
`12.2.3 Read-Write Memories (RAM)
`12.2.4 Contents-Addressable or Associative Memory (CAM)
`Memory Peripheral Circuitry”
`12.3.1 The Address Decoders
`12.3.2 Sense Amplifiers
`12.3.3 Voltage References
`12.3.4 Drivers/Buffers
`12.3.5 Timing and Control
`
`122
`
`123
`
`xxi
`
`559
`
`560
`560
`561
`561
`564
`
`571
`586
`586
`
`587
`589
`
`593
`594
`594
`395
`596
`596
`
`601
`611
`
`617
`618
`619
`620
`621
`
`623
`
`624
`625
`627
`634
`634
`647
`
`657
`670
`672
`672
`679
`686
`689
`
`689
`
`Dell Ex. 1011
`
`Page 16
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`Dell Ex. 1011
`Page 16
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`
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` esa| }
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`i)
`
`xxii
`
`12.4 Memory Reliability and Yield”
`12.4.1 Signal-to-Noise Ratio
`12.4.2 Memory Yield
`12.5 Power Dissipation in Memories”
`12.5.1 Sources of Power Dissipation in Memories
`12.5.2 Partitioning of the Memory
`12.5.3 Addressing the Active Power Dissipation
`12.5.4 Data-Retention Dissipation
`12.5.5 Summary
`12.6 Case Studies in Memory Design
`12.6.1 The Programmable Logic Array (PLA)
`12.6.2 A 4-Mbit SRAM
`12.6.3 A 1-Gbit NAND Flash Memory
`12.7. Perspective: Semiconductor Memory Trends and Evolutions
`12.8 Summary
`12.9 To Probe Further
`References
`Design Methodology Insert H_ Validation and Test
`721
`of Manufactured Circuits
`721
`H.1
`Introduction
`722
`H.2
`Test Procedure
`723
`H.3 Design for Testability
`723
`H.3.1
`Issues in Design for Testability
`725
`H.3.2 Ad Hoc Testing
`726
`H.3.3 Scan-Based Test
`729
`H.3.4 Boundary-Scan Design
`730
`H.3.5 Built-in Self-Test (BIST)
`
`H.4__Test-Pattern Generation 734
`H.4.1 Fault Models
`734
`H.4.2 Automatic Test-Pattern Generation (ATPG)
`736
`H.4.3 Fault Simulation
`737
`To Probe Further
`737
`References
`737
`Problem Solutions
`739
`Index
`745
`
`Contents
`
`693
`693
`698
`701
`701
`702
`702
`704
`707
`707
`707
`710
`712
`714
`716
`717
`718
`
`|
`|
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`|
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`= |
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`H.5
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`|
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`|
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`Dell Ex. 1011
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`Page 17
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`Dell Ex. 1011
`Page 17
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