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`8.2.1.3. High-Valued Polysillcon Load Resistors !or MOS SRAMs
`High-valued resistors are used as the load devices in the poly-load SRAM cell (Fig.
`8-2b). In order to minimize power consumption and yet maintain an optimum soft(cid:173)
`error rate, the load current of the cell is set to about 31 pA.15 Very high-valued load
`resistors must be used to obtain such small load currents. For example, it has been
`calculated that 164 GQ resistors must be used for 64-kbit and 256-kbit SRAMs, and 97
`GO resistors are needed for 1-Mbit and 4-Mbit SRAMs (Fig. 8-6a).15 Films made of
`materials with very high sheet resistances must be used to fabricate these load resistors
`to avoid the consumption of excessive area.
`Undoped polysilicon films exhibit high sheet-resistivity values, making them good
`candidates for fabricating such structures (Fig. 8-6b ). When undoped polysilicon films
`are implanted with arsenic in doses from -lxJ013/cm2 to lx!Q15/cm2, the sheet
`resistivity can be controlled from 104 0/sq up to about 1012 0/sq (Fig. 8-6c). Hence,
`to fabricate a high valued resistor (for example, a 97-GO resistor for a 1-Mbit SRAM
`cell), a polysilicon film with a sheet resistance of 26 GO/sq can be used. This sheet
`resistance can be obtained with an As implant dose of ~3xl01 3/cm2. The length of a
`97-GO resistor fabricated in such a 50-nm-thick, 1.2-µm-wide line of polysilicon would
`be4.0µm.
`Undoped polysilicon exhibits such high resistivity because some of the impurities in
`the films segregate to the grain boundaries and do not effectively produce free carriers.
`In addition, the grain-boundary regions trap some of the free carriers that are produced
`(see Vol. I, chap. 6).
`The I-V characteristics of the high-valued polysilicon resistors predicted by the
`trapping model of Lu et al. fit the experimental data fairly well if the resistor length is
`not 100 short.1 6 On the other hand, lateral diffusion from adjacent higher-doped regions
`in the poly can significantly alter the resistance value if such diffusion takes place over
`a large enough fraction of the resistor length. Because the potential energy barrier to
`diffusion along the grain boundaries is lower than that in the bulk (sec Vol. I, chap. 8),
`the rapid diffusion of impurities along grain boundaries can bring impurities to the
`lightly doped poly regions, even at relatively low temperatures.
`The effect just described can be important in the design of polysilicon-load SRAM
`cells. The resistors are normally formed in the second polysilicon layer, and the
`remainder of this layer is implanted with a much higher dose (so that it can serve as a
`low-resistance interconnect path). During this implant, the high-resistivity poly regions
`are covered with a mask to avoid impurity doping. The minimum size of the mask is
`limited by the effect of the lateral diffusion of impurities from the highly doped regions
`during the activation anneal of the polysilicon following ion implantation (e,g., 950°C
`for 30 min). Hence, a lower limit of about 3 µm was initially predicted for the length
`of such resistors.
`A technique for reducing the extent of the lateral diffusion by implanting the
`polysilicon with a very heavy dose of oxygen (~lxl022/cm3) has been reponect.1 7
`High-valued resistors can be fabricated with lengths as small as 0.8 µm (Fig. 8-6d). The
`oxygen apparently segregates to the grain boundaries, retarding the diffusion of the
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`Oxygen doped 1 x10:ucm 4
`
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`bJ
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`Artonh: Dou, 1cm·1 1
`al
`Fig. 8~6 (c) Sheet resistance versus arsenic dnse for ion~implantcd polysilicon rcsistors. 15
`(© 1985 IEEE). (d) Resistance versus nominal resistor length for oxygen-doped and undoped
`polysilicon resistors. Resistance is normalized to 1-µm width,17 (© 1987 IEEE).
`
`8.2.1.4 Soft Errors in SRAMs. SRAMs offer better resistance than DRAMs to
`both transient and total-dose mdiation, making them better suited for some military and
`space applications. Until recently, the soft-error rates of SRAMs (see section 8.3.4)
`were negligible compared to those of DRAMs. However, as geometries have been
`scaled down to produce circuits of greater density, alpha-particle-induced soft-error rates
`have also become a concern in SRAMs.33 Although p-well CMOS in itself raises the
`threshold against soft-error failures, the use of extra buried p-layers has also been
`explored as a way to reduce such errors by an additional three orders of magnitude. 10 In
`addition, the full-CMOS cells exhibit less susceptibility than poly-load cells to single(cid:173)
`event upsets and soft errors.
`CMOS/SOS technology provides inherently harder parts than docs bulk CMOS, and
`SRAMs have thus been built in CMOS/SOS for such applications. A report detailing
`the causes of the increase in soft-error rates in densely packed SRAM cells is given in
`reference 11. Another report on the modeling of alpha-particle sensitivities of SRAMs
`indicates that state-of-the-art CMOS SRAMs from 64 kbits to 1 Mbit can be made to
`exhibit sufficient insensitivity to alpha particlcs. 18
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`In ultra-high-speed SRAMs, the Schottky diode speeds the switching response and
`increases the soft-error immunity by sustaining most of the stored charge on the SBD
`capacitance. A large SBD capacitance is therefore needed in order for high reliability to
`be maintained. The SBD capacitance, however, is quite small per unit area (2.8
`fF/µm2). An alternative cell that incorporates a separate Ta2O5 capacitor has been
`reported.24,27 The use of this capacitor, which has a capacitance of 8.5 fF/µm 2, makes
`it possible to reduce the cell size by 30% compared to a conventional SBD cell.
`Another ECL-SRAM cell using polysilicon diodes as the load elements has been
`developed.113 The advantages of this approach include: compact cell size, very low
`standby curren~ very low parasitics, and small active junction area. Access tim,;s of 1.5
`ns for a 1-kbit SRAM have been demonstrated.
`Process innovations that have been incorporated to allow faster, higher-density
`SRAMs include the use of elcetromigration-resistant aluminum alloys (to permit higher
`current densities in metal interconnect stripes) and U-groove isolation (see chap. 2)
`which reduces the isolation width by a factor of three compared to fully recessed
`LOCOS isolation (sec Fig. 2-35a).
`Circuit techniques have also been used to enhance the performance of bipolar
`SRAMS. For example, read/write current has been concentrated in the active region of
`device operation, and the word delay has been reduced through the use of Darlington
`drivers. Table 8-2 summarizes the evolution of bipolar SRAM tcehnology.
`
`Table 8.2 Bipolar SRAM Evolution
`
`lntrod uctlon Access Load
`Date
`Size Time
`Device
`
`Process
`Enhancements
`
`Circuit
`Enhancements
`
`1975
`1978
`1982
`1986
`
`lk
`4k
`16 k
`64 k
`
`1.5 ns
`2.2 ns
`3.0 ns
`5.0 ns
`
`Non~Saturated Read/Write Current
`Resistor
`Darlington Drivers
`Schottky Diode
`pnp Transistor U~Groove Isolation
`
`Al~Cu
`
`8.2.2.1 BICMOS SRAMs. Although high-speed ECL SRAMs up to 64 khils in
`size have been fabricated, such large bipolar SRAMs have power dissipation and yield
`problems. Power dissipation increases because each cell draws a minimum standby
`current of about 2 µA to maintain sufficient noise margins and immunity from alpha
`particle soft errors. Defects in the narrow base region make it difficult for high-yielding
`circuits containing 262,144 narrow bases to be produced (i.e., each cell of a 64-kbit
`ECL SRAM designed with pnp loads contains four transistors).
`On the other hand, CMOS alone cannot be used to build such high-performance,
`higher-density SRAMs because the driving capability of CMOS is inferior to bipolar,
`and it is practically impossible to design an input and output buffer circuit in CMOS
`that has an ECL l/O capability.
`SRAMs have been developed which combine both bipolar and CMOS devices on the
`same chip. A comparison of 64-kbit SRAMs built using ECL and BiCMOS tcehno-
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`speeds than bipolar ECL at middle and higher densities (because of the severe speed,
`power, and density trade-off in bipolar ECL). In addition, BiCMOS SRAMs are
`somewhat faster than CMOS SRAMs at equivalent power and density for the same
`geometry, and TTL 1/0 BiCMOS SRAMs are a little slower than ECL 1/0 SRAMs
`because of their larger output voltage swing. Finally, BiCMOS offers a range of speed
`and power trade-offs (from very fast, low-density BiCMOS at high power, to slightly
`slower, mid-density memory circuits at moderate power).
`Recently, an 8 ns 1-Mbit BiCMOS SRAM1 14 and a 3.5 ns 16-kbit ECL BiCMOS
`SRAM115 have been reported.
`
`8.3 DYNAMIC RANDOM ACCESS MEMORIES
`(DRAMS)
`
`As noted earlier, dynamic random access memories (DRAMs) are so named because their
`cells can retain information only temporarily (on the order of milliseconds); even with
`power continuously applied. The cells must therefore be read and refreshed at periodic
`intervals. While the storage time may at first appear to be very short, it is actually
`long enough to allow for many memory operations between refresh cycles.
`Despite of this apparently complex operating mode, the advantages of cost per bit,
`device density, and flexibility of use (i.e., both read and write operations are possible)
`have made DRAMs the most widely used form of semiconductor memory to date.
`The earliest DRAMs used three-transistor cells and were fabricated using PMOS
`technology. Nevertheless, their introduction represented an immediate, dramatic decrease
`in the minimum semiconductor memory-cell size, since they could replace SRAMs
`based on a six-transistor cell. As a result, more cells per chip could be implemented.
`However, DRAM cells consisting of only one transistor and one capacitor were quickly
`implemented,28 and such cells have been used in DRAMs ever since.
`
`8.3.1 Evolution of DRAM Technology
`
`The earliest MOS combinational logic networks, referred to as static logic circuits,
`operated without any need for periodic clock signals. However, it was recognized that
`clock signals could be used to advantage in combinatorial and sequential logic circuits.
`By introducing clock signals at arbitrary circuit nodes, it was possible to achieve faster
`operation, greater circuit density, and reduced power dissipation. Such logic circuits
`became known as dynamic logic circuits.
`Data in these circuits was temporarily stored in dynamic registers (in the form of
`charge on the gate of an MOS transistor), rather than in static registers (which store data
`as the state of a flip-flop circuit). Thus, dynamic shift registers could be built with
`fewer transistors and, consequently, on much smaller areas of silicon than were needed
`for static shift registers. This allowed a dramatic increase in logic-circuit density.
`A question arose, however, as to how long the gate of a MOS transistor could store
`charge before that charge would be lost through leakage currents. H turned out that at
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`region of the capacitor. The storage capacitor consislS of a polysilicon plate over a thin
`oxide film (which is the capacitor dielectric), with the semiconductor region under the
`oxide serving as the other capacitor plate. Ann+ diffused region in the semiconductor
`substrate serves as the bit line and an aluminum stripe as the word line. As can be seen
`in the cross-section of the cell (Fig. 8-1 lb), the bit-line diffused region makes contact
`with the n+-ctiffused source region of the access transistor. A contact between the word
`line and the polysilicon gate of the access transistor is made, as also shown in this
`figure.
`One widely implemented enhancement of this basic cell design is shown in Fig.
`8-llc. In this modified cell, the floating drain region of the access transistor is
`eliminated and a second layer of polysilicon transfers the charge from the bit line to the
`storage capacitor. This not only allows the cell to be reduced in size, but also increases
`iis storage capacity.35 The disadvantage is that a double-polysilicon process must be
`used. As has often been the case in the evolution of VLSI, increased packing density
`and better performance are achieved at the price of somewhat greater process complexity.
`Figure 8-1 ld summarizes the structural innovations used as DRAMs have evolved.
`
`8.3.1.2 Operation of the One-Transistor DRAM Cell. To study the
`operation of the cell in Fig. 8-1 lc, assume that the substrate is grounded and that 5 V
`are applied to the polysilicon top plate of the storage capacitor (which we'll refer to as
`the plate electrode of the capacitor). The semiconductor region under the polysilicon
`plate serves as the other capacitor electrode, and in an NMOS cell this p-type region is
`normally inverted by the 5-V bias. As a result, a layer of electrons is formed at the
`surface of the semiconductor, and a depleted region is created below the surface. (The
`electrode on which the charge is stored will be referred to as the storage electrode.)
`To write a one into the cell, 5 V are applied to the bit line, and a 5-V pulse is
`simultaneously applied to the word line. The access transistor is turned ON by this
`pulse, since ilS VT is about I V. The source of the access transistor is biased to 5 V,
`since it is connected to the bit line. However, the electrostatic potential of the channel
`beneath both the access-transistor gate and the polysilicon plate of the storage capacitor
`is less than 5 V, because some of the applied voltage is dropped across the gate oxide.
`As a result, any electrons present in the inversion layer of the storage capacitor will
`flow to the lower potential region of the source, causing the storage electrode to become
`a depletion region that is emptied of any inversion-layer charge. When the word-line
`pulse returns to O V, an empty potential well remains under the storage gate. This
`empty well represenlS a binary one, and it is shown as the deep-depletion space-charge
`region in Fig. 8-12.
`For writing a zero, the bit-line voltage is returned to O V, and the word line is again
`pulsed to 5 V. With the access transistor turned ON, electrons from then+ source
`region (whose potential has been returned to O V) have access to the empty potential
`well (whose potential is now lower than that of the source region). Hence, the electrons
`from the source move to fill it, thus restoring the inversion layer beneath the poly
`plate. When the word-line voltage is returned to zero, the inversion-layer charge present
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`signal fed to the bit (column) and word (row) decoders. The closure of SI causes a
`"high" voltage to be applied to that particular word (row) line (in turn causing the access
`transistors controlled by this line to be turned ON).
`If it is desired to write data into the cell at that point, an appropriate voltage must
`also exist on the correct bit line. In addition, switches S3 and S4 must be set to the
`write positions. This allows the voltage at point A on the bit line, VA, to be applied
`to the source of the cell being addressed (point B). As long as Switch SI is closed and
`the access transistor is turned on, the capacitor of the cell can be charged to VA • V p
`(where Vp is the storage-electrode potentia[). When the write operation is completed,
`switches S 1 and S2 are opened, and another cell can be wrillen.
`If it is desired to read data from a particular cell, the appropriate switches S 1 and S2
`are once again closed (it is assumed that all of the cells already contain the stored
`information). Switch S4, however, is set to the read position. The storage capacitor of
`the cell being read is now connected to one input of the sense amplifier. The sense
`amplifier is a comparator circuit, with its other input being connected lo a reference
`voltage, V,cr. Therefore, if the cell-capacitor voltage is larger than V,cf, a logic 1 is
`read; if it is smaller, a logic O is read.
`,
`A logic 1 corresponds to the condition in which the storage electrode is depleted of
`its inversion layer charge. If a logic J is read immediately after the cell has been wrillcn,
`the signal will be strong. As time passes, thermal electron-hole pair generation will
`cause refilling of the empty potential well, thereby degrading the amplitude of the logic
`J signal. If too long a time elapses between the writing and reading, the inversion
`charge will be reestablished, and a logic O will be produced when the cell is read. Once
`a logic O is stored on a cell, however, it will continue to be read for as long as power
`remains applied to the capacitor plate electrode.
`This indicates that the logic J must be periodically refreshed to allow it lo be retained
`on the cell for indefinite time periods. Because it is not known what logic level is
`stored on each cell at any instant of time (especially since the cells are randomly read
`and written), it is mandatory that the entire memory be refreshed at periodic intervals
`(usually every few milliseconds). Furthermore, since reading a cell changes the charge
`on its capacitor, the cell must also be refreshed immediately following each read
`operation.
`The refresh procedure is accomplished by switching S3 to the refresh position after
`the sense amplifier output has been set by the read operation. The output voltage of the
`sense amplifier will then write the appropriate information back onto the cell capacitor.
`If it is desired to refresh the entire memory, each cell can be read and refreshed. ll is
`apparent, however, that data cannot be written while reading or refreshing is in progress.
`One sense amplifier must be available for each bit line. Note that the sense amplifier
`is an extremely sensitive comparator (basically of the cross-coupled flip-Ilop type), and
`its design is critically important to the success of DRAM manufacture. Allhough the
`details of the design task are not our subject here, some aspects of sense-amplifier
`performance should be mentioned. When a cell is read, the charge stored on the cell
`capacitor is shared with the 10 to 20 times larger capacitance of the bit line (which, as
`we saw earlier, is a long conductor line connected to the sources of all of the cells in the
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`column). After the time interval between refresh pulses has elapsed (e.g., 8 ms) the
`difference in stored voltage between a J and a O may be as small as 2 V. As a result,
`there may only be a 100-200 mV difference between the J and O signals applied to the
`sense-amplifier input.
`
`8.3.1.4 DRAM-Cell Charge Storage and Capacitance. A one must be
`clearly distinguishable from a zero when the read operation is performed. The zero is
`represented by the inversion charge present when the potential well is full. This
`quantity in an MOS capacitor, Q,, is given by
`
`( 8 - 1 )
`
`where VG' is the voltage applied to the gate, 'Pf is the difference in potential between the
`intrinsic Fermi level (EiJ and the Fermi level (Ep), and Cox is the capacitance of the
`capacitor oxide.* In order to pack a great many cells onto a DRAM chip, the cell size
`is made as small as possible. This implies that it is also desirable to make the area of
`the storage capacitor as small as possible. On the other hand, Q, of the storage
`capacitor must be large enough to send a sufficiently strong signal to the sense circuitry
`and to provide sufficient immunity from soft errors (see section 8.3.5). Novel cell
`designs have been developed in an attempt to satisfy these apparently contradictory
`requirements (such designs will be discussed later).
`
`EXAMPLE 8·1: Calculate the charge stored in the inversion layer when a zero is
`stored (beth in units of coulombs, and in terms of the number of electrons present)
`when 5 V are applied to an MOS capacitor whose dimensions are 4 x 4 µm, and
`which has an SiOz dielectric that is 15 nm thick. Also, find its capacitance, C,.
`
`SOLUTION: Q, (0) ~ Va• c, = (Ex A x Vo·) I lox
`
`= (3.9 x 8.85xl0·14 F/cm x l6x10-8 cm2 x 5 V) /l.5xJ0-6 cm
`= 18.6 x 10-14 C = 186 fC, or since q = 1.6 x 10-19 C/electron
`
`Q, = 1.15 x 106 electrons; and
`
`C5 = Q5 /VA = 37 fF.
`
`The above shows that the most important parameters involved in increasing the charge
`stored on the capacitor are the dielectric constant and thickness of the insulator, and the
`area of the capacitor.
`The capacitance of the DRAM cell is also important. As described earlier, when the
`
`* The approximation used in Eq. 8~ 1 is valid when VG' > 2<pf, which is the case for VG' :::: 5V
`and (flf m 0.4 V.
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`contents of the cell are sensed, the charge stored on it is "dumped" into the bit line
`connected to the sense amplifier. Because lhc bit-line capacitance (Cg) is typically 7 to
`15 times larger than the cell capacitance, lhe capacitively-divided voltage difference
`applied to lhe sense amplifier (Li. V 5a) is substantially smaller than !hat existing in lhe
`cell alone. /:,. V sa is given approximately by
`
`( 8 · 2)
`
`The minimum detectable voltage difference !hat the sense amplifiers of 1-Mbit DRAMs
`can detect (i.e., their sensitivity) is in the neighborhood of 150-200 mV. (Note that
`this sensitivity must be maintained under worst-case operating conditions of voltage,
`temperature, and noise, as well as worst-case variations of processing conditions.) It is
`predicted that lhe sensitivity of sense amplifiers will have to be significantly increased
`in order for higher-density DRAMs to be fabricated.
`
`8.3.1.5 High-Capacity (Hl·C) DRAM Cells. Another technique for
`increasing the cell's charge-storage capacity wilhout increasing its size was suggested
`independently by Sodini and Kamins,37 and Tasch, ct al. 106 This novel technique
`involves multiple ion implantations to increase the substrate doping in lhe local
`vicinity of the storage node.
`A deep implantation of p-type impurities (boron) is first performed under lhe storage(cid:173)
`plate area. This increases lhe substrate doping, which in turn increases the depletion(cid:173)
`region capacitance of lhe storage capacitor. However, !his single implant alone does not
`increase the charge-storage capacity of the cell, since lhe extra p-doping also reduces lhe
`difference in the surface potential between an empty and a full potential well.
`To restore surface potential to its previous value it (without compromising the
`increased capacitance), a very shallow layer of n-type dopant (arsenic) is implanted under
`lhe storage plate area (Fig. 8-14). The implanted donor atoms, which are very close to
`lhe Si/SiO2 interface, behave like a fixed positive oxide charge (and the presence of such
`oxide charge acts to increase lhe surface potential in NMOS structures). By increasing
`lhc depletion-region capacitance without simultaneously increasing lhe surface potential,
`the charge-storage capacity of lhese so-called high capacity cells (or Hi-C cells) is
`enhanced by about 50 percent compared to conventional cells.35,104 Although, this
`technique increases lhe storage capacities of planar capacitor structures in lhese types of
`one-transistor cells, the cell size !hat must be used in order for adequate charge-storage
`capacity to be obtained eventually becomes too large for this type of cell to be used in
`advanced DRAMs (i.e., > I Mbit). New cell structures have thus been developed for
`larger DRAMs.
`
`8.3.1.6 CMOS DRAMS. With the introduction of the 256-kbit DRAM, the
`design of DRAM circuits began to change from NMOS to a mixed NMOS/CMOS
`technology. The cells of lhe mixed-technology memory array are all built in a common
`well of a CMOS wafer. The access transistor and storage capacitor of each cell are
`usually still fabricated using NMOS technology, while lhe peripheral circuits are
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`DRAM generation must be able to use the same size package as that used by the
`previous generation. This explains why the 300-mil package housed DRAMs for five
`generations. To squeeze enough cells onto a chip to allow this package to be retained
`implies that the cell size of the 1-Mbit DRAM cannot exceed 20 µm 2.
`For future DRAM generations, however, increased memory size will be achieved by
`both increasing the chip si1,e and shrinking the cell size. Since the chip size is predicted
`to increase by a factor of 1.5 from generation to generation, the cell area will therefore
`need to shrink to 40% of the size of the previous generation (which can be done by
`shrinking the minimum line width to 70% of that used previously). For 4-Mbit
`DRAMs, the cell si1,e must therefore be no larger than 9 µm2; for 16-Mbit DRAMs, no
`larger than 4 µm 2, and so on. To meet the signal-to-noise ratio constraints and the soft(cid:173)
`error rate requirements, a minimum of -200 fC of charge (-106 electrons) will have to
`be stored. For the fabrication process to be economically feasible, as few steps as
`possible should beyond those required to fabricate the transistors and interconnects
`should be added.
`Recovery of the equipment and development costs of the 256-kbit, 1-Mbit, and
`4-Mbit DRAMs has become the major factor dictating the three-year product(cid:173)
`introduction and delivery cycle so that a profit can be generated from each DRAM
`generation. In a typical three-year cycle, fewer than I million chips would be shipped
`for sampling during the introduction year. In the first production year, 5 million chips
`would be shipped; production would increase to 50 million chips in the second year, and
`500 million in the third. (Note that in the second year the market would be mainframe
`computers, and in the third year it would be personal computers.)3 The three-year
`model predicts that 16-Mbit DRAMs will be introduced in 1992, and 64-Mbit DRAMs
`in 1995.
`It was noted in section 8.3.1.3 that the cell's storage capacity could be increased by
`making the capacitor dielectric thinner, by using an insulator with a larger dielectric
`constant, or by increasing the area of the capacitor. The first two options are not
`currently viable, since capacitor dielectrics thinner than those now being used in DRAM
`cells (10 nm) will suffer leakage due to Fowler-Nordheim tunneling, and dielectrics with
`significantly larger dielectric constants than of SiOz have not yet been accepted for
`DRAM-cell application (although research work is under way to develop such highcr(cid:173)
`dielcctric-constant materials).39 One recent report described a plasma-CVD process for
`depositing high-quality Ta2O5 films. 119 (Ta2O5 exhibits a much higher dielectric
`constant than SiO2 (22 vs. 3.9], but normally also suffers from a much higher leakage
`current.) However, by reacting TaCl5 with NzO under optimized plasma-CVD
`conditions, Ta2O5 films with a thickness that yielded capacitances equivalent to those
`of a 30-A Si(½ film, demonstrated very low leakage currents for up to 10-year operation
`at 3.3 V.
`It should also be noted that since the 256-kbit DRAM generation bilayer films
`(consisting of both silicon nitride and SiO2), have been used as the capacitor dielectric
`to increase cell capacitance (Fig. 8-15a). The higher dielectric constant of Si3N4 (twice
`as large as that of SiO2) was responsible for this increase.
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`SILICON PROCESSING FOR THE VLSI ERA - VOLUME II
`
`The planar capacitor structure used in the one-transistor DRAM cell described in
`section 8.3.1.1 was predicted to be usable up to the 256-kbit DRAM generation. In
`this generation, the capacitor consumes 30 to 40% of the cell area. It was generally
`agreed that beyond this, a three-dimensional capacitor structure would be needed in order
`for sufficient charge storage to be obtained. It turned out, however, that virtually all of
`the DRAM manufacturers elected to squeeze everything they could from the planar
`capacitor, and continued to use it to manufacture 1-Mbit DRAMs. This decision was
`due largely to the difficulty in achieving a reliable capacitor dielectric in a trench cell at
`the time 1-Mbil DRAMs were introduced. The use of both larger chip sizes and the
`half-V cc plate-electrode voltage technique permilled the planar capacitor lo perform
`adequately for 1-Mbit DRAMs. Reference 42 presents the details of a 1-Mbit DRAM
`technology using a 38-fF planar-capacitor structure in which the cell size is 37 µm2.
`As DRAM size increases, process complexity is expected to increase markedly as
`well. For example, a 1-Mbit DRAMs is reported to require -18 masks and 350
`processing steps, all of which could be successfully carried out in a Class 10 cleanroom
`(Fig. 8-15c). In comparison, the 4-Mbit DRAM is expected to need 20-25 masks and
`in excess of 450 processing steps, and will thus require a Class I cleanroom processing
`facility _43,44 A detailed report on the technology issues that will need to be addressed
`in the design and fabrication of 64- and 256-Mbit DRAMs has recently been
`published.105
`In 1989 1-Mbit CMOS DRAMs with access times ranging from 6-100 ns were
`being commercially offered. (The fabrication of a high speed 22-ns CMOS DRAM was
`announced in late 1989, but it wa~ not being offered for sale.) 110 At that time, 4-Mbit
`DRAMs with access times of 80-120 ns were also being offered, and 16-Mbit CMOS
`DRAMs with access times as small as 45 ns were being reportcd.111 Finally, 1-Mbit
`BiCMOS DRAMs with access times of 30 ns were being introduced.112
`
`8.3.3 Trench-Capacitor DRAM Cells
`
`8.3.3.1 Trench Capacitor Processing for DRAMS. Trench-capacitor
`structures have been developed as a way to to achieve DRAM cells with larger
`capacitance values without increasing the area these cells occupy on the chip surface.
`(For example, the silicon-area reduction of a trench capacitor compared to a planar
`capacitor for the same specific capacitance is a factor of 18 or more. Specifically, a 4.0,.
`µm-dccp trench capacitor with surface dimensions of 0.87 x 2.4 µm will occupy less
`than 3 µm2 of chip area but will have a capacitance of 40 tF.)66 Many of the
`processing details involved in trench- capacitor fabrication are the same as those
`described in chapter 2, section 2.6.3, which deals with the process technology of trench(cid:173)
`isolation structures. In this section we discuss those issues that are unique to the
`fabrication of trench capacitors used in DRAM cells.
`There arc several differences between the trench structures used for isolation and those
`used as DRAM capacitors. In the former, the dielectric film on the trench walls can be
`relatively thick, and the trench can be refilled with polysilieon or CVD SiO2. In the
`la11er, the insulator formed on the trench walls serves as the capacitor dielectric, and it
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`601
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`must therefore be as thin as possible. Since the material that refills the trench serves as
`one plate of the capacitor, it must consist of highly doped polysilicon. Furthermore, in
`order for increased capacitance to be obtained through increases in trench depth (while all
`other parameters remain constant), the trench walls must be highly vertical. To allow
`for reliable refilling of the lrenches, however, some lrench sidewall slope must be
`allowed, and a compromise process that produces a nominal sidewall slope of 87° has
`been suggestect.46 Finally, to obtain such slrUctures as Hi-C capacitors, the trench walls
`may need to be selectively doped.
`Several techniques have been developed for achieving a dielec1ric capacitor film that
`is thin enough to provide both high capacitance and high reliability (that is, the
`dieleclric must be able to provide the