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`THE SUBMICRON MOSFET
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`255
`
`We first note that the factors resulting from both mobility degradation due to
`transverse fields and velocity saturation effects are outside of the integral in the
`equations used to calculate Io (see Eqs. 4-16 and 4-19). Hence, they merely serve as
`multiplicative factors if incorporated into any of the long-channel de models described in
`chap. 4. This means that any one of the long-channel models could be used to
`demonstrate the impact of these mobility effects the I0 -V os characteristics. Here, for
`mathematical simplicity, we elect to use the square-law model of section 4.5.5 for this
`purpose. To complete the de short-channel MOSFET model, however, we will later still
`need to add some discussion of the short-channel effects that occur when the MOSFET
`is operated in saturation (i.e., the effects of channel-length modulation).
`
`5.4.2.1 DC Circuit Model of the Short-Channel MOSFET in the
`Linear Regime. As noted above, all of the long-channel MOSFET de model
`equations can be modified in the same manner to take into account both effects described
`above. For simplicity, the square-law long-channel model is chosen to be modified. In
`the linear-region, the modified (i.e., short-channel) version of de I 0-V os equation of the
`square-law model (Eq. 4-68) is
`
`Io =
`
`(5 - 34)
`
`Taking the ratio of the two currents given by Eqs. 5-22 and 4-68, we get
`
`(5 - 35)
`
`I0 (5-34 )/10 ( 4-68) = ( µeff I µn ) [ 1/ ( I + (Vos /EsatL)}]
`Note that since E,at and L appear as a product term in both Eqs. 5-22 and 5-23, a
`MOSFET is "long-channel-like" if either Esat or Lis large. Therefore, a MOSFET
`with a thinner gate oxide is more 11long-channel-like" because the thinner oxide will
`produce a larger transverse field, making the carrier mobility lower so that Esat is high.
`The saturation drain voltage Vossat can next be calculated by equating the current at
`the drain to the current given by Eq. 5-34 when Vos= Vossat· The current at the drain
`is given by the product of the carrier density and the drift velocity. The charge density
`at the drain, assuming that the GCA is still valid, is ZQ1 = C0 x(Vas - VT- Vossatl and
`the drift velocity is v,at· Therefore the current is
`
`Io = Z v,at Cox [Vas - VT - Vossatl
`
`z
`L µeff Cox
`
`[Vas - VT - (VoSsati2)] VoSsai [
`
`l
`l + (Vos'Esat L)
`
`]
`
`After some algebra, an expression for V ossat is obtained
`
`(5 - 36a)
`
`(5 - 36b)
`
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`THE SUBMICRON MOSFET
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`K of the thicker oxide device saturates at longer channel lengths. As a result, decreasing
`the channel length of a thick oxide MOSFET cannot significantly improve the current
`drive. On the other hand, as L becomes very short ( e.g., of the order of 0.25 µm), K
`approaches unity independent of tax• Thus, losat becomes proportional to Cox· Since,
`in MOSFETs with very short channels, losat becomes independent of channel length,
`the chief means of increasing losat will be to make t0 x as thin as possible (i.e., the
`device driving current will increase linearly with C0 x). Data and numerical simulation
`results support this argument.
`· As a last comment, note that because the value of Vsat for electrons and holes is
`comparable, n-channel and p-channel MOSFETs tend to perform similarly under
`velocity saturation, other things being equal. This is not the case under normal
`operation. That is, because !0 is proportional to µ 0 in normal operation, and in this
`case the value of µ 0 for holes in p-channel devices is one-half to one-fourth the
`corresponding value of~ for n-channel devices.
`
`5.4.2.2 Effects of Scaling on Ymsat• From Eq. 5-39 the maximum available
`value of gmsat for a given t0 x is given by
`gmsat = Z Vsat Cox
`This is the ultimate relationship for very-short-channel MOSFETs. However, the gm,at
`of a device with practical geometries with finite channel length is always lower than
`this maximum. In general,
`
`(5 - 42)
`
`gmsat = Kgm Z Vsat Cox,
`
`where Kgm<I
`
`(5 - 43)
`
`Compared to Eq. 5-39, Kgm can be written as
`
`Kgm = [l - (ilVossat I ilVos )]
`
`(5 - 44)
`
`It is observed that 8msat of a short-channel device often peaks at some moderate gate
`bias, beyond which it appears to either remain flat or sometimes decrease slightly, as
`shown in Fig. 5-38. This is a consequence of the term ilVossatlilV 0 8 in Eq. 5-44,
`which becomes almost constant beyond a gate bias roughly equal to tsatL.
`
`5.4.2.3 Comparing the Values of lo Calculated with the Long• and
`Short-Channel MOSFET Models as a Function of Channel
`Length. The values of losat as the channel length is reduced from 5 µm to 0.3 µm as
`calculated both by the charge-control de circuit model of the long-channel MOSFET
`(Eq. 4-68), and the short channel de circuit model (Eq. 5-38, whose basis is also the
`charge-control model) are given in Table 5-3. We observe that Eq. 4-68 predicts larger
`values of losat than those calculated with Eq. 5-38 (and these in turn are much closer to
`the measured values). This reiterates the importance of choosing the correct device
`model when performing technology scaling studies.
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`274 SILICON PROCESSING FOR THE VLSI ERA - VOLUME III
`
`subthreshold parameters rJo, TJs, and TJo are used to model the subthreshold slope
`coefficient 11, as:59
`
`rJ = TJo + TJs Vas + TJo Vos
`
`(5 - 82)
`
`The subthreshold swing St is expressed as (Eq. 4-91)
`
`St = (2.3kT/q) rJ = (2.3kT/q) (I + CctiCoxl
`
`(5 - 83)
`
`where rJ is the subthreshold slope coefficient calculated from Eq. 3-82. As discussed in
`chap. 4 and earlier in this chapter, the subthreshold swing is a function of both substrate
`and drain biases, and this bias dependence is modeled in BSIM by the linear relation
`given by Eq. 5-82.
`
`5.6 MOSFET SCALING
`
`A roadmap of the scaling of MOSFET devices was proposed by Hu in 1993.24 He
`assumed that a new generation of technology will continue to be developed every three
`years, with perhaps a slow-down to four years beyond the 0.35 µm generation. His
`proposal for MOSFET scaling is outlined as follows, with the result summarized in
`Table 5-4.
`
`1. The IC industry/market will agree on the next power-supply voltage standard
`V cc several years in advance of introducing a technology/product using that
`voltage.
`
`2. For a given V cc, the thinnest gate oxide (i.e., from manufacturability,
`reliability and GIDL considerations) will be used to get maximum 10 .
`
`3. Junction depths will be scaled aggressively to keep the short-channel effects
`(i.e., subthreshold leakage current) within a desired limit.
`
`4. VT of general purpose technology will remain basically unchanged. A
`significant reduction in VT is unacceptable for channel sub threshold leakage.
`
`5. The well doping concentration or punchthrough implant dose will be
`increased, and the gate length may be chosen to be larger than the minimum
`feature size in order to achieve acceptable leakage and standby current.
`
`6. Drain engineered structures will be used as necessary to meet the constraints
`of hot-carrier reliability, breakdown voltage, and GIDL.
`
`5.6.1 Design of Submicron MOSFETs:
`Scaling Guidelines
`
`The fundamental issue of downsizing MOSFETs is to preserve long-channel
`characteristics after miniaturization. Several approaches have been proposed as roadmaps
`for designing submicron MOSFETs (L<I µm) so that they exhibit such behavior.
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`THE SUBMICRON MOSFET
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`279
`
`Finally, Eq. 5-84 does not take into account the lateral ballooning of the drain
`depletion region in the lightly doped substrate beneath the source and drain regions.
`That is, this effect may allow bulk (subsurface) punchthrough to occur between drain
`and source. To prevent such subsurface punchthrough the substrate doping cannot be
`made as low as one would like in an attempt to reduce junction capacitance and
`threshold variation under source-to-substrate bias. A rough guideline for selecting the
`minimum value of substrate doping to avoid subsurface punchthrough has been
`suggested by Klaassen64 to be
`
`(5 - 87)
`
`where NsuB is the substrate doping and Nch is the doping in the region between the
`source and drain. Equation 5-87 sets a lower bound on the junction-to-substrate
`capacitance.
`
`5.6.1.3 Off-Current Scaling Approach. Another scaling approach
`employing a more flexible criterion for acceptable "off'-state behavior (but which is
`also somewhat more complex than the previous subthreshold approach), has been
`recently proposed.66 We will provide a brief outline of this method in this section. The
`crux of the procedure involves finding a channel doping profile which yields an
`acceptable combination of off-current l0 ff (10 when Vas= 0V) and VT in a device with as
`small an L as possible. The following three parameters are varied to arrive at the
`appropriate channel doping profile: the exposed dose D1 and centroid Xe of the VT
`implant, and the substrate doping Nsus- The profile is initially determined assuming
`that the device exhibits long-channel behavior (i.e., no significant punchthrough should
`be observed in the subthreshold operating region). However, the acceptable value of
`"off'-current in the long-channel device {10 ff,Ic) is deliberately picked to be smaller than
`loff in the short-channel device being designed - in anticipation of the increase in loff
`due to surface-DIEL in the shrunken device. The estimate of the increase in loff,lc due
`to surface-DIBL depends on the DIBL model chosen by the designer. To ensure that the
`subthreshold punchthrough current remains insignificant at maximum Vos, a minimum
`Nsua is identified. Finally, in the process of selecting appropriate values of D1 and Xe,
`the criterion that the channel depletion-region width d should be a minimum is applied
`(to keep LiVTSc as small as possible when Lis shrunk, as suggested by either Eq. 5-2 or
`barrier-lowering analysis).
`In the report that describes this scaling strategy, the example to which it is applied is
`a symmetrical CMOS process (i.e., in which NMOSFETs are built with n+-poly gates
`and PMOSFETs with p+ poly gates), a technological approach that is gaining more
`popularity as Lis decreased to 0.5 µm or smaller. Let us now also consider this scaling
`strategy as applied to a symmetrical CMOS process in more detail.
`First, the approach assumes that the following parameters are set by system and
`processing constraints: V 0 0 ; the type of gate material (e.g., heavily doped poly); and
`minimum values of lox and rj. The minimum manufacturable L is also limited by the
`lithographic process. However, loff,VT, and the actual value of Lare left as parameters
`that can be traded off later, based on the specific circuit or system application
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`280 SILICON PROCESSING FOR THE VLSI ERA - VOLUME III
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`requirements. The tradeoffs between VT and long-channel Ioff (Ioff,Ic) values are carried
`out with the aid of families of curves that relate VT and Ioff,lc for a fixed lox (with
`NsuB as a parameter). Figure 5-45 is an example of one such family of curves in
`which lox = !ODA. Notice that the x-axis is expressed in N0 ff 1c!Nmo instead of Ioff' 1
`,C•
`a
`,
`However, since Ioff,lc is directly proportional to Noff,lc (the latter being defined as the
`free-carrier density in the channel per unit area - e.g., per cm·2 - when V GS = 0V)
`according to
`
`Ioff,Ic = µ (ZIL)(kT/q)qNoff,lc
`
`(5 - 88)
`
`Ioff,lc is implicitly expressed in these curves. In Eq. 5-88, Zand Lare the device width
`and length, respectively. In addition, Nmg is the free-carrier concentration per unit area
`in the channel at midgap,* and this value can be found from
`
`Nmg (cm·2) = "i (Ksi IKox)(2kT/Eg) lox
`
`(5 - 89)
`
`Nmg is therefore the free-carrier density in the channel at the point when the surface is
`undergoing its field-induced reversal of polarity (e.g., from p-type ton-type). Thus,
`Nmg represents the smallest free-carrier concentration in the channel in weak inversion.
`As is also indicated by Eq. 5-89, Nmg is independent of NsuB- In an Si-Si02 MOS
`device at 300K, Eq. 5-89 can be written to explicitly express the relation between Nmg
`and lox as
`
`Nmg (@ 300K, in cm-2) = !010(cm·3)(1 l.8/3.9) 22.4 t0 x(cm) = l.33x!09 t0 x(cm).
`
`Thus, for a MOSFET with lox= 15 nm = l.5xI0·6 cm
`
`Nmg - 2x!03 cm·2.
`
`Thus, if loff,lc is given, and it is desired to relate this value to a point on a curve in
`which one axis is expressed in terms of N0 rr,1c!Nmg (such as Fig. 5-45), it can be done
`as follows:
`
`Example 5-1: If a maximum off-current loff,lc at 300K of 10 pA is required in
`an NMOSFET with L = 3 µm, Z = 6 µm, lox= 15 nm, and µn = 400 cm2/Vsec,
`find the value of N0 rr,1c!Nmg that corresponds to this loff,lc value.
`
`Solution: Since Noff,lc = 10 rr,1cl[µ,, (ZIL) (kT/q)q]
`
`= Ix!0- 11 A I [400 cm2/Vsec (6/3) (0.025V) I.6xI0· 19C]
`
`= 3.Ix!07 carriers/cm2
`* Midgap is the state of a MOSFET in which band bending is causing EF at the Si surface to
`co-incide with the energy level at the middle of the bandgap (which is also where Ej resides).
`Also at midgap, 'Psurflcp, = ln(Nsus/nj) as shown in Fig. 5-46. In the special case of midgap
`occurring at V GS =0V, Nmg is the free-carrier concentration (cm-2) in the channel for that
`condition.
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`THE SUBMICRON MOSFET
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`. 307
`
`deposited on the gate oxide prior to the implant (in fact, immediately after the
`oxide is grown),77
`
`2. After the implant has been performed, the remainder of the polysilicon film
`is deposited. In order to avoid the 900°C thermal cycle that would have to be
`used if the poly were doped following deposition, this polysilicon is doped in
`situ at ~600°C with phosphorus.
`
`3. A BPSG glass layer is used as the dielectric between the gate and the first
`level of metal. A significantly lower temperature can be used to flow BPSG
`than PSG (e.g., 900°C versus 1000°C). A lower temperature cycle can thus be
`used to smooth the surface topography (flow step) and gently taper the contact
`holes after etch (reflow step).
`
`to Suppress
`5.8.3.2 Shallow p+ Source/Drain Junctions
`Punchthrough in PMOSFETs. As noted in our discussion of MOSFET
`scaling in section 5.6.1.2, reducing the source/drain junction depths also decreases the
`susceptibility to short-channel effects. By reducing the vertical depth of the source/drain
`junctions the lateral spread of the dopants in these regions beneath the gate also
`becomes smaller. Hence, a longer effective channel length is possible for a fixed drawn
`gate length. In addition, the lateral spread of source and drain depletion regions below
`the surface layer makes a MOSFET more prone to punchthrough. Consequently,
`shallow source and drains effectively suppress subsurface punchthrough paths.
`In NMOSFETs, it is easier to fabricate shallow n+ source/drain regions (i.e.,
`~0.2 µm in depth) because dopants with heavy ionic masses (usually arsenic) are
`implanted to form these regions. They yield implant profiles with small projected
`ranges and little channeling. Furthermore arsenic has a low diffusivity, so that little
`redistribution occurs during postimplant annealing. In PMOSFETs, however, the only
`practical p-type dopant for forming the p+ regions is boron, and junctions formed with
`boron are much deeper than those formed with arsenic for several reasons. First, the
`projected range of the low-mass boron is relatively larger, even at low implantation
`energies. Ion channeling also causes the implanted boron profile to have a long tail,
`even if the target wafers are tilted to minimize this effect. Thus, the minimum junction
`depth which results when boron is implanted into a lightly doped n-type crystalline
`silicon wafer is about 0.35 µm.
`The high diffusivity of boron compounds the problem. That is, in CMOS processes
`both then- and p-implants that form the NMOS and PMOS source and drain regions,
`respectively, must be annealed. The anneal used for the arsenic implant will cause
`significant (>0.1 µm) redistribution of the boron implant. In CMOS technologies with
`channel lengths of 2 µm or longer, this issue does not arise because the boron can be
`implanted after the arsenic implantation and anneal steps (i.e., allowing the boron to be
`annealed only for the minimum time and temperature needed for full activation). Thus,
`boron redistribution after implantation can be minimized. However, in submicron
`CMOS processes it is generally not possible to perform the boron implant after then+
`arsenic implant. This is because submicron NMOS devices usually use LDD structures,
`
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`THE SUBMICRON MOSFET
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`315
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`THE SUBMICRON MOSFET
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`318 SILICON PROCESSING FOR THE VLSI ERA - VOLUME III
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`94. N.D. Arora and M.S. Sharma, "Modeling the Anomalous Threshold Voltage Be!1avior of
`Submicrometer MOSFETs," IEEE Electron Dev. Lett., EDL-13, p. 92, February 1992.
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`Electron Dev. Lett., EDL-14, p. 575, December 1993.
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`tribution Induced by Arsenic Source and Drain Implant," IEDM Tech. Dig. 1992, p. 849.
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`THE SUBMICRON MOSFET
`
`319
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`IGFETs," IEEE Trans. Electron Dev., ED-25, p. 435 (1978).
`
`PROBLEMS
`
`1, Calculate the threshold voltage (a) in I Q-cm p-type silicon and (b) in I Q-cm p-type
`-~mcon. The MOS devices for each case have: (i) 11+-polysilicon gate; (ii) t0x = 100 nm; and
`(iii) the oxide is free of charge except for a surface density of Qf = 5xl 010 cm·2.
`--,2. For exercise 1, what are the threshold voltages if p+ polysilicon is used for both the n-
`and p-channel devices.
`-
`:3. Describe punchthrough current and subthreshold current and explain the difference
`, between them.
`4, Ann-channel MOSFET has a tox of 20 nm, an Leff= I µm, rj = 0.2 µm, and VT= 0.6V. If
`thC device is biased at Vas:= 3V and Vos= 5V, calculate the saturation voltage Yossat and the
`1Tlaximum electric field.
`i:;'5. Use one-dimensional junction theory to estimate the punchthrough voltage of a MOSFET
`with a channel length of 1 µm. Assume a substrate doping of 3x1016/cm3, a substrate bias of
`"ov, and a uniformly doped substrate (no Vradjust implant).
`6. Using Eq. 5-97, calculate the buried-channel St value for X1 = 500A, t0 x:;:; 250A, x2<<x3:;:;
`3000A and compare it with the St value calculated for a surface-channel MOSFET with the
`same t0 x and a channel depletion width of d :;:; x3.
`·"7, How does a MOSFET's threshold change when constant field scaling rules are applied?
`Does it scale proportionately?
`8, Consider a long-channel MOSFET with l = 3 µm, Z = 21 µm, NA= 5x!015 cm·3, Cox=
`1.5x to·7 F/cm2, and VT= 1.5V. Calculate Vossat for the case when Vas = 4V. If a constant
`scaling factor is used to reduce the channel length to l µm, find the following scaled-down
`parameters: Z, Cox, and losat·
`9. A MOSFET with gate oxide thickness of 20 nm is to be fabricated on a p-type substrate of
`doping NA= 1016 cm·3. The source/drain regions have a depth of 0.2 µm and No:;:; 10 19 cm·3.
`The device is to be operated with Yes= 0V, but Vos could be as large as 3V. From Eq. 5-84 es(cid:173)
`the minimum channel length this MOSFET can have while still exhibiting electrically
`long-channel behavior. (The gate length is the channel length plus twice the junction depth.)
`A smaller value of minimum channel length could be obtained if a larger NA was used. Suggest
`some undesirable side effects that such a choice could produce.
`10. Qualitatively describe the differences between a surface-channel and a buried-channel
`MOSFET.
`11. We have stated in this chapter that the saturation of electron velocity can limit the drain
`current in a MOSFET with a channel length of 1 µm or less operating from a 5-V supply.
`Examine this effect by using SPICE to generate the 10 -Vos characteristic of an NMOSFET
`with L = 1 µrn formed on a substrate of doping NA= 1016 cm·3 with a 50 nm thick gate oxide.
`Set V GS = 5V and sweep Vos from 0 to 5V using the Level 2 model. First run a simulation in
`which VMAX is not specified, and then repeat the simulation with VMAX = 8x106 cm sec· 1
`,
`which corresponds roughly to the scatter-limited velocity of electrons in a MOSFET channel.
`
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`CHAPTER 8
`
`WELL FORMATION IN CMOS
`
`Both n- and p-channel transistors must be fabricated on the same wafer in CMOS
`technologies. Obviously, only one type of device can be fabricated on a given starting
`substrate. To accommodate the device type that cannot be built on this substrate,
`regions of a doping type opposite to that present in the starting material must be
`formed. These regions are called wells (or sometimes tubs) and are usually (but not
`always) the first features to be defined on a starting wafer. The well-formation process
`starts with a uniform, lightly doped p- or ,Hype substrate. Excess dopants of the
`opposite type are then selectively implanted or diffused to attain the proper well depth
`and doping profile in the well regions. The doping type in the wells becomes the
`identifying characteristic of the CMOS technology (e.g., p-well or n-well CMOS).
`Conventional well-implant doses range from 2x!012-8x!0 12/cm 2 at energies from
`100-200 keV. The term "conventional" in this sense refers to wells formed by low(cid:173)
`energy (<200 keV) ion implantation and a thermal drive-in. Alternative well-formation
`techniques that do not require a drive-in will also be discussed separately. Epitaxial
`n-on-n+ or p-on-p+ starting substrates have also come into widespread use, since they
`help reduce the susceptibility of CMOS circuits to latchup.
`As well as being of the correct doping type, the well and substrate must be
`electrically isolated from each other under every operating condition. As noted in chap.
`6, to ensure that pn junctions are not forward-biased during circuit operation, if a p-type
`substrate is used as the starting material of an IC, the substrate must be connected to the
`most negative circuit voltage. If an n-type substrate is used, it must be connected to the
`most positive circuit voltage. When wells are present, however, the well regions must
`also be connected to the appropriate circuit voltages to prevent forward-biasing of the
`junctions within the well (and between the well and substrate). Because the wells are
`totally junction-isolated from the rest of the wafer, it is especially important that
`provisions for well connections be made at the top surface of the wafer. That is, in non(cid:173)
`well technologies, it may still be possible to contact the substrate from the backside of
`the wafer even if no provision is made for a substrate contact from the top surface.
`Obviously, such backside connections cannot be established to the well regions.
`The dopant concentration near the surface of the well is one of the factors that impact
`VT, carrier mobility, source/drain capacitance, and field isolation. The well concentration
`deeper beneath the surface affects other characteristics of MOSFET behavior such as
`latch-up and vertical punchthrough (i.e., between drain and well-substrate junctions).*
`* To ensure that vertical punchthrough will not occur, the depletion regions of the drain/well
`and well/substrate junctions must be prevented from merging. That is, the depth of the
`we