United States Patent (19)
`Kawagoe et al.
`
`US006043114A
`Patent Number:
`11
`(45) Date of Patent:
`
`6,043,114
`Mar. 28, 2000
`
`54 PROCESS FOR MANUFACTURING A
`SEMICONDUCTOR WAFER, A
`SEMICONDUCTOR WAFER, PROCESS FOR
`MANUFACTURING ASEMCONDUCTOR
`INTEGRATED CIRCUIT DEVICE AND
`9
`SEMCONDUCTOR INTEGRATED CIRCUIT
`DEVICE
`75 Inventors: Hiroto Kawagoe, Hinode-machi;
`Tatsumi Shirasu, Kawasaki; Shogo
`Kiyota, Tateno-machi; Norio Suzuki,
`Higashimurayama; Eiichi Yamada,
`Kumage-gun; Yuji Sugino,
`Nakakoma-gun; Manabu Kitano,
`Yanai; Yoshihiko Sakurai; Takashi
`Naganuma, both of Nakakoma-gun;
`Hisashi Arakawa, Kohfu, all of Japan
`73 Assignee: Hitachi, Ltd., Tokyo, Japan
`
`4,477.310 10/1984 Park et al..
`4,525,920 7/1985 Jacobs et al..
`4,564,416
`1/1986 Homma et al. .
`4,578,128 3/1986 Mundt et al..
`4,622,082 11/1986 Dyson et al..
`4,684,971 8/1987 Payne et al..
`4,717,686
`1/1988 Jacobs et al..
`4,766,090 8/1988 Coquin et al..
`4,803,179 2/1989 Neppl et al..
`4,943,536 7/1990 Havemann.
`5,216.269 6/1993 Middelhoek et al..
`5,237,188 8/1993 Iwai et al..
`5,396,093 3/1995 Lu.
`5,508.540 4/1996 Ikeda et al..
`5,508,549 4/1996 Watanabe et al..
`OTHER PUBLICATIONS
`Wolf, S., “Silicon Processing for the VLSI Era vol. 1, pp.
`64-65, 1986.
`Ghandhi, S., “VSLI Fabrication Principles Silicon and Gal
`lium Arsenide,” pp. 735–738, 1994.
`Yamaguchi et al., “Process integration and device perfor
`21 Appl. No.: 08/934,774
`mance of a submicrometer BiCMOS with 16-GHz f(t)
`double Poly-Bipolar devices," IEEE Transactions on Elec
`22 Filed:
`Sep. 22, 1997
`tron Devices, vol. 36, No. 5 pp. 890-896, May 1989.
`Related U.S. Application Data
`Primary Examiner John F. Niebling
`ASSistant Examiner Jonathan Hack
`62) Division of application No. 08/508.483, Jul. 28, 1995,
`Attorney, Agent, or Firm- Antonelli, Terry, Stout & Kraus,
`abandoned.
`LLP
`Foreign Application Priority Data
`30
`ABSTRACT
`57
`Jul. 28, 1994
`JP
`Japan .................................... 6-176872
`Oct. 28, 1994
`JP
`Japan .................................... "“” Over the principal surface of a semiconductor substrate body
`51) Int. Cl." ...................... H01L 21/336; H01L 21/8234
`containing an impurity of a predetermined conduction type,
`52 U.S. Cl. .......................... 438/197; 438/222; 438/223;
`there is formed an epitaxial layer which contains an impurity
`438/224; 438/226; 438/227
`of the Same conduction type as that of the former impurity
`58 Field of Search ..................................... 438/197, 222,
`and the Same concentration as the designed one of the former
`438/223, 224, 226, 227
`impurity. After this, there are formed a well region which has
`the same conduction type as that of Said impurity and its
`impurity concentration gradually lowered depthwise of Said
`epitaxial layer. The well region is formed with the gate
`insulating films of MIS.FETs.
`
`56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`8/1976 Zirinsky et al..
`1/1977 Le Can et al. .
`
`3,974,003
`4,005,453
`
`42 Claims, 19 Drawing Sheets
`
`A 26 12t
`Y/S2SA
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`N N Y IN IN
`lNb
`5Sa
`Na
`lNC
`
`IN NIN N
`lPb
`Pa 5Sb 6
`
`
`
`PC
`
`Dell Ex. 1007
`Page 1
`
`

`

`U.S. Patent
`
`Mar. 28, 2000
`
`Sheet 1 of 19
`
`6,043,114
`
`
`
`
`
`
`
`4S232,2535K
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`lPa 5Sb
`P"a
`6
`
`FIG 2
`
`Dell Ex. 1007
`Page 2
`
`

`

`U.S. Patent
`
`Mar. 28, 2000
`Sheet 2 of 19
`FIG 3
`
`6,043,114
`
`FIG. 4.
`
`-vi
`
`FIG 5
`
`Y. -
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`
`Dell Ex. 1007
`Page 3
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`

`

`U.S. Patent
`
`Mar. 28, 2000
`
`Sheet 3 of 19
`
`6,043,114
`
`
`
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`APC
`kNb 4Pb
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`Pa
`
`Dell Ex. 1007
`Page 4
`
`

`

`U.S. Patent
`
`Mar.28, 2000
`
`Sheet 4 of 19
`
`6,043,114
`
`
`
`FIG. 8
`
`
` SONSEEasm =
`2WERy.
`
`TONICAVAL 26
`“Te
`4Pb
`4Pa
`SSb
`LNc
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`1
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`9Na
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`SNb=9Ph
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`Dell Ex. 1007
`
`Page 5
`
`Dell Ex. 1007
`Page 5
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`

`

`U.S. Patent
`
`Mar. 28, 2000
`
`Sheet 5 of 19
`
`6,043,114
`
`FIG 10
`
`v
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`
`Dell Ex. 1007
`Page 6
`
`

`

`U.S. Patent
`
`Mar. 28, 2000
`
`Sheet 6 of 19
`
`6,043,114
`
`
`
`ZS-Yegg-EZS 2st 2
`
`AS Q13 4.N.
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`Dell Ex. 1007
`Page 7
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`

`

`6,043,114
`
`
` FIG.
`
`715
`
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`Page 8
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`

`

`U.S. Patent
`
`Mar. 28, 2000
`
`Sheet 8 of 19
`
`6,043,114
`
`FIG 16
`
`F
`
`P 9Pa 10a
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`9Nb kN 9Na
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`Dell Ex. 1007
`Page 9
`
`

`

`U.S. Patent
`
`Mar. 28, 2000
`
`Sheet 9 of 19
`
`6,043,114
`
`FIG 17
`
`
`
`Dell Ex. 1007
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`

`

`U.S. Patent
`
`Mar. 28, 2000
`
`Sheet 10 of 19
`
`6,043,114
`
`FIG 18
`PRIOR ART
`
`
`
`0
`
`Wep 1
`Ww1
`-> DEPTH (m)
`
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`

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`U.S. Patent
`
`Mar. 28, 2000
`
`Sheet 11 of 19
`
`6,043,114
`
`FIG. 19
`PRIOR ART
`
`EP2
`
`
`
`SB2
`
`NS2
`
`0
`
`Wep2 WW2
`-> DEPTH (4 m)
`
`Dell Ex. 1007
`Page 12
`
`

`

`U.S. Patent
`
`/
`
`Mar. 28, 2000
`Sheet 12 of 19
`FIG. 20
`/ / / / / / /
`
`6,043,114
`
`2E
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`Dell Ex. 1007
`Page 13
`
`

`

`U.S. Patent
`
`Mar. 28, 2000
`
`Sheet 13 of 19
`
`6,043,114
`
`
`
`
`
`
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`
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`Dell Ex. 1007
`Page 14
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`

`

`U.S. Patent
`
`Mar. 28, 2000
`
`Sheet 14 Of 19
`
`6,043,114
`
`
`
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`Dell Ex. 1007
`Page 15
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`

`

`U.S. Patent
`
`Mar. 28, 2000
`
`Sheet 15 0f 19
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`6,043,114
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`Dell Ex. 1007
`Page 16
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`

`

`U.S. Patent
`
`Mar.28, 2000
`
`Sheet 16 of 19
`
`6,043,114
`
`
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`
`Dell Ex. 1007
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`Page 17
`
`Dell Ex. 1007
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`

`

`U.S. Patent
`
`Mar. 28, 2000
`
`Sheet 17 of 19
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`6,043,114
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`

`

`U.S. Patent
`
`Mar. 28, 2000
`
`6,043,114
`
`Sheet 18 of 19
`
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`
`Dell Ex. 1007
`Page 19
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`

`

`U.S. Patent
`
`Mar. 28, 2000
`
`Sheet 19 of 19
`
`6,043,114
`
`FIG 29
`
`
`
`Dell Ex. 1007
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`

`

`1
`PROCESS FOR MANUFACTURING A
`SEMICONDUCTOR WAFER, A
`SEMICONDUCTOR WAFER, PROCESS FOR
`MANUFACTURING ASEMCONDUCTOR
`INTEGRATED CIRCUIT DEVICE, AND
`SEMCONDUCTOR INTEGRATED CIRCUIT
`DEVICE
`
`This application is a Divisional application of application
`Ser. No. 08/508,483, filed Jul. 28, 1995 now abandoned.
`BACKGROUND OF THE INVENTION
`The present invention relates to a proceSS for manufac
`turing a Semiconductor wafer, a Semiconductor wafer, a
`proceSS for manufacturing a Semiconductor integrated cir
`cuit device, and a Semiconductor integrated circuit device
`and, more particularly, to a technique which is effective if
`applied to the So-called "epitaxial wafer manufacturing
`process' for forming an epitaxial layer over the Surface of a
`Semiconductor Substrate body, an epitaxial wafer, a proceSS
`for manufacturing a Semiconductor integrated circuit device
`by using the epitaxial wafer, and a Semiconductor integrated
`circuit device.
`An epitaxial wafer is a Semiconductor wafer which is
`formed with an epitaxial layer over the principal Surface of
`a mirror-finished (or -polished) Semiconductor mirror wafer
`(or polished wafer) by epitaxial growth. Incidentally, the
`epitaxial growth method is described, for example, on pp. 51
`to 74 of “VLSITECHNOLOGY, edited by S. M. Sze and
`issued in 1983 by McGraw-Hill. On the other hand, the
`polishing is described on pp. 39 to 42 of the same
`Publication, for example.
`The epitaxial wafer is advantageous in that it is excellent
`in Suppressing the Soft errors and resisting to the latchup,
`and in that the gate insulating film to be formed over the
`epitaxial layer can have excellent breakdown characteristics
`to drastically reduce the defect density of the gate insulating
`film. Thus, application of the epitaxial wafer to the technique
`for manufacturing the Semiconductor integrated circuit
`device.
`AS to this epitaxial wafer, there are the following two
`techniques.
`The first technique is described on pp. 761 to 763 of
`“ Applied Physics, Vol. 60, No. 8", issued on Aug. 10, 1991
`by Japanese ASSociation of Applied Physics. There is
`described an epitaxial wafer, in which a p-type (or n-type)
`Semiconductor Substrate is formed thereover with a p- (or n-)
`type epitaxial layer containing a p- (or n-) type impurity
`having a lower concentration than the p- (or n-) type
`impurity concentration of the Semiconductor Substrate.
`In this case, there is described the Structure in which a
`semiconductor region called the “well' is formed in the
`epitaxial layer and is formed thereover with a MOSFET.
`Since the well of this case is formed by the diffusion of the
`impurity from the Surface of the epitaxial layer, the impurity
`concentration in the well is distributed to be high in the
`Surface and low in its inside.
`The Second technique is described in Japanese Patent
`Laid-Open No. 260832/1989, for example and is directed to
`an epitaxial wafer which has a p-type epitaxial layer over a
`p-type Semiconductor Substrate. In this case, an element
`forming diffusion layer is formed to extend from the surface
`of the epitaxial layer to the upper portion of the Semicon
`ductor Substrate.
`Also described is a process, in which the Semiconductor
`substrate body is doped at the time of forming the diffusion
`
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`layer with a diffusion layer forming impurity So that Simul
`taneously with the growth of the epitaxial layer over the
`Semiconductor Substrate body, the impurity in the upper
`portion of the semiconductor Substrate body may be diffused
`to form the diffusion layer.
`The distribution of the impurity concentration of this case
`is made to have Such a plateau curve having a peak at the
`boundary between the epitaxial layer and the Semiconductor
`Substrate body that the impurity concentration is low at the
`Surface Side of the epitaxial layer, high at the boundary
`between the epitaxial layer and the Semiconductor Substrate
`body and low in the semiconductor Substrate body.
`The Semiconductor integrated circuit device manufac
`tured according to the aforementioned first technique is
`excellent in performance and reliability but has a problem in
`the cost because the Semiconductor Substrate used contains
`an (p-type or n-type) impurity in high concentration, is
`expensive, because an epitaxial layer having a large thick
`neSS is formed over the Semiconductor Substrate.
`According to the aforementioned Second technique, on
`the other hand, the diffusion layer is formed by the so-called
`“upper diffusion” to diffuse the impurity in the upper portion
`of the Semiconductor Substrate. As a result, the impurity
`concentration is So difficult to Set that there arise a problem
`that the diffusion layer forming accuracy drops. Another
`problem is that it is obliged to change the LSI (i.e., Large
`Scale Integration circuit) manufacturing process using the
`So-called “mirror wafer'.
`
`SUMMARY OF THE PRESENT INVENTION
`An object of the present invention is to provide a tech
`nique which can be implemented at comparatively low cost
`through the use of a semiconductor wafer having a semi
`conductor Single crystal layer over a Semiconductor Sub
`Strate.
`Another object of the present invention is to provide a
`technique capable of improving the performance and reli
`ability of a Semiconductor integrated circuit device and of
`SimultaneSusly reducing the cost for the Semiconductor
`integrated circuit device.
`An object of the present invention is to provide a tech
`nique capable of facilitating the control of forming a Semi
`conductor region on the Semiconductor wafer which has the
`Semiconductor Single crystal layer over the Semiconductor
`Substrate.
`An object of the present invention is to provide a tech
`nique capable of using a proceSS for manufacturing the
`Semiconductor integrated circuit device using the So-called
`“mirror wafer', as it is.
`The aforementioned and other objects and the novel
`features of the present invention will become apparent from
`the following description to be made with reference to the
`accompanying drawings.
`Representatives of the invention disclosed herein will be
`briefly described in the following.
`Specifically, according to the present invention, there is
`provided a proceSS for manufacturing a Semiconductor
`wafer, comprising the Step of forming Such a Semiconductor
`Single crystal layer over the Surface of a relatively lightly
`doped Semiconductor Substrate body, which contains an
`impurity of a predetermined conduction type, as contains an
`impurity having the same conduction type as that of Said
`impurity and the same concentration as the designed one of
`Said impurity.
`Moreover, according to the present invention, there is
`provided a process for manufacturing a Semiconductor inte
`
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`

`3
`grated circuit device, comprising: the Step of preparing a
`relatively lightly doped Semiconductor Substrate body,
`which contains an impurity of a predetermined conduction
`type, with a Semiconductor Single crystal layer formed over
`the Surface of the Semiconductor Substrate body and con
`taining an impurity having the same conduction type as that
`of Said impurity and the same concentration as the designed
`one of Said impurity; and the Step of forming an oxide film
`over Said Semiconductor Single crystal layer.
`Moreover, according to the present invention, there is
`provided a process for manufacturing a Semiconductor inte
`grated circuit device, comprising: the Step of preparing a
`relatively lightly doped Semiconductor Substrate body,
`which contains an impurity of a predetermined conduction
`type, with a Semiconductor Single crystal layer formed over
`the Surface of the Semiconductor Substrate body and con
`taining an impurity having the same conduction type as that
`of Said impurity and a concentration not higher than that of
`Said Semiconductor Substrate body; the Step of forming a
`first Semiconductor region extending from the Surface of
`Said Semiconductor Single crystal layer to the upper portion
`of Said Semiconductor Substrate body and having the same
`conduction type as that of Said impurity and its impurity
`concentration gradually lowered depthwise of Said Semicon
`ductor Single crystal layer; and the Step of forming an oxide
`film over Said Semiconductor region.
`Moreover, according to the present invention, there is
`provided a Semiconductor integrated circuit device manu
`facturing method comprising the Step of doping Said Semi
`conductor Single crystal layer with the ions an impurity and
`then thermally diffusing Said impurity, at the Step of forming
`Said first Semiconductor region.
`Moreover, according to the present invention, there is
`provided a Semiconductor integrated circuit device manu
`facturing method characterized in that Said first Semicon
`ductor region is a well to be used for forming a comple
`mentary MOS.FET (Metal-Oxide-Semiconductor. Field
`Effect-Transistor) circuit (i.e., for forming a complementary
`MIS (Metal-Insulator-Semiconductor). FET circuit).
`According to the aforementioned Semiconductor wafer
`manufacturing process of the present invention, any Semi
`conductor Substrate body of high price and density (of p- or
`n"-type) need not be used, and the Semiconductor single
`crystal layer can be thinned, So that the cost for the Semi
`conductor wafer capable of realizing high element charac
`teristics and reliability can be lowered.
`According to the aforementioned Semiconductor inte
`grated circuit device manufacturing process of the present
`invention, moreover, a gate insulating film having an excel
`lent film quality can be formed by forming the gate insu
`lating film of a MOS.FET over a semiconductor single
`crystal layer So that the gate insulating film can have its
`breakdown voltage raised to reduce the defect density of the
`gate insulating film. Moreover, the Semiconductor Substrate
`body of high price and density need not be used, but the
`Semiconductor Single crystal layer can be thinned to reduce
`the cost for the Semiconductor integrated circuit device
`having high element characteristics and reliability.
`According to the aforementioned Semiconductor inte
`grated circuit device manufacturing process of the present
`invention, moreover, the degree of freedom for Setting the
`impurity concentration and depth is So high when a Semi
`conductor region Such as a well is formed in the Semicon
`ductor Substrate, as to facilitate the control of the formation.
`AS a result, it is possible to reduce the defective products
`thereby to improve the production yield. Moreover, the cost
`for the Semiconductor integrated circuit device can be low
`ered.
`
`15
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`4
`According to the aforementioned Semiconductor inte
`grated circuit device manufacturing process of the present
`invention, moreover, the impurity concentration of the Semi
`conductor Substrate body below the Semiconductor Single
`crystal layer is made higher than that of the Semiconductor
`Single crystal layer, So that the resistance of the Semicon
`ductor substrate body can be relatively lowered to improve
`the resistance to the latchup.
`According to the aforementioned Semiconductor inte
`grated circuit device manufacturing process of the present
`invention, moreover, Since the first Semiconductor region is
`formed by the ion implantation method and the thermal
`diffusion method, the Semiconductor integrated circuit
`device can be manufactured without being accompanied by
`any change in the design or manufacture proceSS but by
`using the same method as that of the Semiconductor inte
`grated circuit device having the So-called "mirror wafer',
`when it is to be manufactured by using the Semiconductor
`wafer having the Semiconductor Single crystal layer over the
`Semiconductor Substrate body.
`According to the aforementioned Semiconductor inte
`grated circuit device manufacturing process of the present
`invention, moreover, Since the memory cell of the dynamic
`type random acceSS memory is formed over the Semicon
`ductor Single crystal layer having leSS defects Such as the
`precipitation of oxygen, it is possible to reduce the junction
`leakage current in the Source region and the drain region of
`the transfer MOS.FET of the memory cell. Since, moreover,
`the charge leakage in the capacitor of the memory cell can
`be Suppressed to elongate the charge Storage time period, it
`is possible to improve the refresh characteristics. As a result,
`it is possible to improve the performance, reliability and
`production yield of the dynamic type random access
`memory.
`According to the aforementioned Semiconductor inte
`grated circuit device manufacturing process of the present
`invention, moreover, Since the memory cell of the Static type
`random acceSS memory is formed over the Semiconductor
`Single crystal layer having less defects Such as the precipi
`tation of oxygen, the junction leakage current of the Source
`region and drain region of the MOS FET composing the
`memory cell can be reduced to improve the data retention
`level thereby to reduce the data retention fault percentage.
`AS a result, it is possible to improve the performance,
`reliability and production yield of the Static type random
`acceSS memory.
`According to the aforementioned Semiconductor inte
`grated circuit device manufacturing process of the present
`invention, moreover, the memory cell of a read only memory
`capable of electrically erasing and programming data is
`formed over the Semiconductor Single crystal layer having
`less defects Such as the precipitation of oxygen, So that the
`resistance to the data programming can be improved and So
`that the dispersion of the data erasure can be reduced. AS a
`result, it is possible to improve the performance, reliability
`and production yield of the read only memory capable of
`electrically erasing and programming the data.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a Section showing an essential portion of a
`Semiconductor integrated circuit device according to one
`embodiment of the present invention;
`FIG. 2 is a top plan View showing a Semiconductor wafer
`to be used at a step of manufacturing the Semiconductor
`integrated circuit device of FIG. 1;
`FIG. 3 is a Section showing an essential portion at a step
`of manufacturing the Semiconductor integrated circuit
`device of FIG. 1;
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`FIG. 4 is a Section showing an essential portion at the Step,
`as Subsequent to FIG. 3, of manufacturing the Semiconduc
`tor integrated circuit device of FIG. 1;
`FIG. 5 is a Section showing an essential portion at the Step,
`as Subsequent to FIG. 4, of manufacturing the Semiconduc
`tor integrated circuit device of FIG. 1;
`FIG. 6 is a Section showing an essential portion at the Step,
`as Subsequent to FIG. 5, of manufacturing the Semiconduc
`tor integrated circuit device of FIG. 1;
`FIG. 7 is a Section showing an essential portion at the Step,
`as Subsequent to FIG. 6, of manufacturing the Semiconduc
`tor integrated circuit device of FIG. 1;
`FIG. 8 is a Section showing an essential portion at the Step,
`as Subsequent to FIG. 7, of manufacturing the Semiconduc
`tor integrated circuit device of FIG. 1;
`FIG. 9 is a Section showing an essential portion of a
`Semiconductor integrated circuit device according to another
`embodiment of the present invention;
`FIG. 10 is a Section showing an essential portion at a step
`of manufacturing the Semiconductor integrated circuit
`device of FIG. 9;
`FIG. 11 is a Section showing an essential portion at the
`Step, as Subsequent to FIG. 10, of manufacturing the Semi
`conductor integrated circuit device of FIG. 9;
`FIG. 12 is a Section showing an essential portion of a
`Semiconductor integrated circuit device according to another
`embodiment of the present invention;
`FIG. 13 is a Section showing an essential portion at a step
`of manufacturing the Semiconductor integrated circuit
`device of FIG. 12;
`FIG. 14 is a Section showing an essential portion at the
`step, as Subsequent to FIG. 13, of manufacturing the semi
`conductor integrated circuit device of FIG. 12;
`FIG. 15 is a Section showing an essential portion at the
`Step, as Subsequent to FIG. 14, of manufacturing the Semi
`conductor integrated circuit device of FIG. 12;
`FIG. 16 is a Section showing an essential portion of a
`Semiconductor integrated circuit device according to another
`embodiment of the present invention;
`FIG. 17 is an impurity distribution diagram in the semi
`conductor integrated circuit device of FIG. 16 and has an
`abscissa indicating the depth from the Surface of an epitaxial
`layer 2E and an ordinate indicating an impurity concentra
`tion;
`FIG. 18 is an impurity distribution diagram in the semi
`conductor integrated circuit device, as has been described in
`the prior art and has an abscissa indicating the depth from
`the Surface of an epitaxial layer EP1 and an ordinate
`indicating an impurity concentration;
`FIG. 19 is an impurity distribution diagram in the semi
`conductor integrated circuit device, as has been described in
`the prior art and has an abscissa indicating the depth from
`the Surface of an epitaxial layer EP2 and an ordinate
`indicating an impurity concentration;
`FIG. 20 is a Section showing an essential portion of a
`Semiconductor Substrate at a Step of manufacturing the
`semiconductor integrated circuit device of FIG. 16;
`FIG. 21 is a Section showing an essential portion of the
`Semiconductor Substrate at the Step, as Subsequent to FIG.
`20, of manufacturing the Semiconductor integrated circuit
`device of FIG. 16;
`FIG. 22 is a Section showing an essential portion of the
`Semiconductor Substrate at the Step, as Subsequent to FIG.
`21, of manufacturing the Semiconductor integrated circuit
`device of FIG. 16;
`
`1O
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`15
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`50
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`FIG. 23 is a Section showing an essential portion of the
`Semiconductor Substrate at the Step, as Subsequent to FIG.
`22, of manufacturing the Semiconductor integrated circuit
`device of FIG. 16;
`FIG. 24 is a Section showing an essential portion of the
`Semiconductor Substrate at the Step, as Subsequent to FIG.
`23, of manufacturing the Semiconductor integrated circuit
`device of FIG. 16;
`FIG.25 is a graph diagram for explaining the effects of the
`Semiconductor integrated circuit device of the present
`embodiment;
`FIG. 26(A) is a Section showing an essential portion of a
`Semiconductor integrated circuit device according to another
`embodiment of the present invention;
`FIG. 26(B) is a circuit diagram showing a memory cell of
`the semiconductor integrated circuit device of FIG. 26(A);
`FIG. 27(A) is a Section showing an essential portion of a
`Semiconductor integrated circuit device according to another
`embodiment of the present invention;
`FIG. 27(B) is a circuit diagram showing a memory cell of
`the semiconductor integrated circuit device of FIG. 27(A);
`FIG. 28 is a Section showing an essential portion of a
`Semiconductor integrated circuit device according to another
`embodiment of the present invention;
`FIG. 29 is a Section showing an essential portion at a step
`of manufacturing a Semiconductor integrated circuit device
`according to another embodiment of the present invention;
`and
`FIG. 30 is a section showing an essential portion at the
`Step, as Subsequent to FIG. 29, of manufacturing a Semi
`conductor integrated circuit device according to another
`embodiment of the present invention.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`The present invention will be described in detail in the
`following in connection with its embodiments with refer
`ence to the accompanying drawings.
`(Embodiment 1)
`FIG. 1 is a Section showing an essential portion of a
`Semiconductor integrated circuit device according to one
`embodiment of the present invention; FIG. 2 is a top plan
`View of a Semiconductor wafer to be used in a process for
`manufacturing the Semiconductor integrated circuit device
`of FIG. 1; and FIGS. 3 to 8 are sections showing an essential
`portion in a process for manufacturing the Semiconductor
`integrated circuit device of FIG. 1.
`AS shown in FIG. 1, a Semiconductor Substrate 2 consti
`tuting a Semiconductor integrated circuit device 1 of the
`present embodiment 1 is constructed of a Semiconductor
`Substrate body 2S, an epitaxial layer (i.e., semiconductor
`Single crystal layer) 2E and a gettering layer (i.e., trap
`region) 2G.
`Incidentally, the gettering layer is described, for example,
`on pp. 42 to 44 of “VLSITECHNOLOGY”, edited by S. M.
`Sze and issued in 1983 by McGraw-Hill.
`The semiconductor substrate body 2S is made of a single
`crystal of p-type Silicon (Si) having a thickness of about
`500 to 800 um, for example. The semiconductor substrate
`body 2S is doped with a p-type impurity such as boron (B)
`in a concentration of about 1.3x10" atoms/cm.
`Over the principal Surface of the Semiconductor Substrate
`body 2S, there is formed the epitaxial layer 2E which is
`made of a single crystal of p-type Si, for example. This
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`epitaxial layer 2E is doped with a p-type impurity Such as
`boron in a concentration equal to the designed one of the
`semiconductor substrate body 2S, e.g., 1.3x10" atoms/cm.
`Here, the designed impurity concentration is intended to
`cover an allowable value. Specifically, the equality to the
`designed impurity concentration means that, in case the
`Semiconductor Substrate body 2S has its designed impurity
`concentration expressed by impurity concentration: At
`allowable value: C. and has an actual impurity concentra
`tion of A, the semiconductor substrate body 2S and the
`epitaxial layer 2E have equal impurity concentrations if the
`actual impurity concentration of the epitaxial layer 2E is not
`at A but within Ato.
`Thus, in the present embodiment 1, the p-type epitaxial
`layer 2E is formed over the relatively lightly doped p-type
`Semiconductor Substrate body 2S, and any precious heavily
`doped p-type Semiconductor Substrate body is not used so
`that the cost for the Semiconductor Substrate 2 can be
`reduced to one half or So.
`In case the cost for the Semiconductor Substrate of the
`prior art having the p-type epitaxial layer formed over the
`p"-type Semiconductor Substrate body, for example, is 2.5 to
`3 times as high as that of the ordinary Semiconductor
`Substrate having no epitaxial layer. On the contrary, the cost
`for the Semiconductor Substrate of the present embodiment
`1 can be Suppressed within 1.5 times as high as that of the
`ordinary Semiconductor Substrate. As a result, the cost for
`the Semiconductor integrated circuit device can be lowered.
`The epitaxial layer 2E is made relatively thin to have a
`thickness of about 1 um. As a result, the following effects
`can be attained.
`At first, it is easy to control the Setting of the thickneSS or
`resistivity of the epitaxial layer 2E. Secondly, for the first
`reason, the apparatus used for forming the epitaxial layer is
`not required to have a high filming accuracy Such as thick
`neSS uniformity or doping uniformity of the deposited film
`So that it needs not be expensive. Thirdly, the epitaxial layer
`can be easily formed to improve the throughput. Fourthly,
`for the first, Second and third reasons, it is possible to reduce
`the cost for the Semiconductor Substrate 2.
`The lower limit of the thickness of the epitaxial layer 2E
`is one half or more of the thickness of the gate insulating film
`in the later-described MOS.FET. This setting is made while
`considering that one half of the thickness of the gate
`insulating film of the MOS.FET goes into the side of the
`Semiconductor Substrate 2 when the gate insulating film is
`formed.
`Specifically, in case the epitaxial layer 2E is made thinner
`than one half of the thickness of a gate insulating film, its
`entirety is covered with the gate insulating film when this
`film is to be formed over the epitaxial layer 2E. As a result,
`the Structure is made Such that the gate insulating film is
`formed over the semiconductor Substrate body 2S. This
`Structure loses the effect of the case, in which the gate
`insulating film is formed over the epitaxial layer 2E, namely,
`that an excellent gate insulating film can be formed to
`improve its breakdown Voltage.
`Incidentally, the lower limit of the thickness of the epi
`taxial layer 2E is frequently Set to 0.3 um by evaluating the
`performance of the gate insulating film (e.g., the gate
`breakdown voltage), as will be described with reference to
`FIG. 25.
`On the other hand, the upper limit of the thickness of the
`epitaxial layer 2E cannot be generally Said because it
`depends upon the product or manufacturing conditions, but
`may desirably be less than 5 um, for example, if the
`following is considered.
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`Specifically, first of all, the upper Surface of the epitaxial
`layer 2E can retain flatness. If the epitaxial layer 2E is made
`thicker, the level difference of the principal Surface of the
`Semiconductor Substrate body 2S is accordingly increased,
`but no substantial difference is caused by the thickness of
`Such extent.
`If the principal Surface has an excessively large
`roughness, a larger level difference than the focal depth may
`be made in a photolithography for the later-described MIS
`device forming Step, thus causing a problem that the pattern
`cannot be formed by the photolithography.
`Secondly, the cost for the mother material of the semi
`conductor Substrate 2 or the Semiconductor wafer (i.e., the
`later-described epitaxial wafer) can be Suppressed within a
`low price. If the epitaxial layer 2E is thickened, it is difficult
`to control the filming operation, as described above, So that
`the cost for the Semiconductor wafer (i.e., the later-described
`epitaxial wafer) rises. However, this thickness will not invite
`a drastic increase in the cost.
`Thirdly, the roughness, if any, on the principal Surface of
`the semiconductor substrate body 2S can be ignored. With
`the thickness of this order, the roughness will not make