`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`DELL TECHNOLOGIES INC. AND DELL INC.,
`Petitioners,
`v.
`GREENTHREAD LLC,
`Patent Owner.
`____________
`
`Case: IPR2023-00506
`U.S. Patent No. 10,510,842
`____________
`
`DECLARATION OF TRAVIS BLALOCK, PH.D.
`
`
`
`
`
`
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`Dell Ex. 1003
`Page 1
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`
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`I, Dr. Travis Blalock, declare as follows:
`
`1. My name is Travis Blalock.
`
`2. I have been retained as an expert witness on behalf of Dell Technologies Inc.
`
`and Dell (collectively “Dell” or “Petitioner”) for the above-captioned Petition for
`
`Inter Partes Review (“Petition”) of U.S. Patent No. 10,510,842 (the “’842 Patent”)
`
`(Ex. 1001). I am being compensated for my time in connection with this Petition at
`
`my standard consulting rate of $450 per hour. My compensation is not affected by
`
`the outcome of this matter.
`
`3. I have been asked to provide my opinions regarding whether claims 1-18 of
`
`the ’842 Patent (the “Challenged Claims”) are invalid as obvious to a person having
`
`ordinary skill in the art at the time of the alleged invention.
`
`4. I am not currently, and have not at any time in the past been, an employee of
`
`Dell. I have no financial interest in Dell.
`
`5. Previously, I submitted a declaration on December 5, 2022 in IPR2023-00308
`
`on behalf of Intel Corporation. My declaration in IPR2023-00308 was directed to
`
`the same patent, the same Challenged Claims, the same combinations of prior art
`
`references, and the same invalidity theories that form the bases for my opinions here.
`
`6. My opinions regarding the invalidity of the Challenged Claims of the ’842
`
`Patent have not changed and are identical to my opinions in the declaration submitted
`
`in IPR2023-00308. My background and qualifications are also unchanged since that
`
`
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`
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`date. Therefore, I incorporate my previous declaration in its entirety and attach it as
`
`Exhibit A to this declaration, which is reproduced below.
`
` hereby declare that all statements made herein of my own knowledge are true and
`
` I
`
`that all statements made on information and belief are believed to be true; and further
`
`that these statements were made with the knowledge that willful false statements and
`
`the like so made are punishable by fine or imprisonment, or both, under Section 1001
`
`of Title 18 of the United States Code and that such willful false statements may
`
`jeopardize the results of the proceedings.
`
`
`
`
`
`
`
`
`
`
`
`Respectfully Submitted,
`
`_________________________
`Travis Blalock, Ph.D.
`
`
`
`Date: January 27, 2023
`
`
`
`
`
`
`
`
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`
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`
`APPENDIX A
`APPENDIX A
`
`Page 4
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 10,510,842
`
`
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`
`INTEL CORPORATION,
`Petitioner
`
`v.
`
`GREENTHREAD LLC,
`Patent Owner
`
`
`
`U.S. PATENT NO. 10,510,842
`
`Case IPR2023-TBD
`
`
`DECLARATION OF TRAVIS BLALOCK, PH.D.
`
`
`
`
`
`
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 10,510,842
`
`TABLE OF CONTENTS
`
`I.
`
`BACKGROUND AND QUALIFICATIONS ................................................. 1
`
`II. MATERIALS AND OTHER INFORMATION CONSIDERED ................... 5
`
`III. UNDERSTANDING OF PATENT LAW ...................................................... 8
`
`A.
`
`B.
`
`Claim Construction................................................................................ 8
`
`Obviousness ........................................................................................... 8
`
`IV. SUMMARY OF OPINIONS .........................................................................10
`
`V. OVERVIEW OF THE TECHNOLOGY .......................................................11
`
`VI. THE ’842 PATENT .......................................................................................15
`
`A.
`
`B.
`
`C.
`
`Claims ..................................................................................................15
`
`Summary of the Specification .............................................................15
`
`Summary of the Prosecution History ..................................................18
`
`VII. LEVEL OF ORDINARY SKILL IN THE ART ...........................................19
`
`VIII. CLAIM CONSTRUCTION ..........................................................................20
`
`IX. OVERVIEW OF THE PRIOR ART .............................................................22
`
`A. Kawagoe ..............................................................................................22
`
`B. Wieczorek ............................................................................................25
`
`C. Wolf .....................................................................................................27
`
`D. Gupta ...................................................................................................27
`
`X.
`
`SPECIFIC GROUNDS FOR PETITION ......................................................27
`
`A. Ground I: .............................................................................................27
`
`1.
`
`Independent Claim 1 .................................................................27
`
`i
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 10,510,842
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`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`7.
`
`8.
`
`9.
`
`Dependent Claim 2: “The semiconductor device of claim
`1, wherein the substrate is a p-type substrate.” .........................49
`
`Dependent Claim 4: “The semiconductor device of claim
`1, wherein the substrate has epitaxial silicon on top of a
`nonepitaxial substrate.” .............................................................49
`
`Dependent Claim 5: “The semiconductor device of claim
`1, wherein the first active region and second active
`region contain one of either p-channel and n-channel
`devices.” ....................................................................................49
`
`Dependent Claim 6: “The semiconductor device of claim
`1, wherein the first active region and second active
`region contain either p-channel or n-channel devices in n-
`wells or p-wells, respectively, and each well has a graded
`dopant.” .....................................................................................50
`
`Dependent Claim 7: “The semiconductor device of claim
`1, wherein the first active region and second active
`region are each separated by at least one isolation
`region.” ......................................................................................51
`
`Dependent Claim 8: “The semiconductor device of claim
`1, wherein the graded dopant is fabricated with an ion
`implantation process.” ...............................................................52
`
`Independent Claim 9 .................................................................53
`
`Dependent Claim 10: “The semiconductor device of
`claim 9, wherein the substrate is a p-type substrate.” ...............55
`
`10. Dependent Claim 12: “The semiconductor device of
`claim 9, wherein the substrate has epitaxial silicon on top
`of a nonepitaxial substrate.” ......................................................55
`
`11. Dependent Claim 13: “The semiconductor device of
`claim 9, wherein the first active region and second active
`region contain at least one of either p-channel and n-
`channel devices.” ......................................................................55
`
`ii
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 10,510,842
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`12. Dependent Claim 14: “The semiconductor device of
`claim 9, wherein the first active region and second active
`region contain either p-channel or n-channel devices in n-
`wells or p-wells, respectively, and each well has a graded
`dopant.” .....................................................................................55
`
`13. Dependent Claim 15: “The semiconductor device of
`claim 9, wherein the first active region and second active
`region are each separated by at least one isolation
`region.” ......................................................................................56
`
`14. Dependent Claim 16: “The semiconductor device of
`claim 9, wherein the graded dopant is fabricated with an
`ion implantation process.” ........................................................56
`
`15. Dependent Claim 17: “The semiconductor device of
`claim 1, wherein the first and second active regions are
`formed adjacent the first surface of the substrate.” ..................56
`
`16. Dependent Claim 18: “The semiconductor device of
`claim 1, wherein the transistors which can be formed in
`the first and second active regions are CMOS transistors
`requiring a source, a drain, a gate and a channel region.” ........57
`
`B.
`
`Ground II: ............................................................................................58
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`Independent Claim 1 .................................................................59
`
`Dependent Claim 2: “The semiconductor device of claim
`1, wherein the substrate is a p-type substrate.” .........................74
`
`Dependent Claim 3: “The semiconductor device of claim
`1, wherein the substrate is an n-type substrate.” .......................74
`
`Dependent Claim 5: “The semiconductor device of claim
`1, wherein the first active region and second active
`region contain one of either p-channel and n-channel
`devices.” ....................................................................................75
`
`Dependent Claim 6: “The semiconductor device of claim
`1, wherein the first active region and second active
`region contain either p-channel or n-channel devices in n-
`
`iii
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 10,510,842
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`wells or p-wells, respectively, and each well has a graded
`dopant.” .....................................................................................75
`
`Dependent Claim 7: “The semiconductor device of claim
`1, wherein the first active region and second active
`region are each separated by at least one isolation
`region.” ......................................................................................76
`
`Dependent Claim 8: “The semiconductor device of claim
`1, wherein the graded dopant is fabricated with an ion
`implantation process.” ...............................................................77
`
`Independent Claim 9 .................................................................77
`
`Dependent Claim 10: “The semiconductor device of
`claim 9, wherein the substrate is a p-type substrate.” ...............80
`
`6.
`
`7.
`
`8.
`
`9.
`
`10. Dependent Claim 11: “The semiconductor device of
`claim 9, wherein the substrate is an n-type substrate.” .............80
`
`11. Dependent Claim 13: “The semiconductor device of
`claim 9, wherein the first active region and second active
`region contain at least one of either p-channel and n-
`channel devices.” ......................................................................80
`
`12. Dependent Claim 14: “The semiconductor device of
`claim 9, wherein the first active region and second active
`region contain either p-channel or n-channel devices in n-
`wells or p-wells, respectively, and each well has a graded
`dopant.” .....................................................................................80
`
`13. Dependent Claim 15: “The semiconductor device of
`claim 9, wherein the first active region and second active
`region are each separated by at least one isolation
`region.” ......................................................................................80
`
`14. Dependent Claim 16: “The semiconductor device of
`claim 9, wherein the graded dopant is fabricated with an
`ion implantation process.” ........................................................81
`
`iv
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 10,510,842
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`15. Dependent Claim 17: “The semiconductor device of
`claim 1, wherein the first and second active regions are
`formed adjacent the first surface of the substrate.” ..................81
`
`16. Dependent Claim 18: “The semiconductor device of
`claim 1, wherein the transistors which can be formed in
`the first and second active regions are CMOS transistors
`requiring a source, a drain, a gate and a channel region.” ........81
`
`C.
`
`GROUNDS III/IV ...............................................................................83
`
`XI. CONCLUSION ..............................................................................................88
`
`
`
`v
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 10,510,842
`
`I, Dr. Travis Blalock, declare as follows:
`
` My name is Travis Blalock.
`
`
`
`I have been retained as an expert witness on behalf of Intel Corporation
`
`(“Intel” or “Petitioner”) for the above-captioned Petition for Inter Partes Review
`
`(“Petition”) of U.S. Patent No. 10,510,842 (the “’842 Patent”) (Ex. 1001). I am being
`
`compensated for my time in connection with this Petition at my standard consulting
`
`rate of $450 per hour. My compensation is not affected by the outcome of this matter.
`
`
`
`I have been asked to provide my opinions regarding whether claims 1-
`
`18 of the ’842 Patent (the “Challenged Claims”) are invalid as obvious to a person
`
`having ordinary skill in the art at the time of the alleged invention.
`
`
`
`The ’842 Patent issued on December 17, 2019 from Application No.
`
`15/590,282, filed on May 9, 2017. The ’842 Patent claims priority to Application
`
`No. 10/934,915, filed on September 3, 2004.
`
`
`
`I am not currently, and have not at any time in the past been, an
`
`employee of Intel. I have no financial interest in Intel.
`
`I.
`
`BACKGROUND AND QUALIFICATIONS
`
`
`
`I am currently an Associate Professor at the University of Virginia. I
`
`served as an Associate Professor from 1998 until 2013 when I moved to a non-
`
`resident Associate Professor position so I could lead a Handheld Ultrasound R&D
`
`team for Analogic, Inc. I earned my Bachelor of Science and Master of Science in
`
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`Electrical Engineering from the University of Tennessee at Knoxville in 1985 and
`
`1988 respectively. I earned my Ph.D. from Auburn University in 1991. The primary
`
`emphasis of my doctoral research was CMOS analog and digital integrated circuit
`
`design.
`
`
`
`From 1991 through August 1998, I worked at Hewlett Packard
`
`Laboratories, first as a Member of the Technical Staff, and then as a Principal
`
`Scientist. My work at Hewlett Packard Laboratories involved design and
`
`implementation of digital and analog integrated circuits. I was the principal architect
`
`and designer of integrated circuits having a diverse range of applications, including
`
`CMOS analog signal processing integrated circuits for mass storage devices and
`
`optoelectronic image acquisition and processing integrated circuits. I also have
`
`experience with software and custom design tools that allow for improved analysis,
`
`modeling, and simulation of integrated circuit analysis and design.
`
` While I was employed at Hewlett-Packard Laboratories (now Agilent
`
`Laboratories) I was the lead designer on several mixed-signal CMOS chips. One of
`
`these was a massively parallel analog signal processing prototype integrated circuit
`
`[1]. The chip measures position with an accuracy of better than 100 µm over 10
`
`inches by cross-correlating past and present images acquired by the integrated photo-
`
`array. The photodetector design was based on an understanding of dopant profiles
`
`and the resulting effects on detector sensitivity. This was incorporated into the
`
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 10,510,842
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`detection circuit design to optimize response. The chip has a 2048 element 25,000
`
`frame/second photoreceiver array coupled with an analog signal processing cross-
`
`correlation array. The array performs a set of 9 nearest-neighbor cross-correlations
`
`between the two images at a total computation throughput of 1.5 billion operations
`
`per second. Over 100 million second generation versions of this chip have been sold
`
`and the architecture forms the core of most optical mice.
`
`
`
`I was also the technical lead in the design of a 1024 x 768 silicon
`
`backplane ferro-electric liquid-crystal microdisplay. The chip also includes 1024
`
`compact, offset-corrected column amplifiers and high-speed analog signal
`
`distribution. Both of the above chip designs were the highest density mixed-signal
`
`integrated circuits ever produced within Hewlett-Packard (at that time) and were
`
`fully functional at first silicon. I was also directly involved in the testing and
`
`verification of these chips in the laboratory.
`
` At the University of Virginia, I led research in design of low-power
`
`mixed-signal integrated circuits. This work covered a broad range of application
`
`areas including medical ultrasound, subthreshold RFID for mobile health
`
`applications, wearable sensors, custom RFID for bio-tracking of plaque propagation,
`
`infrared imaging, cryptographic hardening, and sensors for CMOS process
`
`reliability.
`
`3
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 10,510,842
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` More recently, I have led the development of a CMOS 600 channel low
`
`power medical imaging front-end integrated circuit. The chip simultaneously
`
`amplifies, filters, and digitizes signals from 600 independent ultrasound transducer
`
`elements. The chip development was part of an independent medical ultrasound
`
`startup (PocketSonics, Inc.) I founded which was acquired by Analogic, Inc in 2013.
`
`This work led to the development and release of a handheld medical ultrasound
`
`product by Analogic, Inc. This device was powered by a lithium-ion battery and
`
`included circuits to manage high peak currents, pulse-width modulation for
`
`controlled power delivery, charge management, and battery protection circuits.
`
`
`
`I am currently a collaborator with the Integrated Electromagnetics,
`
`Circuits, and Systems Lab at the University of Virginia. In this group we design a
`
`variety of high frequency RF integrated circuits and merged RF/Optical circuits. Of
`
`particular interest are low power wake-up receivers, clock recovery, and high
`
`efficiency power amps for battery powered RF circuits.
`
`
`
`I have written widely in the field of electrical engineering, including
`
`several editions of a textbook that is used across the world to teach principles of
`
`microelectronic circuit design to undergraduate and graduate students. I have
`
`authored or co-authored over 50 journal and conference papers. My textbook
`
`includes discussions of the solid-state physics needed to understand the operation of
`
`semiconductor diodes, BJT transistors, and CMOS transistors. In the course of
`
`4
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 10,510,842
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`integrated circuit design teaching and practice, particularly the low noise, high
`
`sensitivity circuits I have focused on, it has been essential to understand the device
`
`physics and how neighboring devices may interact to understand subtle effects that
`
`impact the success of both industrial and academic designs.
`
`
`
`I have contributed to or consulted on the design, fabrication, and/or
`
`operation of integrated circuits, including microelectronic integrated circuits, for
`
`organizations such as Hewlett-Packard, NASA Langley Research Center, Agilent
`
`Technologies, Displaytech, PocketSonics, and Analogic.
`
`
`
`I am a named inventor on at least 27 U.S. patents. Several of these
`
`concern analog circuitry or semiconductor design, including guard rings, charge
`
`storage devices, and photosensors.
`
` My qualifications and publications are set forth more fully in my
`
`curriculum vitae, attached.
`
`II. MATERIALS AND OTHER INFORMATION CONSIDERED
`
`
`
`In forming the opinions expressed in this Declaration, I relied upon my
`
`education and experience in the relevant field of the art and have considered the
`
`viewpoint of a person having ordinary skill in the art (POSITA) at the time of the
`
`alleged invention.
`
`
`
`I have considered the materials referenced herein, including the ’842
`
`Patent (Ex. 1001), the file history of the ’842 Patent (Ex. 1002), the parent and
`
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 10,510,842
`
`related applications, the file histories of the parent and related applications, including
`
`for the parent ’195 Patent (Ex. 1016), the Petition, and other documents listed in the
`
`Exhibit List of the Petition, including:
`
`Description
`U.S. Patent Application Publication
`No. 2003/0183856 to Wieczorek
`(“Wieczorek”) (Ex. 1006)
`U.S. Patent No. 6,043,114 to
`Kawagoe, et al. (“Kawagoe”) (Ex.
`1007)
`Stanley Wolf and Richard N. Tauber,
`Silicon Processing For The VLSI Era,
`Vol 1, Lattice Press (2000)
`(“Wolf.1”) (Ex. 1008A)
`Stanley Wolf and Richard N. Tauber,
`Silicon Processing For The VLSI Era,
`Vol. 2, Lattice Press (2000)
`(“Wolf.2”) (Ex. 1008B)
`Stanley Wolf and Richard N. Tauber,
`Silicon Processing For The VLSI Era,
`Vol. 3, Lattice Press (2000)
`(“Wolf.3”) (Ex. 1008C)
`Stanley Wolf and Richard N. Tauber,
`Silicon Processing For The VLSI Era,
`Vol. 4, Lattice Press (2000)
`(“Wolf.4”) (Ex. 1008D)
`Wang and Agrawal, Single Event
`Upset: An Embedded Tutorial, 21st
`Intl Conf on VLSI Design, IEEE 2008
`(“Wang”) (Ex. 1009)
`U.S. Patent No. 4,481,522
`(“Jastrzebski”) (Ex. 1010)
`U.S. Patent No. 6,163,877 (“Gupta”)
`(Ex. 1014)
`U.S. Patent No. 6,534,805 (“Jin”)
`(Ex. 1015)
`
`Date of Public Availability
`Filed on October 29, 2002 (with
`priority to March 28, 2002).
`
`Filed on September 22, 1997 (with
`priority to July 28, 1995) and issued
`on March 28, 2000.
`Published and publicly available no
`later than 2002.
`
`Published and publicly available no
`later than 2002.
`
`Published and publicly available no
`later than 2002.
`
`Published and publicly available no
`later than 2002.
`
`Published and publicly available in
`2008.
`
`Filed March 24, 1982 and issued on
`November 6, 1984.
`Filed November 5, 1996 and issued
`on December 19, 2000.
`Filed April 9, 2001 and issued on
`March 18, 2003.
`
`6
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 10,510,842
`
`Description
`Sze, Semiconductor Devices Physics
`and Technology, 2d Ed., John Wiley
`& Sons (2002) (Ex. 1022)
`
`Maziasz and Hayes, Layout
`Minimization of CMOS Cells, Kluwer
`Academic Publishers (1992)
`(“Maziasz”) (Ex. 1023)
`
`Rabaey et al., Digital Integrated
`Circuits, A Design Perspective,
`Prentice Hall Electronics and VLSI
`Series (2003) (“Rabaey”) (Ex. 1025)
`
`Gregory and Shafer, “Latch-Up In
`CMOS Integrated Circuits,” IEEE
`Transactions on Nuclear Science,
`Volume 20, Issue 6 (1973) (Ex. 1026)
`
`Date of Public Availability
`Published and publicly available in
`2002.
`
`Published and publicly available in
`1992.
`
`Published and publicly available in
`2003.
`
`Published and publicly available in
`1973.
`
`U.S. Patent No. 4,160,985 to Kamins
`et al. (“Kamins”) (Ex. 1031)
`
`Filed November 25, 1977 and
`issued July 10, 1979.
`
`McGraw-Hill Dictionary of Scientific
`and Technical Terms (2003) (Ex.
`1032)
`
`U.S. Patent Application Publication
`No. 2003/0030488 to Hueting et al.
`(“Hueting”) (Ex. 1035)
`
`Published and publicly available in
`2003.
`
`Filed July 25, 2002 (with priority to
`August 7, 2001).
`
` The references listed above include prior art to the ’842 Patent which is
`
`entitled to a priority date not earlier than September 3, 2004. None of the prior art
`
`references were before the Patent Office during prosecution.
`
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 10,510,842
`
`III. UNDERSTANDING OF PATENT LAW
`
`
`
`I am not an attorney. For purposes of this declaration, I have been
`
`informed about certain aspects of the law that are relevant to my opinions. My
`
`understanding of the law is as listed below.
`
`A. Claim Construction
`
`
`
`I understand that in an IPR petition filed after November 13, 2018, a
`
`claim must be construed under the Phillips standard. Under that standard, words of
`
`a claim are given their plain and ordinary meaning as understood by a POSITA at
`
`the time of invention, in light of the specification and prosecution history, unless
`
`those sources show an intent to depart from such meaning, as well as pertinent
`
`evidence extrinsic to the patent.
`
`B. Obviousness
`
`
`
`I have been informed and understand that a patent claim can be
`
`considered to have been obvious to a POSITA at the time the application was filed.
`
`This means that, even if all of the requirements of a claim are not found in a single
`
`prior art reference, the claim is not patentable if the differences between the subject
`
`matter in the prior art and the subject matter in the claim would have been obvious
`
`to a POSITA at the time the application was filed.
`
`
`
`I have been informed and understand that a determination of whether a
`
`claim would have been obvious should be based upon several factors, including,
`
`among others:
`
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 10,510,842
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` the level of ordinary skill in the art at the time the application was filed;
`
` the scope and content of the prior art; and
`
` what differences, if any, existed between the claimed invention and the
`prior art.
`
`
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`I have been informed and understand that the teachings of two or more
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`references may be combined in the same way as disclosed in the claims, if such a
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`combination would have been obvious to a POSITA. In determining whether a
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`combination based on either a single reference or multiple references would have
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`been obvious, it is appropriate to consider at least the following factors:
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` whether the teachings of the prior art references disclose known concepts
`combined in familiar ways, which, when combined, would yield
`predictable results;
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` whether a POSITA could implement a predictable variation, and would
`see the benefit of doing so;
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` whether the claimed elements represent one of a limited number of
`known design choices, and would have a reasonable expectation of
`success by a POSITA;
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` whether a POSITA would have recognized a reason to combine known
`elements in the manner described in the claim;
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` whether there is some teaching or suggestion in the prior art to make the
`modification or combination of elements claimed in the patent; and
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` whether the innovation applies a known technique that had been used to
`improve a similar device or method in a similar way.
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`
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`I understand that a POSITA has ordinary creativity, and is not an
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`automaton.
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 10,510,842
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`
`
`I understand that in considering obviousness, it is important not to
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`determine obviousness using the benefit of hindsight derived from the patent being
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`considered.
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`
`
`I understand that prior art to the ’842 Patent includes patents and printed
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`publications in the relevant art that predate the Priority Date of the ’842 Patent.
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`
`
`I understand
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`that certain
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`factors—often called “secondary
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`considerations”—may support or rebut an assertion of obviousness of a claim. I
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`understand that such secondary considerations include, among other things,
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`commercial success of the alleged invention, skepticism of those having ordinary
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`skill in the art at the time of the alleged invention, unexpected results of the alleged
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`invention, any long-felt but unsolved need in the art that was satisfied by the alleged
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`invention, the failure of others to make the alleged invention, praise of the alleged
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`invention by those having ordinary skill in the art, and copying of the alleged
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`invention by others in the field. I further understand that there must be a nexus—a
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`connection—between any such secondary considerations and the alleged invention.
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`I also understand that contemporaneous and independent invention by others is a
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`secondary consideration tending to show obviousness.
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`IV. SUMMARY OF OPINIONS
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`
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`It is my opinion that claims 1-2, 4-10, and 12-18 are disclosed or, at a
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`minimum, rendered obvious by Kawagoe (Ground I).
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 10,510,842
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`
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`It is my opinion that claims 1-3, 5-11, and 13-18 are rendered obvious
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`by Wieczorek in combination with Wolf (Ground II).
`
`
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`It is my opinion that claims 1-2, 4-10, and 12-18 are rendered obvious
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`by Kawagoe in view of Gupta (Ground III).
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`
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`It is my opinion that claims 1-3, 5-11, and 13-18 are rendered obvious
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`by Wieczorek in combination with Wolf and Gupta (Ground IV).
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`
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`It is my opinion that for purposes of this proceeding, the claim terms
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`need not be construed to resolve the prior art issues presented in this Petition.
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`V. OVERVIEW OF THE TECHNOLOGY
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` A Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a
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`transistor that switches from an OFF state to an ON state when a voltage is applied
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`to a gate terminal. Ex. 1008B, 402. In the ON, or active state, current flows from a
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`source to a drain through a channel region (the length of such channel region is
`
`labelled “L” below). The channel region is under the gate and gate oxide, and
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`between the source and drain.
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`
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`Ex. 1008B, FIG. 5-1 (annotations in red);1 id., 298-301, FIGS. 5-2, 6-4. The
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`combination of the source, drain, and channel regions form the active region of a
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`transistor. Ex. 1008B, 299-300 (“The top surface of the [substrate] body consists of
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`active or transistor regions as well as passive or (field) regions. The active regions
`
`are those in which transistor action occurs; i.e., the channel and the heavily doped
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`source and drain regions.”), FIG. 5-2, 382, FIG. 6-8(c), 387, FIG. 6-10; Ex. 1008C,
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`525, FIG. 8-1(e).
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` MOSFETs are characterized by the material used in the source and
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`drain. A MOSFET with source/drain regions made from “p-type” material in such
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`areas (as shown in the figure above, labelled “p+”) is known as a PMOS or p-FET,
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`
`1 All emphases and annotations added unless otherwise noted.
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`while a MOSFET with source/drain regions made from “n-type” material (“n+”) in
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`such areas is known as a NMOS or n-FET. In the mid-1980s, Complementary MOS
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`(CMOS) devices became popular, which have both PMOS (p-FET) and NMOS (n-
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`FET) transistors on the same device. In such devices, the active areas (and associated
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`transistors) are generally formed in regions called “wells,” which have opposite
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`dopant type to the dopants of the source/drain, as illustrated below.
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`
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`Ex. 1008A, FIG. 16-28 (annotations in red).
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`
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`Impurities known as “dopants” are added to the active areas and wells
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`to add charge carriers and tailor the electrical properties of these regions such as their
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`conductivity. Charge carriers can be electrons or holes. Ex. 1008C, 86. When a
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`region is doped with p-type dopants, the holes are majority carriers and the electrons
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`are minority carriers. Ex. 1008C, 86. When a region is doped with n-type dopants,
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`the electrons are majority carriers and the holes are minority carriers. Ex. 1008C, 86.
`
` A “dopant profile” refers to the “map” of concentration of dopants over
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`a doped region and, in certain simplified scenarios, can be expressed as as a function
`
`of depth. For example, a dopant concentration that does not change with depth is a
`
`uniform concentration. A non-uniform dopant concentration that varies for example
`
`with depth, e.g., increases or decreases with depth, is a non-uniform dopant
`
`concentration called “graded.” A graded dopant concentration that peaks at some
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`depth of the doped region(s) instead of at th