EV76C560
`1.3 Mpixels B&W and Color
`CMOS Image Sensor
`
`Datasheet
`Features
`• 1.3 million (1280 x 1024) pixels, 5.3 μm square pixels with micro-lens
`• Optical format 1/1.8"
`• 60 fps@ full resolution
`• Embedded functions:
`– Image Histograms and Context output
`– Sub-sampling / binning
`– Multi-ROI (including 1 line mode)
`– Defective pixel correction
`– PLL with 5 to 50 MHz input frequency range (compatible with dithered
`master clock)
`– High dynamic range capabilities
`– Time to Read improvement (Abort image and Good first image)
`• Timing modes:
`– Global shutter in serial and overlap modes
`– Rolling shutter allowing true CDS readout and global reset
`• Output format 8 or 10 bits parallel plus synchronization
`• SPI controls
`• Control input pins: Trigger, Reset
`• Light control output
`• 3.3 V and 1.8 V power supplies
`
`Performance Characteristics
`• Low power consumption (200 mW)
`• High sensitivity at low light level
`• Operating temperature [-30° to +65°C]
`• Peak QE > 60%
`
`Available Sensor Types
`• B&W
`• Color (Bayer arrangement)
`
`Applications
`• Surveillance IP/CCTV cameras
`• Industrial Machine Vision (Barcode reading)
`• Biometrics/Medical Imaging
`• Automotive Vision
`
`Introduction
`The EV76C560 is a 1.3 million pixel CMOS image sensor designed with e2v's proprietary Eye-On-Si CMOS imaging tech-
`nology. It is suitable for many different types of application where superior performance is required. The innovative pixel
`design offers excellent performance in low-light conditions with an electronic global (true snapshot) shutter, and offers a
`high readout speed at 60 fps in full resolution. Its very low power consumption makes it well suited for battery powered
`applications.
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`1. Typical Performance Data
`
`Table 1-1.
`
`Typical electro-optical performance @ 25°C and 65°C, nominal pixel clock
`
`EV76C560
`
`Parameter
`
`Sensor
`characteristics
`
`Resolution
`
`Image size
`
`Pixel size (square)
`
`Aspect ratio
`
`Max frame rate
`
`Pixel rate
`
`Bit depth
`
`Dynamic range (1)
`
`Qsat
`
`SNR Max
`
`Pixel
`performance
`
`MTF at Nyquist, (cid:79)=550 nm
`Dark signal (2)
`DSNU(2)
`PRNU (3) (RMS)
`Responsivity(2) (4)
`
`Electrical
`interface
`
`Power supplies
`
`Power consumption:
`
` Functional (5)
`Standby
`
`Unit
`
`pixels
`
`mm
`inches
`
`μm
`
`fps
`
`Mpixels / s
`
`bits
`
`dB
`
`ke-
`
`dB
`
`%
`
`LSB10/s
`LSB10/s
`%
`
`LSB10/(Lux.s)
`V
`
`mW
`μW
`
`Typical value
`
`1280 (H) (cid:117) 1024 (V)
`
`6.9 (H) (cid:117) 5.5 (V) - 8.7 (diagonal)
`(cid:124) 1/1.8
`5.3 (cid:117) 5.3
`
`5 / 4
`
`60 @ full format
`
`90 -> 120
`
`@ TA 25°C
`>62
`
`41
`
`24
`
`6
`
`10
`
`12
`
`50
`
`@ TA 65°C
`>57
`
`39
`
`420
`
`116
`
`<1
`
`6600
`
`3.3 & 1.8
`
`< 200 mW
`180
`
`1.
`2.
`3.
`4.
`5.
`
`In electronic rolling shutter (ERS) mode.
`Min gain, 10 bits.
`Measured @ Vsat/2, min gain.
`3200K, window without AR coating, IR cutoff filter BG38 2 mm.
`@ 60 fps, full format, with 10 pF on each output.
`
`Figure 1-1.
`
`Spectral response and quantum efficiency
`
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`2. Sensor Overview
`
`Figure 2-1.
`(cid:3)
`
`Block diagram
`
`EV76C560
`
`D ATA_CLK
`
`FEN
`LEN
`
`FLO
`
`D EFE CT
`CO R RECT ION
`
`BIN NI NG
`
`10 t o 8 bits
`
`PATTERN
`GEN ER ATO R
`
`MATRIX
`U sefu l 1 280x
`10 24
`
`DECODER
`
`LINE
`
`A DC ( 10-BITS)
`
`PGA
`
`D ark correcti on
`
`CLAM P
`+
`DIGITAL
`GAINS
`
`C LK _AD C
`
`H IS TOGRA M
`
`S PI
`
`M UX OU T
`
`CONTEXT
`
`TIMING GE NER ATOR
`+
`POWER
`MAN AGEMEN T
`
`CLK _CTRL
`
`CL OCK GE NE RATOR
`
`PLL
`
`INT ERNAL
`OSCILLA TOR
`
`CLK_C HAIN
`
`D ATA<9 :0>
`
`A DC_REF_1
`
`A DC_REF_2
`
`CSN
`M ISO
`
`M OSI
`S CK
`TRIG
`RE SE TN
`
`CL K_FIX
`
`CLK _R EF
`
`Legen d:
`
`C LK_ADC domain
`
`CLK_C TR L do ma in
`
`CL K_ CHA IN dom ain
`
`Detailed descriptions of the I/O signals and blocks are given in the datasheet sections listed in Table 2-1
`See Section 21. for the device pinout information.
`
`Table 2-1.
`
`Quick reference table for block diagram
`
`Signal name
`
`I/O Description
`
`ADC_REF1&2
`
`CSN
`
`I
`
`I
`
`ADC reference voltages
`
`SPI chip select
`
`Reference
`
`Section 5.2
`
`List of blocks
`
`Matrix
`
`ADC + PGA
`
`Reference
`
`Section 4.
`
`Section 5.
`
`O
`
`SPI data output
`
`Clamp + digital gain
`
`Section 6. & 7.
`
`MISO
`
`MOSI
`
`SCK
`
`TRIG
`
`CLK_REF
`
`CLK_FIX
`
`RESETN
`
`DATA<9:0>
`
`FEN
`
`LEN
`
`FLO
`
`DATA_CLK
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`O
`
`O
`
`O
`
`O
`
`O
`
`SPI data input
`
`SPI clock
`
`Trigger input
`
`Reference clock input
`
`Fixed clock input
`
`Sensor reset
`
`10-bit data output bus
`
`Section 17.
`
`Section 18.
`
`Section 14.
`
`Section 18.
`
`Defect correction
`
`Binning
`
`Histogram
`
`10->8 bits
`
`Context
`
`Mux out
`
`Timing and power management
`
`Vertical sync output
`
`Section 19.
`
`Clock generator
`
`Horizontal sync output
`
`Pattern generator
`
`Illumination control output
`
`Section 19.6
`
`SPI
`
`Output clock
`
`Section 8.
`
`Section 9.
`
`Section 10.
`
`Section 11.
`
`Section 12.
`
`Section 13.
`
`Section 14.
`
`Section 15.
`
`Section 16.
`
`Section 17.
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`EV76C560
`
`3. Standard Configuration
`
`3.1
`
`Sensor Settings
`The static configuration required to allow image capture is as follows:
`
`• All ground pins connected.
`• All power supply pins with the same name connected together.
`• SPI pins connected to the host controller.
`• 1.8 V pins and 3.3 V pins powered-on.
`• Input clock driving the CLK_REF input pin.
`• RESETN pin held at high level after the power-on sequence. See Section 18.1.1
`• STANDBY state is deactivated by writing 0 in the stdby_rqst bit in the <reg_ctrl_cfg> register. See
`Section 17.3.8
`• Image capture is triggered by a high level on the TRIG pin or setting the trig_rqst bit in the
`<reg_ctrl_cfg> register. See Section 17.3.8
`For improved performance, VDD33A and VDD18A must be noise-free. The best way to decouple
`VDD33A and to increase the power supply rejection ratio is to use a linear regulator dedicated to the
`image sensor. To prevent noise on VDD18A an inductor can be used.
`
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`3.2
`
`Application Information
`
`Figure 3-1. Required external components
`
`EV76C560
`
`It is recommended to use X7R for all the 100 nF capacitors.
`
`Reset pin has an internal pull-up.
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`3.3
`
`Electrical Levels
`
`Table 3-1.
`
`DC Characteristics @ 25°C
`
`EV76C560
`
`Min
`
`3.15
`
`1.6
`
`1.6
`
`Parameter
`
`Symbol
`
`Analog power supply relative to GND
`
`VDD33A
`
`Digital power supply relative to GND
`
`VDD18D
`
`Analog power supply relative to GND
`Power supply consumption (1)
`
`Supply current at 60 fps (VDD33A pin)
`
`Supply current at 60 fps (VDD18A pin)
`
`Supply current at 60 fps (VDD18D pin)
`
`VDD18A
`
`P
`
`IVDD33A
`IVDD18A
`IVDD18D
`
`Standby supply current on VDD33A
`pin
`
`Standby supply current on VDD18A
`pin
`
`Standby supply current on VDD18D
`pin (2)
`
`IDLE supply current on VDD33A pin
`
`IDLE supply current on VDD18A pin
`
`IDLE supply current on VDD18D pin
`
`IVDD33A(STBY)
`
`IVDD18A(STBY)
`
`IVDD18D(STBY)
`
`IVDD33A(IDLE)
`IVDD18A(IDLE)
`IVDD18D(IDLE)
`
`CMOS in/out
`
`Input voltage low level
`
`Input voltage high level
`Input pin capacitance (3)
`
`Output voltage low level
`
`Output voltage high level
`Output current @ VOH (4)
`Output current @ VOL(4)
`Input leakage current (5)
`ADC_REF current (6)
`
`VIL
`VIH
`CIN
`VOL1
`VOH1
`IOH
`IOL
`IL
`IADC_REF
`
`0.7 VDD18
`
`VDD18-0.55
`-10
`
`-1
`
`Value
`
`Typ
`
`3.3
`
`1.8
`
`1.8
`
`190
`
`20
`
`25
`
`30
`
`0
`
`0
`
`50
`
`6
`
`0
`
`7
`
`4
`
`100
`
`Max
`
`3.45
`
`2
`
`2
`
`100
`
`0.3 VDD18
`
`0.55
`
`10
`
`1
`
`Unit
`
`V
`
`V
`
`V
`
`mW
`
`mA
`
`mA
`
`mA
`
`μA
`
`mA
`
`mA
`
`mA
`
`V
`
`V
`
`pF
`
`V
`
`V
`
`mA
`
`mA
`
`μA
`
`μA
`
`1.
`2.
`3.
`4.
`5.
`6.
`
`Digital output loads =10 pF
`IVDD18D(STDBY) with SPI on, without communication and without CLK_REF input.
`CLCC48 package
`On all output pins
`On all digital input pins
`On ADC_REF pins
`
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`EV76C560
`
`4. Matrix
`
`4.1
`
`Useful Area Definition
`The useful area is 1280 (cid:117) 1024 pixels as shown in Figure 4-1.
`
`19 optically shielded reference lines to allow the black level adjustment.
`
`6 dummy illuminated pixels surround the useful area.
`
`max with dummy = 1036
`
`Minimum offset in column = 0
`Minimum offset in line = 0
`
`FEN
`
`19 reference lines
`
`(0,0)
`
`(6,6)
`
`USEFUL 1280 x 1024
`
`(1285,1029)
`
`(1291,1035)
`
`Max with dummy = 1292
`
`First pixel out
`
`Horizontal active pixels
`Number depending on binning & sub-sampling
`
`Figure 4-1.
`
`Area description
`
`First line out
`
`Vertical active lines
`
`Depending on binning &
`
`sub-sampling
`
`Time
`
`Len
`
`D (9 :0)
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`EV76C560
`
`4.2
`
`CFA (Color Filter Array)
`The following CFA types are implemented:
`
`• Monochrome
`• RGB Bayer filter
`Other types are available on request.
`
`As CFA choice does not implied a silicon hardware change but only post-process, to allow good choice
`of binning, subsampling models and color gains use the sensor must be configured by setting 1 in
`color_en when a color sensor is used. Note that image size depends on this factor. See Section 4.5.3.1.
`
`Table 4-1.
`
`Color of first pixel using the flip functions (depends on H&V offset parities)
`
`RoiX_0l_1 / RoiX_0c_1
`
`Flip H
`
`Flip V
`
`Odd/Odd
`
`Odd/Even
`
`Even/odd
`
`Even/Even
`
`N
`
`N
`
`O
`
`O
`
`N
`
`O
`
`N
`
`O
`
`Red
`
`Green Red
`
`Green Blue
`
`Blue
`
`Green Blue
`
`Green Red
`
`Blue
`
`Red
`
`Red
`
`Blue
`
`Green Red
`
`Green Blue
`
`Blue
`
`Green Blue
`
`Green Red
`
`Red
`
`RoiX_0l stands for ROI1_0l_1, Roi2_0l_1, Roi3_0l_1 & Roi4_0l_1. See Section 17.3.11, 17.3.12,
`17.3.13, and 17.3.14 respect
`
`RoiX_0c stands for Roi1_0c_1, Roi2_0c_1, Roi3_0c_1 & Roi4_0c_1. Section 17.3.11, 17.3.12, 17.3.13,
`and 17.3.14 respectively
`
`It is recommended to keep:
`
`• Roi_W_1 + Roi_0c_2 even
`• Roi_h_1 + Roi_0l_2 even
`Flip H & Flip V are under roi_flip_h & roi_flip_v control. See <reg_miscel2> in Section 17.3.4
`
`4.3
`
`Pixels
`
`The matrix is composed of five transistor (5T) pixels. This structure supports either global shutter (GS)
`mode or electronic rolling shutter (ERS) mode (Section 18.2).
`
`4.4
`
`Lens CRA (Chief Ray Angle) compensation.
`In order to better focus the light rays on the photodiode, the EV76C560 micro lenses are radially shifted
`to match the exit angles due to the external application lens. This results in improved efficiency and
`reduced corner shading.
`This shift is linearly applied from center (0 shift) to corner ((cid:68)(cid:3)angle).
`
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`EV76C560
`
`(cid:68) is the corner CRA (Chief Ray Angle) defined as a mean value of the telecentricity of optics lenses that
`would be used with the sensor.
`
`The sensor, optimized for a corner CRA of 12°, can be used with a range of telecentricity from 5°
`to 20° (estimated for fnumber f#/1.2).
`
`Figure 4-2. Microlens Shifting
`
`(cid:68)(cid:3)
`
`MICROLENS
`
`Photodiode
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`Figure 4-3.
`
`Lens CRA overview
`
`EV76C560
`
`Photodiode
`Microlens
`
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`EV76C560
`
`4.5
`
`Region Of Interest (ROI)
`
`4.5.1
`
`Flip Functions
`Flip functions are available to allow the application to use any type of lens (with or without mirror). The
`flip functions are controlled by programming the roi_flip_h and roi_flip_v bitfields in the <reg_miscel2>
`register. See Section 17.3.4. The ROI is applied on the flipped image.
`
`The shielded lines for dark reference are always read first (except in expanded ROI mode selected by
`the roi_expanded bit in the <reg_miscel2> register (see Section 17.3.4) when whole lines may be read.
`
`Figure 4-4.
`
`Flip effects
`
`NO FLIP
`
`FLIP H
`
`FLIP H&V
`
`FLIP V
`
`ROI
`
`4.5.2
`
`ROI Definition
`All ROIs are defined in relation to the matrix and useful pixel area (as shown in Figure 4-1). The ROIs are
`defined before sub-sampling, defect correction and binning.
`
`If a flip effect is used, ROI selection is done after the flip.
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`EV76C560
`
`4.5.3
`
`Sub-Sampling and Windowing
`• The sub-sampling function causes the sensor to read only 8 pixels over the selected factor. For
`example, a sub-sampling factor of 8 over 16 means that the sub-sampling ratio is 1:2. For color
`sensors, the algorithm is more complicated due to the Bayer organization.
`Sub-sampling is programmable with a ratio 1 to 32 in steps of 0.125. Different sub-sampling factors
`can be defined for horizontal and vertical directions. They are programmable using SPI commands:
`roiX_subs_v and roiX_subs_h in <reg_roiX*> (where X* is the number of the ROI 1, 2, 3 or 4
`registers group) see Section 17.3.11, 17.3.12, 17.3.13, and 17.3.14 respectively.
`• Windowing defines the size and position of the ROI. Windowing is defined in two dimensions:
`horizontal and vertical. The minimum width of the window is 16 columns and the minimum height is 1
`line. The user has to define the height, width and offsets of the ROI through the SPI control bus for
`each ROI used. (See Section 4.5.4).
`Windowing, sub-sampling and then binning are possible on the same image.
`
`Figure 4-5. Combination of windowing, sub-sampling and binning example for a B&W image.
`With Binning
`Sub-sampling
`
`ROI
`
`Useful Area
`Full Area
`
`Without Binning
`
`Figure 4-6.
`
`Sub-sampling example
`
`1 2 3
`
`987654
`
`10
`
`11
`
`12 13 14
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23 24 25
`
`26
`
`27
`
`28
`
`29
`
`30
`
`31
`
`32
`
`1 2 3
`
`654
`
`987
`
`With an 8/30 sub-sampling factor only these pixels (or lines) will be read:
`
`• On the first group of 30 pixels: 1, 4, 8, 12, 16, 19, 23, 27
`• On the second group of 30 pixels: 31, 34, 38…
`• On the third group of 30 pixels: 61…
`Roughly, the sub-sampled image format will be multiplied by 8/30=1/3.75. For more precise calculation
`of the output image size the following formulas must be used.
`
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`

`4.5.3.1
`
`Calculating the Image Output Size
`Image output sizes are determined by the following equations depending on:
`
`EV76C560
`
`• B&W or color version (color_en in <reg_miscel2> see Section 17.3.4,
`• Sub-sampling factor (roiN_subs_v and roiN_subs_h in <reg_roiN*> see Section 17.3.11, 17.3.12,
`17.3.13, and 17.3.14 respectively),
`• Defect correction activation (roi_ddc_en in <reg_chain_cfg> see Section 17.3.7 ),
`• Binning activation (roiN_binning_en in <reg_chain_cfg> see Section 17.3.7.
`If roiN_binning_en = 0 AND color_en = 0
`
`For ROI 1:
`
`ROI_width = INT
`
`8 (cid:117) roi1_w_1
`roi1_subs_factor + 8
`
`+ INT
`
`8 (cid:117) roi1_w_2
`roi1_subs_factor + 8
`
`For ROI 2, 3 and 4:
`
`ROI_width = INT
`
`8 (cid:117) roiN_w
`roiN_subs_factor + 8
`
`If (roiN_binning_en = 1 AND color_en = 0) OR (roiN_binning_en = 0 AND color_en = 1)
`
`For ROI 1:
`
`ROI_width = 2 (cid:117)(cid:3)
`
`INT
`
`4 (cid:117) roi1_w_1
`roi1_subs_factor + 8
`
`+ INT
`
`4 (cid:117) roi1_w_2
`roi1_subs_factor + 8
`
`For ROI 2, 3 and 4:
`
`ROI_width = 2 (cid:117)(cid:3)INT
`
`4 (cid:117) roiN_w
`roiN_subs_factor + 8
`
`If roiN_binning_en = 1 AND color_en = 1
`
`For ROI 1:
`
`ROI_width = 4 (cid:117)(cid:3)
`
`INT
`
`2 (cid:117) roi1_w_1
`roi1_subs_factor + 8
`
`+ INT
`
`2 (cid:117) roi1_w_2
`roi1_subs_factor + 8
`
`For ROI 2, 3 and 4:
`
`ROI_width= 4 (cid:117)(cid:3)INT
`
`2 (cid:117) roiN_w
`roiN_subs_factor + 8
`
`Then, width_out is:
`
`width_out = ROI_width – 4 (cid:117)(cid:3)ddc_en
`2roiN_binning_en
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`EV76C560
`
`If roiN_binning_en = 0 AND color_en = 0
`
`For ROI 1
`
`ROI_height = INT
`
`8 (cid:117) roi1_h_1
`roi1_subs_factor + 8
`
`+ INT
`
`8 (cid:117) roi1_h_2
`roi1_subs_factor + 8
`
`For ROI 2, 3 and 4:
`
`ROI_height = INT
`
`8 (cid:117) roiN_h
`roiN_subs_factor + 8
`
`If (roiN_binning_en = 1 AND color_en = 0) OR (roiN_binning_en = 0 AND color_en = 1)
`
`For ROI 1
`
`ROI_height = 2 (cid:117)(cid:3)
`
`INT
`
`4 (cid:117) roi1_h_1
`roi1_subs_factor + 8
`
`+ INT
`
`4 (cid:117) roi1_h_2
`roi1_subs_factor + 8
`
`For ROI 2, 3 and 4:
`
`ROI_height = 2 (cid:117)(cid:3)
`INT
`
`4 (cid:117) roiN_h
`roiN_subs_factor + 8
`
`If roiN_binning_en = 1 AND color_en = 1
`
`For ROI 1:
`
`ROI_height = 4 (cid:117)(cid:3)
`
`INT
`
`2 (cid:117) roi1_h_1
`roi1_subs_factor + 8
`
`+ INT
`
`2 (cid:117) roi1_h_2
`roi1_subs_factor + 8
`
`For ROI 2, 3 and 4:
`
`ROI_height = 4 (cid:117)(cid:3)
`
`INT
`
`2 (cid:117) roiN_h
`roiN_subs_factor + 8
`
`Then, height_out is:
`height_out = ROI_height – 4 (cid:117)(cid:3)ddc_en
`2roiN_binning_en
`
`Notes:
`
`• INT( ) takes the integer part of the division result.
`• N stands for ROI index (1, 2, 3 or 4).
`• If defect correction is active, the minimum ROI size is 5; defect correction must be disabled for smaller
`ROI size.
`
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`

`EV76C560
`
`4.5.4
`
`Multi-ROI
`The multi-ROI offers two different and separate modes:
`
`• MIMR (Multiple Integration Multiple ROI) mode allows the user to define an acquisition cycle
`comprising 1 to 4 ROI cycle(s) (see roi_max_id in <reg_chain_cfg> in Section 17.3.7).
`• SIMR (Single Integration Multiple ROI) mode acts on the first ROI of the multi-ROI cycle only,
`allows 1, 2 or 4 areas of interest to be acquired within the same integrated image. In SIMR mode, the
`sensor outputs only the configured zones and concatenates them to form a single image (see Section
`4.5.4.2).
`Each ROI has its own specific parameters (see Table 4-2) and parameters that are common to all ROIs
`(see Table 4-3).
`
`Table 4-2.
`
`ROI-specific parameters
`
`Parameter
`
`Description
`
`ROI1
`
`ROI2
`
`ROI3
`
`ROI4
`
`Register bitfield names
`
`ROI
`Configuration
`
`Defines the ROI
`dimensions and
`position in the
`total field of view.
`
`For each ROI two
`integration times
`have to be
`defined, one in
`number of lines
`and one in sub-
`line times.
`
`Integration
`times
`
`Analog and
`digital gains
`
`Vertical and
`horizontal
`sub-sampling
`factors
`
`roi1_0l_1
`roi1_h_1
`roi1_0c_1
`roi1_w_1
`roi1_0l_2
`roi1_h_2
`roi1_0c_2
`roi1_w_2
`in <reg_roi1*>,
`see Section
`17.3.11
`
`roi1_t_int_ll
`roi1_t_int_clk
`in <reg_roi1*>,
`see Section
`17.3.11
`
`roi2_0l_1
`roi2_h_1
`roi2_0c_1
`roi2_w_1
`in <reg_roi2*>,
`see Section
`17.3.12
`
`roi3_0l_1
`roi3_h_1
`roi3_0c_1
`roi3_w_1
`in <reg_roi3*>,
`see Section
`17.3.13
`
`roi4_0l_1
`roi4_h_1
`roi4_0c_1
`roi4_w_1
`in <reg_roi4*>,
`see Section
`17.3.14
`
`roi2_t_int_ll
`roi2_t_int_clk
`in <reg_roi2*>,
`see Section
`17.3.12
`
`roi3_t_int_ll
`roi3_t_int_clk
`in <reg_roi3*>,
`see Section
`17.3.13
`
`roi4_t_int_ll
`roi4_t_int_clk
`in <reg_roi4*>,
`see Section
`17.3.14
`
`roi1_ana_gain
`roi1_dig_gain in
`<reg_roi1*>, see
`Section 17.3.11
`
`roi2_ana_gain
`roi2_dig_gain in
`<reg_roi2*>, see
`Section 17.3.12
`
`roi3_ana_gain
`roi3_dig_gain in
`<reg_roi3*>, see
`Section 17.3.13
`
`roi4_ana_gain
`roi4_dig_gain in
`<reg_roi4*>, see
`Section 17.3.14
`
`roi1_subs_v
`roi1_subs_h
`in <reg_roi1*>,
`see Section
`17.3.11
`
`roi2_subs_v
`roi2_subs_h
`in <reg_roi2*>,
`see Section
`17.3.12
`
`roi3_subs_v
`roi3_subs_h
`in <reg_roi3*>,
`see Section
`17.3.13
`
`roi4_subs_v
`roi4_subs_h
`in <reg_roi4*>,
`see Section
`17.3.14
`
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`
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`

`EV76C560
`
`Table 4-2.
`
`ROI-specific parameters (Continued)
`
`Parameter
`
`Description
`
`ROI1
`
`ROI2
`
`ROI3
`
`ROI4
`
`Register bitfield names
`
`Binning
`factor
`
`Repetition
`count
`
`Wait time
`
`Binning is
`performed after
`the sub-sampling
`if this is used.
`Each ROI can
`have its own
`binning factor.
`See Section 9.
`
`Each ROI will be
`repeated several
`times before
`reading the next
`ROI.
`
`Wait time after the
`end of the last
`ROI repetition
`(see Figure 4-7
`Multi-ROI cycle).
`
`roi1_binning_en
`in
`<reg_chain_cfg>,
`see Section 17.3.7
`
`roi2_binning_en
`in
`<reg_chain_cfg>,
`see Section 17.3.7
`
`roi3_binning_en
`in
`<reg_chain_cfg>,
`see Section 17.3.7
`
`roi4_binning_en
`in
`<reg_chain_cfg>,
`see Section 17.3.7
`
`roi1_rep_nb
`in <reg_roi1*>,
`see Section
`17.3.11
`
`roi2_rep_nb
`in <reg_roi2*>,
`see Section
`17.3.12
`
`roi3_rep_nb
`in <reg_roi3*>,
`see Section
`17.3.13
`
`roi4_rep_nb
`in <reg_roi4*>,
`see Section
`17.3.14
`
`roi1_t_wait_ext
`in <reg_roi1*>,
`see Section
`17.3.11
`
`roi2_t_wait_ext
`in <reg_roi2*>,
`see Section
`17.3.12
`
`roi3_t_wait_ext
`in <reg_roi3*>,
`see Section
`17.3.13
`
`roi4_t_wait_ext
`in <reg_roi4*>,
`see Section
`17.3.14
`
`All the used ROIs use these common parameters:
`
`Table 4-3.
`
`ROI common parameters
`
`Parameter
`
`Description
`
`The binning result may be divided by 1, 2 or 4 to
`either keep the maximum amount of information
`or reduce the noise.
`(see Figure 4-4: Flip effect)
`
`Depends on MIMR, SIMR or High dynamic
`configuration. See Section 4.5.4.1, Section
`4.5.4.2 and Section 4.5.4.3
`
`Binning factor divider
`
`Flip configuration
`
`Readout mode
`
`Digital color gains (For
`color sensor)
`
`Wait time at the end of
`each frame
`
`Line length
`
`Clamp configuration and
`offsets
`
`16
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`Register bitfield names
`
`binning_div_factor in <reg_chain_cfg>,
`see Section 17.3.7
`
`roi_flip_h and roi_flip_v in
`<reg_miscel2>, see Section 17.3.4
`
`roi_readout_mode , see Section 17.3.8
`
`gb_dig_gain; gr_dig_gain; in
`<reg_dig_gain_gb_gr>, see Section 17.3.16
`b_dig_gain; r_dig_gain in
`<reg_dig_gain_b_r>, see Section 17.3.15
`
`roi_t_wait, see Section 17.3.10
`
`line_length, see Section 17.3.1
`
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`

`4.5.4.1
`
`Multiple Integration (MIMR) Mode Configuration
`
`Figure 4-7. Multi-ROI cycle in MIMR mode
`
`(cid:3)
`
`EV76C560
`
`ROI 1
`
`x N1
`
`Wait 1
`
`ROI 2
`
`x N2
`
`1 ROI
`
`MIMR cycle using
` 1 to 4 ROI
`
`Wait 2
`
`2 ROI
`
`Wait 4
`
`ROI 4
`
`x N4
`
`Wait 3
`
`ROI 3
`
`x N3
`
`4 ROI
`
`3 RO I
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`

`EV76C560
`
`4.5.4.2
`
`Single Integration (SIMR) Mode Configuration
`
`Figure 4-8.
`
`SIMR parameters
`
`roi1_0c_1
`roi1_w_1
`
`roi1_w_2 =0
`
`roi1_0c_1
`roi1_w_1
`
`roi1_0c_2
`roi1_w_2
`
`roi1_0l_1
`
`roi1_h_1
`
`roi_1_1
`
`roi_1_1
`
`roi_1_2
`
`1 ROI
`
`2 ROI
`
`roi1_h_2=0
`
`roi1_0l_1
`
`roi1_h_1
`
`roi1_0l_2
`
`roi_1_1
`
`roi_1_1
`
`roi_1_2
`
`roi1_h_2
`
`roi_2_1
`
`2 ROI
`
`roi_2_1
`
`roi_2_2
`
`4 ROI
`
`All the ROI 1 registers are described in Section 17.3.11.
`
`• If the ROI_1_2 width and ROI_2_1 height are null, only ROI_1_1 is read. The user has to choose:
`– ROI_1_1 horizontal (roi1_0c_1) and vertical (roi1_0l_1) offsets.
`– ROI_1_1 horizontal (roi1_w_1) and vertical (roi1_h_1) dimensions.
`• If the ROI_1_2 width is greater than 0 and ROI_2_1 height is null, only ROI_1_1 and ROI_1_2 are
`read. The user has to choose:
`– ROI_1_1 horizontal (roi1_0c_1) and vertical (roi1_0l_1) offsets.
`– ROI_1_1 horizontal (roi1_w_1) and vertical (roi1_h_1) dimensions.
`– ROI_1_2 horizontal (roi1_0c_2) offset. (ROI_1_2 vertical offset = ROI_1_1).
`– Horizontal (roi1_w_2) width (ROI_1_2 height = ROI_1_1).
`• If the ROI_1_2 width is null and ROI_2_1 height is greater than 0, only ROI_1_1 and ROI_2_1 are
`read. The user has to choose:
`– ROI_1_1 horizontal (roi1_0c_1) and vertical (roi1_0l_1) offsets.
`– ROI_1_1 horizontal (roi1_w_1) and vertical (roi1_h_1) dimensions.
`– ROI_2_1 vertical (roi1_0l_2) offset. (ROI_2_1 horizontal offset = ROI_1_1).
`
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`
`

`

`EV76C560
`
`– ROI_2_1 height (roi1_h_2) (ROI_2_1 width is the same as ROI_1_1).
`• If the ROI_1_2 width and ROI_2_1 height are greater than 0, then 4 ROI_1_1, ROI_2_1, ROI_1_2
`and ROI_2_2 are read. The user has to choose:
`– ROI_1_1 horizontal (roi1_0c_1) and vertical (roi1_0l_1) offsets.
`– ROI_1_1 horizontal (roi1_w_1) and vertical (roi1_h_1) dimensions.
`– ROI_2_1 ROI_2_2 vertical (roi1_0l_2) offset and (roi1_h_1) height.
`– ROI_1_2 horizontal (roi1_0c_2) offset and (roi1_w_2) width.
`
`Figure 4-9. ROI output for the "4 ROI" configuration
`
`When using the defect correction (roi_ddc_en = 1) there is:
`
`• A 4-column (or 2 if binning function is enabled) black border between ROI_1_1 and ROI_1_3 and
`ROI_1_2 and ROI_1_4.
`• A 4-line (or 2 if binning function is enabled) black border between ROI_1_1 and ROI_1_2 and
`ROI_1_3 and ROI_1_4.
`
`4.5.4.3
`
`High Dynamic Range Configuration
`A special MIMR configuration using two integration times can be used to provide high dynamic images.
`
`The first integration time image followed by a second integration image are combined without any image
`loss. For example:
`
`• Image 1 with a short integration time
`• Image 2 with N time longer integration time
`• A computed image may be calculated by summing image 2 + [image 1 with each of its pixel values
`multiplied by N]
`Note that due to the 60 fps maximum frame rate a true 30 fps output can be achieved.
`
`In this mode only two ROIs are used. They must have the same:
`
`• Position and dimensions.
`• Binning
`• Sub-sampling factor
`• Repetition factor (=1)
`• ROI mode (SIMR must not be used)
`To prevent motion distortion it is recommended to perform the short integration time first.
`
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`
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`
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`

`EV76C560
`
`Figure 4-10. Dual integration time mode for high dynamic
`High dynamic image
`
`Integration 1
`
`Readout 1
`
`Integration 2 Readout 2
`
`Integration 3
`
`Readout 3
`
`In GS
`
`Integration 1
`
`Readout 1
`
`Integration 2 Readout 2
`
`In ERS
`
`Time
`
`20
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`
`

`

`EV76C560
`
`5. 10-Bit ADC
`
`5.1
`
`Analog Gain
`Digital conversion is done by a high speed 10-bit column ADC. All the pixel values of the same line are
`converted in parallel.
`
`The analog gain is done by a slope adjustment. There are 8 available values. These values are program-
`mable via SPI. Each ROI has its own analog gain:
`
`• roi1_ana_gain in <reg_roi1*> for ROI 1 (see Section 17.3.11)
`• roi2_ana_gain in <reg_roi2*> for ROI 2 (see Section 17.3.12)
`• roi3_ana_gain in <reg_roi3*> for ROI 3 (see Section 17.3.13)
`• roi4_ana_gain in <reg_roi4*> for ROI 4 (see Section 17.3.14)
`
`Figure 5-1.
`
`Principle of the column ADC
`
`Counter +
`Slope
`
`Column 1
`Conversion
`
`Column 2
`Conversion
`
`Column 3
`Conversion
`
`Column N
`Conversion
`
`ADC schematic diagram
`
`10
`
`10
`
`Latch
`
`RAM
`
`R
`
`W
`
`Reset
`l
`l
`
`+ -
`
`COM
`
`Signal
`
`10
`
`S/H
`
`Pixel
`
`Pixel
`
`10 bits
`
`Figure 5-2.
`(cid:3)
`
`A DC_CLK
`
`Start slope
`
`Slope
`Generator
`
`Reset
`
`Write
`
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`
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`

`EV76C560
`
`5.2
`
`External Resistor Choice
`The ADC gain value is set through an external resistor connected between ADC_REF_1 and
`ADC_REF_2 pins. An internal protection against a short circuit between these two pins is included in the
`design.
`
`REXT =
`
`K
`CLK_ADC
`
`– 80
`
`where K = 1.94 (cid:117) 1012, CLK_ADC is in Hertz and REXT is in Ohms.
`With a 114 MHz ADC clock, the resistor value is 16.9 k(cid:58)(cid:17)
`
`5.3
`
`Analog Gain Tolerances
`
`Table 5-1.
`
`ADC gain tolerances
`
`1
`
`89.09
`
`Precision
`
`1.5
`
`59.09
`
`0.5%
`
`2
`
`44.18
`
`1%
`
`3
`
`29.64
`
`1%
`
`4
`
`22.30
`
`1%
`
`6
`
`14.90
`
`1
`
`8
`
`11.27
`
`2%
`
`6. Clamp and Offset Adjustment
`The purpose of the automatic black level adjustment function (or clamp) is to cancel:
`
`• The offset due to pixel dark current (offset variable with temperature and integration time).
`• The analog chain offset (mainly due to comparator offset).
`The black level adjustment is active up to 65 °C with 200 ms integration time.
`
`Black level adjustment can be automatic or manual. This is selected by the clamp_auto_en bit in the
`<reg_miscel2> register. See Section 17.3.4
`
`In order to compensate possible differences in dark current generation between masked pixels and use-
`ful pixels, the automatic black level correction works as follows:
`
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`

`

`Figure 6-1. Clamp principle
`
`Measurement of shielded pixel
`black level @ Tint = tint image
`
`Pixel level
`
`EV76C560
`
`2
`
`3
`
`Slope=
`Dark signal of
`shielded pixels
`
`Slope =
`Dark signal of
`useful pixels
`
`Black level of shielded
`pixels at Tint = 0
`
`Electronic offset does
`not depend on Tint
`
`1
`
`0
`
`ESTIMATED black level of useful pixels
` @ Tint = Tint image
`
`Tint
`
`Tint image
`
`For each frame acquisition:
`
`1. A first measurement is taken on a shielded pixel with a very short integration time (fixed to the
`minimum possible time) to determine the hardware offset of the acquisition chain (chain_offset).
`2. A second measurement is taken to determine the dark signal mean value of a shielded pixel for
`the configured integration time (shld_pix_level).
`3. The dark signal of a useful pixel is deduced from these 2 measurements and from the ratio
`between useful and shielded pixels (V0_ratio). This ratio is configurable via the v0_gain bit field
`in the <reg_clamp_cfg> register. See Section 17.3.18.
`
`Useful dark signal = (shielded pixel level - chain offset) (cid:117) V0_ratio + chain offset
`
`A lock mechanism guarantees a constant correction offset as long as the difference between the new
`correction offset and the current correction is less than a threshold configurable by clamp_lock_th in
`<reg_clamp_cfg> see Section 17.3.18. This mechanism is necessary to ensure offset stability during a
`video stream. It can be bypassed using clamp_lock_en in <reg_clamp_cfg>, see Section 17.3.18.
`
`Offset can be adjusted using either clamp_add_offset (if clamp_auto_en = '1' in <reg_miscel2>) or
`clamp_manual_offset (if clamp_auto_en = '0' in <reg_miscel2>) in <reg_clamp_offset>, see Section
`17.3.17.
`
`The flag_dig_cor flag in the <fb_status> register indicates if a digital correction is needed or not, see
`Section 17.3.23.
`
`If the analog correction allowed by <max_offset> is saturated, a digital correction can be activated by
`setting <dig_cor_en>.
`
`If <dig_cor_en> = 1 and analog offset is saturated, then the maximum data output level will be limited.
`
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`
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`
`

`

`Digital and analog offsets are output in two feedback bitfields fb_ana_offset and fb_dig_offset in
`<fb_clamp>, see Section 17.3.22.
`
`EV76C560
`
`Figure 6-2. Clamp algorithm
`
`If clamp_auto_en = 0
`
`Yes
`
` No
`
`Compute new_offset
`
`Select current_offset according to ROI id
`
`No
`
`If |new_offset -
`current_offset| >
`clamp_lock_th
` Or
`If clamp_lock_en = 0
`
` Yes
`current_offset = new_offset
`
`If current_offset >
`max_offset
`
` No
`ana_offset = current_offset
`flag_dig_cor = 0
`
`current_offset = clamp_manual_offset
`
`Yes
`
`Yes
`
`ana_offset_po = clamp_max_offset
`flag_dig_cor = 1
`
`If dig_cor_en = 0
`
` No
`
`dig_offset = 0
`
`dig_offset = current_offset - ana_offset
`
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`
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`

`EV76C560
`
`7. Digital Gain
`This block applies one global gain followed by four digital gains (for the Bayer or WRGB CFA structures)
`configurable by 8-bit SPI registers.
`
`In B&W products, only the global gain is used.
`
`To allow good precision with low gains the 8-bits for programming the digital gain are used as follows:
`
`• The 2 MSB are used for precision P
`• The 6 LSB are used to control the gain G (from 0 to 63)
`• The ROIX digital gains (roiX_dig_gain) follow this rule:
`
`Gain = 2P (cid:117) 1 +
`
`G
`64
`• For P=0 Gain varies from 1 to 1.98 in steps of 0.015
`• For P=1 Gain varies from 2 to 3.97 in steps of 0.031
`• For P=2 Gain varies from 4 to 7.94 in steps of 0.062
`• For P=3 Gain varies from 8 to 15.88 in steps of 0.125
`In color products, the four digital gains can be used to balance the four color channels (blue, green blue,
`green red and red):
`
`• The 2 MSB are used for precision P
`• The 6 LSB are used to control the gain G (from 0 to 63)
`• The four digital color gains (gb_dig_gain; gr_dig_gain; b_dig_gain; r_dig_gain) follow this rule:
`
`Gain = 2P –2(cid:3)(cid:117) 1 +
`
`G
`64
`
`• For P=0 Gain varies from 0.25 to 0.5 in steps of 0.004
`• For P=1 Gain varies from 0.5 to 0.99 in steps of 0.008
`• For P=2 Gain varies from 1 to 1.98 in steps of 0.016
`• For P=3 Gain varies from 2 to 3.97 in steps of 0.0.31
`
`8. Defective Pixel Correction
`A multidirectional 3x3 median filter (with maximal weighting) is implemented and can be enabled by pro-
`gramming roi_ddc_en in < reg_chain_cfg >. See Section 17.3.7.
`
`This filter is compatible with B&W and color products (Bayer or WRGB). All pixels of the ROI are cor-
`rected; this correction deletes 2 pixels all around the input picture so the ROI output is reduced by 2
`pixels in each line and column. See Section 4.5.3.
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`EV76C560
`
`P
`i
`
`4
`
`(cid:166)(cid:32)
`
`i
`
`1
`
`(cid:32)
`
`1
`k
`
`P T
`
`bin
`
`he k parameter, see binning_div_factor ,
`allows dividing the sum by 1, 2 or 4.
`
`X
`
`i
`
`4
`
`(cid:166)(cid:32)
`
`i
`
`1
`
`X
`
`bin
`
`(cid:32)
`
`1
`k
`
`With X = B, Gb, Gr or R.
`
`The k parameter, see binning_div_factor,
`allows dividing the sum by 1, 2 or 4.
`
`The binning respects the Bayer pattern to add
`only the same color pixels.
`
`9. Binning
`
`Two binning 2x2 modes are implemented:
`
`Figure 9-1.
`
`B&W binning (color_en=0)
`
`P1 P2
`
`P3
`
`P4
`
`Pbin
`
`Figure 9-2. Color binning (color_en=1)
`
`R1
`
`Gb1
`
`R3
`
`Gb3
`
`Gr1
`1
`B1
`
`Gr3
`1
`B3
`
`R2
`
`Gb2
`
`R4
`
`Gb4
`
`Gr2
`1
`B2
`
`Gr4
`1
`B4
`
`Rbin Grbin
`1
`Gbbin Bbin
`
`When k= 4 (cid:198) Average by 4 (cid:198) Saturation remains the same and noise on the image is reduced by a fac-
`tor 2.
`
`When k=2 or 1, the sum is clipped at the value 1023.
`
`The dimensions of the binning output image are half the input image dimensions.
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`10. Histograms
`Four histograms can be computed (for color sensors):
`
`• The first one with green blue pixels
`• The second one with red pixels
`• The third one with blue pixels
`• The fourth one with green red pixels
`To enable histogram calculation