2, 4, 8Gb: x8/x16 Multiplexed NAND Flash Memory
`Features
`
`NAND Flash Memory
`MT29F2G08AABWP/MT29F2G16AABWP
`MT29F4G08BABWP/MT29F4G16BABWP
`MT29F8G08FABWP
`
`Features
`• Organization:
`(cid:127) Page size:
`x8: 2,112 bytes (2,048 + 64 bytes)
`x16: 1,056 words (1,024 + 32 words)
`(cid:127) Block size: 64 pages (128K + 4K bytes)
`(cid:127) Device size: 2Gb: 2,048 blocks; 4Gb: 4,096 blocks;
`8Gb: 8,192 blocks
`(cid:127) Read performance:
`(cid:127) Random read: 25µs
`(cid:127) Sequential read: 30ns (3V x8 only)
`(cid:127) Write performance:
`(cid:127) Page program: 300µs (TYP)
`(cid:127) Block erase: 2ms (TYP)
`(cid:127) Endurance: 100,000 PROGRAM/ERASE cycles
`(cid:127) Data retention: 10 years
`(cid:127) First block (block address 00h) guaranteed to be
`valid without ECC (up to 1,000 PROGRAM/ERASE
`cycles)
`(cid:127) VCC: 2.7V–3.6V
`(cid:127) Automated PROGRAM and ERASE
`(cid:127) Basic NAND command set:
`(cid:127) PAGE READ, RANDOM DATA READ, READ ID,
`READ STATUS, PROGRAM PAGE, RANDOM DATA
`INPUT, PROGRAM PAGE CACHE MODE, INTER-
`NAL DATA MOVE, INTERNAL DATA MOVE with
`RANDOM DATA INPUT, BLOCK ERASE, RESET
`(cid:127) New commands:
`(cid:127) PAGE READ CACHE MODE
`(cid:127) READ UNIQUE ID (contact factory)
`(cid:127) READ ID2 (contact factory)
`(cid:127) Operation status byte provides a software method of
`detecting:
`(cid:127) PROGRAM/ERASE operation completion
`(cid:127) PROGRAM/ERASE pass/fail condition
`(cid:127) Write-protect status
`(cid:127) Ready/busy# (R/B#) pin provides a hardware
`method of detecting PROGRAM or ERASE cycle
`completion
`(cid:127) PRE pin: prefetch on power up
`(cid:127) WP# pin: hardware write protect
`
`Figure 1:
`
`48-Pin TSOP Type 1
`
`Options
`(cid:127) Density:
`2Gb (single die)
`4Gb (dual-die stack)
`8Gb (quad-die stack)
`(cid:127) Device width:
`x8
`x16
`(cid:127) Configuration:
`
`# of
`die
`1
`2
`4
`
`# of
`CE#
`1
`1
`2
`
`# of
`R/B#
`1
`1
`2
`
`(cid:127) VCC: 2.7V–3.6V
`(cid:127) Second generation die
`(cid:127) Package:
`48 TSOP type I (lead-free)
`48 TSOP type I (NEW version,
`8Gb device only, lead-free)
`48 TSOP type I (contact factory)
`(cid:127) Operating temperature:
`Commercial (0°C to 70°C)
`Extended temperature (-40°C to +85°C)
`
`Marking
`
`MT29F2GxxAAB
`MT29F4GxxBAB
`MT29F8GxxFAB
`
`MT29Fxx08x
`MT29Fxx16x
`
`A
`B
`F
`A
`B
`
`WP
`WA
`
`WG
`
`None
`ET
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`PDF: 09005aef818a56a7 / Source: 09005aef81590bdd
`1
`©2004 Micron Technology, Inc. All rights reserved.
`2gb_nand_m29b__1.fm - Rev. I 1/06 EN
`Products and specifications discussed herein are subject to change by Micron without notice.
`
`Petitioners
`Ex. 1049, p. 1
`
`

`

` 2, 4, 8Gb: x8/x16 Multiplexed NAND Flash Memory
`Part Numbering Information
`
`Part Numbering Information
`Micron® NAND Flash devices are available in several different configurations and
`densities. (See Figure 2.)
`
`Figure 2:
`
` Part Number Chart
`
`
`MT 29F 2G 08 A A B WP ES
`
`Micron Technology
`
`Product Family
`29F = Single-Supply NAND Flash Memory
`
`Density
`2G = 2Gb
`4G = 4Gb
`8G = 8Gb
`
`Device Width
`08 = 8 bits
`16 = 16 bits
`
`Classification
`
`# of die # of CE# # of R/B#
`A
`1
`1
`1
`B
`2
`1
`1
`F
`4
`2
`2
`
`I/O
`Common
`Common
`Common
`
`Operating Voltage Range
`A = 3.3V (2.70V–3.60V)
`
`Production Status
`Blank = Production
`ES = Engineering Sample
`MS = Mechanical Sample
`
`Operating Temperature Range
`Blank = Commercial (0°C to +70°C)
`ET = Extended (–40° to +85°C)
`
`Reserved for Future Use
`
`Reserved for Future Use
`
`Package Codes
`WP = 48-pin TSOP I (lead-free)
`WA = 48-pin TSOP I (new version,
`
` 8Gb device only, lead-free)
`WG = 48-pin TSOP I (contact factory)
`
`Generation
`A = 1st Generation Die
`B = 2nd Generation Die
`C = 3rd Generation Die
`
`Valid Part Number Combinations
`After building the part number from the part numbering chart above, verify that the part
`number is valid using the Micron Parametric Part Search Web site at
`http://www.micron.com/partsearch to verify that the part number is offered and valid.
`If the device required is not on this list, contact the factory.
`
`PDF: 09005aef818a56a7 / Source: 09005aef81590bdd
`2gb_nand_m29b__1.fm - Rev. I 1/06 EN
`
`2
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`©2004 Micron Technology, Inc. All rights reserved.
`
`Petitioners
`Ex. 1049, p. 2
`
`

`

` 2, 4, 8Gb: x8/x16 Multiplexed NAND Flash Memory
`Table of Contents
`
`Table of Contents
`Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
`Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
`Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
`General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
`Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
`Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
`Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
`Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
`Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
`Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
`Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
`READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
`Ready/Busy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
`Minimum Rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
`Power-On AUTO-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
`Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
`READ Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
`PAGE READ 00h-30h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
`RANDOM DATA READ 05h-E0h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
`PAGE READ CACHE MODE START 31h; PAGE READ CACHE MODE START LAST 3Fh. . . . . . . . . . . . . . . . . .24
`READ ID 90h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
`READ STATUS 70h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
`PROGRAM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
`PROGRAM PAGE 80h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
`SERIAL DATA INPUT 80h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
`RANDOM DATA INPUT 85h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
`PROGRAM PAGE CACHE MODE 80h-15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
`Internal Data Move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
`READ FOR INTERNAL DATA MOVE 00h-35h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
`INTERNAL DATA MOVE 85h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
`BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
`BLOCK ERASE 60h-D0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
`RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
`RESET FFh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
`WRITE PROTECT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
`Error Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
`Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
`VCC Power Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
`Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
`Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
`
`PDF: 09005aef818a56a7 / Source: 09005aef81590bdd
`2gb_nand_m29bTOC.fm - Rev. I 1/06 EN
`
`3
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`©2004 Micron Technology, Inc. All rights reserved.
`
`Petitioners
`Ex. 1049, p. 3
`
`

`

` 2, 4, 8Gb: x8/x16 Multiplexed NAND Flash Memory
`List of Figures
`
`List of Figures
`Figure 1:
`48-Pin TSOP Type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
`Figure 2:
`Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
`Figure 3:
`NAND Flash Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
`Figure 4:
`Pin Assignment (Top View) 48-Pin TSOP Type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
`Figure 5:
`Memory Map x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
`Figure 6:
`Memory Map x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
`Figure 7:
`Array Organization for MT29F2G08AxB (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
`Figure 8:
`Array Organization for MT29F2G16AxB (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
`Figure 9:
`Array Organization for MT29F4G08BxB and MT29F8G08FxB (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
`Figure 10:
`Array Organization for MT29F4G16BxB (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
`Figure 11:
`Time Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
`Figure 12:
`READY/BUSY# Open Drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
`Figure 13:
`tR and tF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
`Figure 14:
`Iol vs. Rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
`Figure 15:
`TC vs. Rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
`First Page Power-On AUTO-READ (3V VCC only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
`Figure 16:
`Figure 17:
`AC Waveforms During Power Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
`Figure 18:
`PAGE READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
`Figure 19:
`RANDOM DATA READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
`Figure 20:
`PAGE READ CACHE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
`Figure 21:
`READ ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
`Figure 22:
`Status Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
`Figure 23:
`PROGRAM and READ STATUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
`Figure 24:
`RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
`Figure 25:
`PROGRAM PAGE CACHE MODE Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
`Figure 26:
`INTERNAL DATA MOVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
`Figure 27:
`INTERNAL DATA MOVE with RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
`Figure 28:
`BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
`Figure 29:
`RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
`Figure 30:
`ERASE Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
`Figure 31:
`ERASE Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
`Figure 32:
`PROGRAM Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
`Figure 33:
`PROGRAM Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
`Figure 34:
`COMMAND LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
`Figure 35:
`ADDRESS LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
`Figure 36:
`INPUT DATA LATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
`Figure 37:
`SERIAL ACCESS Cycle After READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
`Figure 38:
`STATUS READ Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
`Figure 39:
`PAGE READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
`Figure 40:
`READ Operation with CE# “Don’t Care” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
`Figure 41:
`RANDOM DATA READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
`Figure 42:
`PAGE READ CACHE MODE Timing Diagram, Part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
`Figure 43:
`PAGE READ CACHE MODE Timing Diagram, Part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
`Figure 44:
`PAGE READ CACHE MODE Timing without R/B#, Part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
`Figure 45:
`PAGE READ CACHE MODE Timing without R/B#, Part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
`Figure 46:
`READ ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
`Figure 47:
`Program Operation with CE# “Don’t Care” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
`Figure 48:
`PROGRAM PAGE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
`Figure 49:
`PROGRAM PAGE Operation with RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
`Figure 50:
`INTERNAL DATA MOVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
`Figure 51:
`PROGRAM PAGE CACHE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
`
`PDF: 09005aef818a56a7 / Source: 09005aef81590bdd
`2gb_nand_m29bLOF.fm - Rev. I 1/06 EN
`
`4
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`©2004 Micron Technology, Inc. All rights reserved.
`
`Petitioners
`Ex. 1049, p. 4
`
`

`

` 2, 4, 8Gb: x8/x16 Multiplexed NAND Flash Memory
`List of Figures
`
`Figure 52:
`Figure 53:
`Figure 54:
`Figure 55:
`
`PROGRAM PAGE CACHE MODE Ending on 15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
`BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
`RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
`48-Pin TSOP Type I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
`
`PDF: 09005aef818a56a7 / Source: 09005aef81590bdd
`2gb_nand_m29bLOF.fm - Rev. I 1/06 EN
`
`5
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`©2004 Micron Technology, Inc. All rights reserved.
`
`Petitioners
`Ex. 1049, p. 5
`
`

`

` 2, 4, 8Gb: x8/x16 Multiplexed NAND Flash Memory
`List of Tables
`
`List of Tables
`Table 1:
`Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
`Table 2:
`Array Addressing: MT29F2G08AxB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
`Table 3:
`Array Addressing: MT29F2G16AxB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
`Table 4:
`Array Addressing: MT29F4G08BxB and MT29F8G08FxB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
`Table 5:
`Array Addressing: MT29F4G16BxB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
`Table 6:
`Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
`Table 7:
`Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
`Table 8:
`Device ID and Configuration Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
`Table 9:
`Status Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
`Table 10:
`Status Register Contents After RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
`Table 11:
`Absolute Maximum Ratings by Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
`Table 12:
`Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
`Table 13:
`DC and Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
`Table 14:
`Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
`Table 15:
`Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
`Table 16:
`Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
`Table 17:
`AC Characteristics: Command, Data, and Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
`Table 18:
`AC Characteristics: Normal Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
`Table 19:
`PROGRAM/ERASE Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
`
`PDF: 09005aef818a56a7 / Source: 09005aef81590bdd
`2gb_nand_m29bLOT.fm - Rev. I 1/06 EN
`
`6
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`©2004 Micron Technology, Inc. All rights reserved.
`
`Petitioners
`Ex. 1049, p. 6
`
`

`

` 2, 4, 8Gb: x8/x16 Multiplexed NAND Flash Memory
`General Description
`
`General Description
`NAND technology provides a cost-effective solution for applications requiring high-
`density solid-state storage. The MT29F2G08AxB and MT29F2G16AxB are 2Gb NAND
`Flash memory devices. The MT29F4G08BxB and MT29F4G16BxB are two-die stacks that
`operate as a single 4Gb device. The MT29F8G08FAB is a four-die stack that operates as
`two independent 4Gb devices (MT29F4G08BxB), providing a total storage capacity of
`8Gb in a single, space-saving package. Micron NAND Flash devices include standard
`NAND features as well as new features designed to enhance system-level performance.
`Micron NAND Flash devices use a highly multiplexed 8- or 16-bit bus (I/O[7:0] or
`I/O[15:0]) to transfer data, addresses, and instructions. The five command pins (CLE,
`ALE, CE#, RE#, WE#) implement the NAND command bus interface protocol. Three
`additional pins control hardware write protection (WP#), monitor device status (R/B#),
`and initiate the auto-read feature (PRE—3V device only). Note that the PRE function is
`not supported on extended-temperature devices.
`This hardware interface creates a low-pin-count device with a standard pinout that is
`the same from one density to another, allowing future upgrades to higher densities with-
`out board redesign.
`MT29F2G and MT29F4G devices contain 2,048 and 4,096 erasable blocks respectively.
`Each block is subdivided into 64 programmable pages. Each page consists of 2,112 bytes
`(x8) or 1,056 words (x16). The pages are further divided into a 2,048-byte data storage
`region with a separate 64-byte area on the x8 device; and on the x16 device, separate
`1,024-word and 32-word areas. The 64-byte and 32-word areas are typically used for
`error management functions.
`The contents of each 2,112-byte page can be programmed in 300µs, and an entire 132K-
`byte/66K word block can be erased in 2ms. On-chip control logic automates PROGRAM
`and ERASE operations to maximize cycle endurance. ERASE/PROGRAM endurance is
`specified at 100,000 cycles when using appropriate error correcting code (ECC) and
`error management.
`
`PDF: 09005aef818a56a7 / Source: 09005aef81590bdd
`2gb_nand_m29b__2.fm - Rev. I 1/06 EN
`
`7
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`©2004 Micron Technology, Inc. All rights reserved.
`
`Petitioners
`Ex. 1049, p. 7
`
`

`

` 2, 4, 8Gb: x8/x16 Multiplexed NAND Flash Memory
`General Description
`
`Figure 3:
`
` NAND Flash Functional Block Diagram
`
`
`VCC
`
`VSS
`
`Column Decode
`
`Row Decode
`
`Data Register
`
`Cache Register
`
`I/O [7:0]
`I/O [15:0]
`
`I/O
`Control
`
`Address Register
`
`Status Register
`
`Command Register
`
`Control
`Logic
`
`CE#
`CLE
`ALE
`WE#
`
`RE#
`WP#
`
`R/B#
`
`Note:
`
`The PRE function is not supported on extended-temperature devices.
`
`Figure 4:
`
` Pin Assignment (Top View) 48-Pin TSOP Type 1
`
`
`x8
`
`x16
`
`NC
`NC
`NC
`NC
`I/O7
`I/O6
`I/O5
`I/O4
`NC
`NC
`PRE/VSS2
`Vcc
`Vss
`NC
`NC
`NC
`I/O3
`I/O2
`I/O1
`I/O0
`NC
`NC
`NC
`NC
`
`Vss
`I/O15
`I/O7
`I/O14
`I/O6
`I/O13
`I/O5
`I/O12
`I/O4
`NC
`PRE/VSS2
`Vcc
`NC
`NC
`NC
`I/O11
`I/O3
`I/O10
`I/O2
`I/O9
`I/O1
`I/O8
`I/O0
`Vss
`
`48
`47
`46
`45
`44
`43
`42
`41
`40
`39
`38
`37
`36
`35
`34
`33
`32
`31
`30
`29
`28
`27
`26
`25
`
`1 ●
`
`234567891
`
`0
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`
`x16
`
`NC
`NC
`NC
`NC
`NC
`NC
`R/B#
`RE#
`CE#
`NC
`NC
`Vcc
`Vss
`NC
`NC
`CLE
`ALE
`WE#
`WP#
`DNU
`DNU
`DNU
`NC
`NC
`
`x8
`
`NC
`NC
`NC
`NC
`NC
`R/B2#1
`R/B#
`RE#
`CE#
`CE2#1
`NC
`Vcc
`Vss
`NC
`NC
`CLE
`ALE
`WE#
`WP#
`DNU
`DNU
`DNU
`NC
`NC
`
`Notes: 1. CE2# and R/B2# on 8Gb device only. These pins are NC for other configurations.
`2. The PRE function is not supported on extended-temperature devices.
`
`PDF: 09005aef818a56a7 / Source: 09005aef81590bdd
`2gb_nand_m29b__2.fm - Rev. I 1/06 EN
`
`8
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`©2004 Micron Technology, Inc. All rights reserved.
`
`Petitioners
`Ex. 1049, p. 8
`
`

`

`Table 1:
`
`Pin Descriptions
`
`Symbol
`ALE
`
`Type
`Input
`
`CE#, CE2#
`
`Input
`
`CLE
`
`PRE1
`(3V device only)
`RE#
`WE#
`WP#
`
`I/O[7:0]
`MT29FxG08
`
`I/O[15:0]
`MT29FxG16
`R/B#, R/B2#
`
`VCC
`VSS
`DNU
`NC
`
`Input
`
`Input
`
`Input
`Input
`Input
`
`I/O
`
`Output
`
`Supply
`Supply
`–
`–
`
` 2, 4, 8Gb: x8/x16 Multiplexed NAND Flash Memory
`General Description
`
`Description
`Address latch enable: During the time ALE is HIGH, address information is
`transferred from I/O[7:0] into the on-chip address register upon a LOW-to-HIGH
`transition on WE#. When address information is not being loaded, the ALE pin
`should be driven LOW.
`Chip enable: Gates transfers between the host system and the NAND device. Once
`the device starts a PROGRAM or ERASE operation, the chip enable pin can be de-
`asserted. For the 8Gb configuration, CE# controls the first 4Gb of memory; CE2#
`controls the second 4Gb. See the Bus Operation section, starting on “Bus
`Operation” on page 16 for additional operational details.
`Command latch enable: When CLE is HIGH, information is transferred from
`I/O[7:0] to the on-chip command register on the rising edge of WE#. When
`command information is not being loaded, the CLE pin should be driven LOW.
`Power-on read enable: Enables the auto-read function when at Vcc. See “Bus
`Operation” on page 16, for additional details.
`Read enable: Gates transfers from the NAND device to the host system.
`Write enable: Gates transfers from the host system to the NAND device.
`Write protect: Pin protects against inadvertent PROGRAM and ERASE operations.
`All PROGRAM and ERASE operations are disabled when the WP# pin is LOW.
`Data inputs/outputs: The bidirectional I/O pins transfer address, data, and
`instruction information. Data is output only during READ operations; at other
`times the I/O pins are inputs.
`
`Ready/busy: An open-drain, active-LOW output, that uses an external pull-up
`resistor. The pin is used to indicate when the chip is processing a PROGRAM or
`ERASE operation. The pin is also used during a READ operation to indicate when
`data is being transferred from the array into the serial data register. Once these
`operations have completed, the R/B# returns to the High-Z state. In the 8Gb
`configuration, R/B# is for the 4Gb of memory enabled by CE#; R/B2# is for the 4Gb
`of memory enabled by CE2#.
`VCC: The VCC pin is the power supply pin.
`VSS: The VSS pin is the ground connection.
`Do not use: Must be left floating.
`No connect: NC pins are not internally connected. These pins can be driven or left
`unconnected.
`
`Notes: 1. The PRE function is not supported on extended-temperature devices.
`
`PDF: 09005aef818a56a7 / Source: 09005aef81590bdd
`2gb_nand_m29b__2.fm - Rev. I 1/06 EN
`
`9
`
`Micron Technology, Inc., reserves the right to change products or specifications without notice.
`©2004 Micron Technology, Inc. All rights reserved.
`
`Petitioners
`Ex. 1049, p. 9
`
`

`

`Architecture
`
`Addressing
`
` 2, 4, 8Gb: x8/x16 Multiplexed NAND Flash Memory
`Architecture
`
`These devices use NAND electrical and command interfaces. Data, commands, and
`addresses are multiplexed onto the same pins. This provides a memory device with a
`low pin count.
`The internal memory array is accessed on a page basis. When doing reads, a page of data
`is copied from the memory array into the data register. Once copied to the data register,
`data is output sequentially, byte-by-byte on x8 devices, or word-by-word on x16 devices.
`The memory array is programmed on a page basis. After the starting address is loaded
`into the internal address register, data is sequentially written to the internal data register
`up to the end of a page. After all of the page data has been loaded into the data register,
`array programming is started.
`In order to increase programming bandwidth, this device incorporates a cache register.
`In the cache programming mode, data is first copied into the cache register and then
`into the data register. Once the data is copied into the data register, programming
`begins.
`After the data register has been loaded and programming started, the cache register
`becomes available for loading additional data. Loading the next page of data into the
`cache register takes place while page programming is in process.
`The INTERNAL DATA MOVE command also uses the internal cache register. Normally,
`moving d