TPS51020
`
`ą
`
`DUAL, VOLTAGE MODE, DDR SELECTABLE, SYNCHRONOUS,
`STEPĆDOWN CONTROLLER FOR NOTEBOOK SYSTEM POWER
`
`SLUS564B − JULY 2003 − REVISED DECEMBER 2003
`
`FEATURES
`D Wide Input Voltage Range: 4.5-V to 28-V
`D Selectable Dual and DDR Modes
`D Selectable Fixed Frequency Voltage Mode
`D Integrated Selectable Output Discharge
`D Advanced Power Good Logic Monitors both
`Channels
`D Selectable Autoskip Mode
`D Integrated Boot Strap Diodes
`D 180° Phase Shift Between Channels
`D Integrated 5-V, 60-mA Regulator
`D Input Feedforward Control
`D 1% Internal 0.85-V Reference
`D RDS(on) Overcurrent Detection (4200 ppm/°C)
`D Integrated OVP, UVP and Power Good Timers
`D 30-pin TSSOP Package
`
`APPLICATIONS
`D Notebook Computers System Bus and I/O
`D DDR I or DDR II Termination
`
`DESCRIPTION
`
`is a multi-function dual-
`The TPS51020
`synchronous step-down controller for notebook
`system power. The part is specifically designed
`for high performance, high efficiency applications
`where the loss associated with a current sense
`resistor is unacceptable. The TPS51020 utilizes
`feed forward voltage mode control to attain high
`efficiency without sacrificing
`line
`response.
`Efficiency at
`light
`load conditions can be
`maintained high as well by incorporating autoskip
`operation. A selectable, Suspend to RAM (STR)
`supported, DDR option provides a one chip
`solution
`for all switching applications
`from
`5-V/3.3-V supply to a complete DDR termination
`solution.
`
`ORDERING INFORMATION
`TA
`PLASTIC TSSOP (DBT)
`TPS51020DBT
`TPS51020DBTR (T&R)
`
`−40°C to 85°C
`−40°C to 85°C
`
`VO1
`
`VIN
`
`VO2
`
`VREG5
`
`EXT_5V
`
`VIN
`
`UDG−03144
`
`VIN
`
`VBST1
`
`OUT1_U
`
`LL1
`
`OUT1_D
`
`OUTGND1
`
`TRIP1
`
`VIN
`TRIP2
`
`VREG5
`
`REG5_IN
`
`OUTGND2
`
`OUT2_D
`
`LL2
`
`OUT2_U
`
`VBST2
`
`30
`
`29
`
`28
`
`27
`
`26
`
`25
`
`24
`
`23
`
`22
`
`21
`
`20
`
`19
`
`18
`
`17
`
`16
`
`TPS51020
`
`INV1
`
`COMP1
`
`SSTRT1
`
`SKIP
`
`VO1_VDDQ
`
`DDR
`
`GND
`
`REF_X
`
`ENBL1
`
`ENBL2
`
`VO2
`
`PGOOD
`
`SSTRT2
`
`1 2 3 4 5 6 7 8 9
`
`10
`
`11
`
`12
`
`13
`
`14
`COMP2
`15 INV2
`
`VO1
`
`SIMPLIFIED
`APPLICATION
`DIAGRAM
`
`VO1
`
`VIN
`
`VO2
`
`VREG5
`
`VO2
`
`Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
`Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
`
`is current as of publication date.
`information
`PRODUCTION DATA
`Products conform to specifications per the terms of Texas Instruments
`standard warranty. Production processing does not necessarily include
`testing of all parameters.
`
`Copyright  2003, Texas Instruments Incorporated
`
`www.ti.com
`
`1
`
`Petitioners
`Ex. 1040, p. 1
`
`

`

`TPS51020
`
`ą
`SLUS564B − JULY 2003 − REVISED DECEMBER 2003
`
`ABSOLUTE MAXIMUM RATINGS
`Over operating free-air temperature range unless otherwise noted. All voltage values are with respect to the network ground terminal unless
`otherwise noted. (1)
`
`Input voltage range
`Input voltage range
`
`Ouput voltage range
`Ouput voltage range
`
`VBST1, VBST2
`VBST1, VBST2 (with respect to LL )
`VIN, TRIP1, TRIP2, ENBL1, ENBL2, DDR
`SKIP, INV1, INV2
`OUT1_U, OUT2_U
`OUT1_U, OUT2_U (with respect to LL )
`LL1, LL2
`REF_X
`PGOOD, VO1_VDDQ, VO2, OUT1_D, OUT2_D, COMP1, COMP2, VREG5,
`SSTRT1, SSTRT2
`
`Output current range
`Output current range
`
`OUTGND1, OUTGND2
`VREG5
`REF_X
`Operating free-air temperature range, TA
`Storage temperature range, Tstg
`Junction temperature range, TJ
`Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
`
`RECOMMENDED OPERATING CONDITIONS
`
`TPS51020
`−0.3 to 35
`−0.3 to 7
`−0.3 to 30
`−0.3 to 7
`−1 to 35
`−0.3 to 7
`−1 to 30
`−0.3 to 15
`
`−0.3 to 7
`
`−0.3 to 0.3
`70
`7
`−40 to 85
`−55 to 150
`−40 to 125
`300
`
`UNIT
`
`V
`V
`
`mA
`mA
`
`°C
`°C
`
`TYP MAX UNIT
`28
`Supply voltage, VIN
`33
`Supply voltage, VBST1, VBST2
`28
`ENBL1, ENBL2, DDR, TRIP1, TRIP2
`33
`OUT1_U, OUT2_U
`5.5
`OUT1_U, OUT2_U (with respect to LL )
`28
`LL1, LL2
`12
`REF_X
`5.5
`SSTRT1, SSTRT2, COMP1, COMP2
`5.5
`SKIP, INV1, INV2
`5.5
`PGOOD VO1_VDDQ, VO2
`5.5
`OUT1_D, OUT2_D, VREG5
`60
`VREG5
`5
`REF_X
`°C
`85
`−40
`Operating free-air temperature, TA
`(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only,
`and functional operation of the device at these or any other conditions beyond those indicated under ”recommended operating conditions” is
`not implied. Exposure to Absolute Maximum Rated conditions for extended periods may affect device reliability
`
`I/O Voltage
`I/O Voltage
`
`Source current
`Source current
`
`MIN
`4.5
`4.5
`−0.1
`−0.8
`−0.1
`−0.8
`−0.1
`−0.1
`−0.1
`−0.1
`−0.1
`
`V
`V
`
`mA
`mA
`
`PACKAGE
`
`30-pin DBT
`
`DISSIPATION RATING TABLE
`TA < 25°C
`DERATING
`FACTOR ABOVE TA = 25°C
`POWER RATING
`7.0 mW/°C
`
`874 mW
`
`TA = 85°C
`POWER RATING
`454 mW
`
`2
`
`www.ti.com
`
`Petitioners
`Ex. 1040, p. 2
`
`
`

`

`TPS51020
`
`ą
`SLUS564B − JULY 2003 − REVISED DECEMBER 2003
`
`TSSOP (0.5 mm)
`DBT PACKAGE
`(TOP VIEW)
`
`30
`29
`28
`27
`26
`25
`24
`23
`22
`21
`20
`19
`18
`17
`16
`
`VBST1
`OUT1_U
`LL1
`OUT1_D
`OUTGND1
`TRIP1
`VIN
`TRIP2
`VREG5
`REG5_IN
`OUTGND2
`OUT2_D
`LL2
`OUT2_U
`VBST2
`
`1 2 3 4
`
`
`
`5 6 7 8 9 1
`
`0
`11
`12
`13
`14
`15
`
`INV1
`COMP1
`SSTRT1
`SKIP
`VO1_VDDQ
`DDR
`GND
`REF_X
`ENBL1
`ENBL2
`VO2
`PGOOD
`SSTRT2
`COMP2
`INV2
`
`ELECTRICAL CHARACTERISTICS
`TA = −40°C to 85°C, 4.5 V < VIN < 20 V, CVIN = 0.1 µF, CVREG5 = 2.2 µF, CREF_X = 0.01 µF, PGOOD = 0.2 V, ENBLx = DDR = VIN,
`INVx = COMPx, RSSTRTx = OPEN, TRIP1 = TRIP2 = VIN, LLx = GND, VBSTx = LLx+5, C(OUTx_U, OUTx_D)=1 nF, REG5_IN = 0V, GND =
`OUTGNDx = 0 V, VO1_VDDQ = VO2 = 0 V (unless otherwise stated)
`
`PARAMETER
`
`TEST CONDITIONS
`
`MIN
`
`TYP MAX UNIT
`
`INPUT CURRENTS
`
`IVIN
`
`VIN supply current
`
`IVIN(STBY)
`
`VIN standby current
`
`IVIN(SHDN) VIN shutdown current
`
`IVIN(REG5)
`
`VIN supply current, REG5_IN as 5-V input
`current
`
`REG5_IN input supply current
`IREG5
`VBST supply current
`IVBSTx
`VBST shutdown current
`IVBSTx
`VREG5 INTERNAL REGULATOR
`VREG5 voltage
`VVREG5
`VLD5
`Load regulation
`VLN5
`Line regulation
`VTHL
`UVLO threshold voltage
`VHYS(UV)
`UVLO hysteresis
`VTH(SW)
`Switchover voltage
`VHYS(SW)
`Switchover hysteresis
`
`REG5V_IN = OPEN,
`OSC = OFF
`
`ENBLx = 0 V,
`REG5V_IN = OPEN,
`
`ENBLx = DDR = 0 V,
`REG5V_IN = OPEN
`
`REG5V_IN = 5 V,
`
`REG5V_IN = 5 V,
`ENBLx = DDR = VIN
`ENBLx = DDR = 0 V
`
`IOUT = 0 A
`0 mA ≤ IOUT ≤ 50 mA,
`IOUT = 20 mA,
`High to low
`
`REG_IN voltage
`
`TRIPx = VIN,
`
`DDR = VIN,
`OSC = OFF
`
`OSC = OFF
`
`OSC = OFF
`
`VIN = 12 V
`7 V≤VIN ≤ 28 V
`
`1.4
`
`2.2 mA
`
`350
`
`550
`
`0.05
`
`1.00
`
`µA
`
`200
`
`500
`
`1.0
`0.05
`0.05
`
`1.7 mA
`1.00
`1.00
`
`µA
`A
`
`4.8
`
`3.45
`100
`4.2
`50
`
`V
`
`5.2
`5.0
`0.6% 2.5%
`0.4% 2.0%
`V
`3.65
`3.85
`200
`300 mV
`4.5
`4.8
`V
`250 mV
`
`www.ti.com
`
`3
`
`Petitioners
`Ex. 1040, p. 3
`
`
`

`

`TPS51020
`
`ą
`SLUS564B − JULY 2003 − REVISED DECEMBER 2003
`
`TEST CONDITIONS
`
`MIN
`
`TYP
`
`MAX
`
`UNIT
`
`ELECTRICAL CHARACTERISTICS (continued)
`TA = −40°C to 85°C, 4.5 V < VIN < 20 V, CVIN = 0.1 µF, CVREG5 = 2.2 µF, CREF_X = 0.01 µF, PGOOD = 0.2 V, ENBLx = DDR = VIN,
`INVx = COMPx, RSSTRTx = OPEN, TRIP1 = TRIP2 = VIN, LLx = GND, VBSTx = LLx+5, C(OUTx_U, OUTx_D)=1 nF, REG5_IN = 0V, GND =
`OUTGNDx = 0 V, VO1_VDDQ = VO2 = 0 V (unless otherwise stated)
`PARAMETER
`REF_X REFERENCE VOLTAGE
`10-V reference voltage
`VREF10
`VLD10
`Load regulation
`VLN10
`Line regulation
`
`V
`
`8.5
`
`11.0
`10.0
`-12% -20%
`5%
`
`1.5%
`
`0.75%
`
`765
`892
`
`786
`920
`
`808
`945
`
`1.12
`
`1.14
`
`1.16
`
`1.28
`
`1.31
`
`1.33
`
`mV
`mV
`
`V
`V
`
`2048
`
`clks
`
`2.2
`
`0.25
`
`945
`1.31
`
`510
`750
`
`11
`10
`
`3.7
`100
`
`0.3
`|1.0|
`
`10
`0.40
`|1.0|
`
`V
`V
`
`µA
`
`Ω
`
`V
`µA
`MΩ
`
`6
`0.32
`
`1.5
`
`970 1010 mV
`1.36
`1.41
`V
`µs
`20
`553
`813
`4096
`
`mV
`mV
`
`clks
`
`595
`875
`
`13
`13
`
`4200
`
`0
`0
`3.9
`200
`
`15
`16
`
`µA
`A
`
`ppm/
`°C
`
`mV
`mV
`
`|3.0|
`|5.0|
`V
`4.1
`300 mV
`
`VREFVTT
`
`VTT reference voltage
`
`VTT reference load regulation
`VREFVTT
`POWERGOOD COMPARATORS
`
`VTHDUAL(PG) PGOOD threshold (dual mode)
`VTHDUAL(PG) PGOOD threshold (dual mode)
`
`VTHDDR(PG) PGOOD threshold (DDR)
`VTHDDR(PG) PGOOD threshold (DDR)
`
`TPG(del)
`
`PGOOD delay time
`
`IOUT = 0 A
`VIN = 14 V,
`0 mA ≤ IOUT ≤ 2 mA,
`VIN = 18 V
`14 V≤VIN ≤28 V
`IOUT = 100 µA,
`DDR = 0 V wrt VO1_VDDQ input divided by 2
`VVO1 = 2.5 V
`0 mA ≤ IO ≤ 3 mA
`
`Undervoltage PGOOD
`Overvoltage PGOOD
`Undervoltage PGOOD,
`VO1_VDDQ = 2.5 V
`
`Overvoltage PGOOD,
`VO1_VDDQ = 2.5 V
`
`INVx > undervoltage PGOOD,
`Delay time from SSTRTx > 1.5 V to PGOOD
`going high
`
`DIGITAL CONTROL INPUTS
`High-level input voltage, logic
`VIH
`VIL
`Low-level input voltage, logic
`IINLEAK
`Logic input leakage current
`VO1_VDDQ and VO2
`VOx sink impedance
`RVOUT
`VVOUTOK
`VOx low restart voltage
`VVO2LEAK
`VOx input leakage current
`RVOUT
`VO1_VDDQ input impedance
`UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
`VOVPDUAL OVP trip output threshold (dual)
`OVP trip output threshold (DDR)
`VOVPDDR
`OVP propagation delay time(1)
`TOVP(del)
`VUVPDUAL UVP trip output threshold (dual)
`UVP trip output threshold (DDR)
`VUVPDDR
`TUVP(del)
`UVP propagation delay time
`OVERCURRENT and INPUT VOLTAGE UVLO PROTECTION
`TRIPx sink current
`ITRIPSNK
`VTRIPx = VIN − 100 mV,
`ITRIPSRC
`TRIPx source current
`VTRIPx = 100 mV,
`TA = 25°C
`
`DDR, ENBL1, ENBL2, SKIP
`DDR, ENBL1, ENBL2, SKIP
`DDR, ENBL1, ENBL2, SKIP= 5 V
`
`fault engaged
`VVOUTx = 0.5 V,
`Fault condition removed, restart
`DDR= VIN,
`VOx = 5 V
`DDR= 0
`
`Sensed at INVx
`VO1_VDDQ = 2.5 V
`
`Sensed at INVx
`VO1_VDDQ = 2.5 V
`
`TA = 25°C
`TA = 25°C
`
`TCITRIP
`
`TRIP current temperature coeficient(1)
`
`VOCPHI
`VOCPLO
`VVINUVLO
`VVINHYS
`
`High-level OCP comparator offset voltage(1)
`Low-level OCP comparator offset voltage(1)
`VIN UVLO trip threshold
`VIN UVLO trip hysteresis
`
`REF5V_IN = 4.8 V
`
`4
`
`www.ti.com
`
`Petitioners
`Ex. 1040, p. 4
`
`
`

`

`TPS51020
`
`ą
`SLUS564B − JULY 2003 − REVISED DECEMBER 2003
`
`ELECTRICAL CHARACTERISTICS (continued)
`TA = −40°C to 85°C, 4.5 V < VIN < 20 V, CVIN = 0.1 µF, CVREG5 = 2.2 µF, CREF_X = 0.01 µF, PGOOD = 0.2 V, ENBLx = DDR = VIN,
`INVx = COMPx, RSSTRTx = OPEN, TRIP1 = TRIP2 = VIN, LLx = GND, VBSTx = LLx+5, C(OUTx_U, OUTx_D)=1 nF, REG5_IN = 0V, GND =
`OUTGNDx = 0 V, VO1_VDDQ = VO2 = 0 V (unless otherwise stated)
`PARAMETER
`0.85-V REFERENCE CONTROL LOOP
`Error amplifier reference, channel 1 initial
`accuracy
`
`VREFCH1
`
`Measure COMP1,
`TA = 25°C
`
`COMP1= INV1,
`
`0.84
`
`0.85
`
`0.86
`
`V
`
`TEST CONDITIONS
`
`MIN
`
`TYP
`
`MAX
`
`UNIT
`
`VREFTC1
`
`VREFLN1
`
`Error amplifier reference, channel 1
`change with accuracy
`
`Error amplifier reference, channel 1
`change with line
`
`Channel 2 to channel 1 voltage mismatch
`VCHMM
`CONTROL LOOP: SKIP HYSTERSTIC COMPARATOR AND ZERO CURRENT COMPARATOR
`Skip hysteresis comparator hysteresis(1)
`VLLHYS
`Lload hysteresis comparator offset(1)
`VLLOFF
`Zero current comparator offset(1)
`VZOFF
`THLTOLL
`PWM skip delay time
`THLTOHL
`Skip to PWM delay time
`CONTROL LOOP ERROR AMPLIFIER
`COMPx source current
`IEASRC
`IEASNK
`COMPx sink current
`Unity gain bandwidth(1)
`FUGB
`Open loop gain(1)
`AOL
`COMPx voltage range(1)(6)
`CMRCOMP
`IINVLEAK
`INVx input current
`CONTROL LOOP: DUTY CYCLE, VOLTAGE RAMP, CHANNEL PHASE AND PWM DELAY PATH
`fOSC = 270 kHz(3)
`fOSC = 360 kHz
`fOSC = 450 kHz(2)
`PWM phase reversal only
`
`DCMAX
`DCMAX
`
`Maximum duty cycle
`Maximum duty cycle
`
`Channel to channel phase difference(5)
`PHCH
`OUTX_U minimum pulse width(1)
`TMIN
`TIMERS: INTERNAL OSCILLATOR(4)
`Fast oscillator frequency initial accuracy(2)
`fOSC(hi)
`fOSC(lo)
`Slow oscillator frequency initial accuracy
`fOSC(tc)
`Oscillator frequency over line and temperature
`(1) Ensured by design. Not production tested.
`(2) Maximum 450-kHz frequency can be achieved when both channels are enabled.
`(3) 270 kHz is the default frequency during start-up for both channels.
`(4) See Table 1.
`(5) See PWM detailed description
`
`RSSTRTx = OPEN
`RSSTRTx = 1MΩ or VSSTRT = 3 V
`Trimmed for 360 kHz
`
`0.5%
`
`0.1%
`
`0
`
`|5.0| mV
`
`3
`1 mV
`mV
`18
`
`2
`0
`10
`8
`1
`
`0.9
`0.7
`2.5
`80
`
`1
`
`0.2
`0.2
`
`0.4
`
`VREG5−3
`|0.5|
`
`clks
`clks
`
`mA
`mA
`
`MHz
`dB
`V
`µA
`
`°
`
`ns
`
`86% 88%
`84% 85%
`80% 82%
`180
`100
`
`450
`270
`360
`
`306
`
`kHz
`kHz
`
`414
`
`www.ti.com
`
`5
`
`Petitioners
`Ex. 1040, p. 5
`
`
`

`

`TPS51020
`
`ą
`SLUS564B − JULY 2003 − REVISED DECEMBER 2003
`
`TEST CONDITIONS
`
`MIN
`
`TYP MAX UNIT
`
`ELECTRICAL CHARACTERISTICS (continued)
`TA = −40°C to 85°C, 4.5 V < VIN < 20 V, CVIN = 0.1 µF, CVREG5 = 2.2 µF, CREF_X = 0.01 µF, PGOOD = 0.2 V, ENBLx = DDR = VIN,
`INVx = COMPx, RSSTRTx = OPEN, TRIP1 = TRIP2 = VIN, LLx = GND, VBSTx = LLX+5, C(OUTx_U, OUTx_D)=1 nF, REG5_IN = 0V, GND =
`OUTGNDx = 0 V, VO1_VDDQ = VO2 = 0 V (unless otherwise stated)
`PARAMETER
`TIMERS: SOFT-START RAMP GENERATOR
`SSTRTx charge current
`ISSQ
`ISSDQ
`SSTRTx discharge current
`SSTRTx at SMPS regulation point voltage(7)
`VREFTRK
`VSSOK
`SSTRTx OK to restart voltage
`SSTRTx finished voltage(8)
`VSSFIN
`SSTRTx frequency select voltage(9)
`VSSCLP
`OUTPUTS: INTERNAL BST DIODE
`
`VSSTRTx = 1 V
`VSSTRTx = 0.5 V
`
`1.8
`0.1
`1.00
`0.23
`1.4
`3.35
`
`2.3
`
`2.9
`
`1.22
`0.29
`1.5
`3.60
`
`1.45
`0.35
`1.6
`3.80
`
`µA
`mA
`
`V
`V
`
`0.80
`
`0.85
`
`0.1
`
`0.5
`
`10
`10
`5.0
`5.0
`
`3
`3
`2.5
`2.5
`100
`
`V
`
`µA
`
`Ω
`Ω
`
`ns
`
`VFBST
`
`Forward voltage
`
`(VVREF5− VVBSTx), VVREF5 = 5 V, IF = 10 mA
`TA = 25°C
`VRBST= 30 V
`
`Reverse current
`IRBST
`OUTPUTS: N-CHANNEL MOSFET GATE DRIVERS
`OUTx_U source impedance
`RUSRC
`RDSRC
`OUTx_D source impedance
`RUSNK
`OUTx_U sink impedance
`RDSNK
`OUTx_D sink impedance
`TDEAD
`Gate non-overlap dead time
`(1) Ensured by design. Not production tested.
`(2) Maximum 450-kHz frequency can be achieved only when both channels are enabled.
`(3) 270 kHz is the default frequency during start-up for both channels.
`(4) See Table 1.
`(5) See PWM detailed description
`(6) Feedforward Gain can be approximated as follows:
`VRAMP= K1×VIN+B1, VOFFSET=K2×VIN×+B2 where K1=0.017, K2=0.01, B1=0.35 V, B2=0.4 V.
` ǒK1 ) B1
`Ǔ ) (K2 VIN ) B2)
`+ VOUT
`At the running duty cycle, the VCOMP should be approximately: VCOMP
`(7) See waveform point A in Figure 1
`(8) See waveform point B in Figure 1
`(9) See waveform point C in Figure 1
`
`VIN
`
`Table 1. Frequency Selection
`
`FREQUENCY (kHz)
`SSTRT2
`SSTRT1
`450(10)
`CSSTRT only
`CSSTRT only
`1 MΩ || CSSTRT to GND
`360
`CSSTRT only
`1 MΩ || CSSTRT to GND
`360
`CSSTRT only
`1 MΩ || CSSTRT to GND
`1 MΩ || CSSTRT to GND
`270
`(10)Although selection is made by placing a 1M resistor in parallel with the SSTRTx timing
`capacitor, the softstart time to 0.85V is altered by about only 20%.
`
`6
`
`www.ti.com
`
`Petitioners
`Ex. 1040, p. 6
`
`
`

`

`TPS51020
`
`ą
`SLUS564B − JULY 2003 − REVISED DECEMBER 2003
`
`fSW − Switching Frequency − kHz
`
`270
`
`360
`
`360
`
`270
`
`270
`
`SSTRT1
`
`SSTRT2
`
`ENBL1
`
`ENBL2
`
`5.0
`
`3.6
`
`1.5
`1.2
`0
`
`5.0
`
`3.6
`
`1.5
`1.2
`0
`
`VSSTRT − Soft-Start Voltage − V
`
`270
`
`C
`
`AB
`
`ABC
`
`t0
`
`t1
`
`t2
`
`t3
`
`t4
`
`t5
`
`t − Time
`RSSTRT1 = 1 MΩ, RSSTRT2 = OPEN = 360 kHz
`Figure 2
`
`DESCRIPTION
`DESCRIPTION
`
`fSW − Switching Frequency − kHz
`270 360
`
`470
`
`360
`
`SSTRT1
`
`470
`
`SSTRT2
`
`t0
`
`t1
`
`t2
`
`t3
`t − Time
`RSSTRT1 = RSSTRT2 = OPEN = 450 kHz
`
`t4
`
`t5
`
`Figure 1
`
`ENBL1
`
`ENBL2
`
`5.0
`
`3.6
`
`1.5
`1.2
`0
`
`5.0
`
`3.6
`
`1.5
`1.2
`0
`
`VSSTRT − Soft-Start Voltage − V
`
`TERMINAL FUNCTIONS
`TERMINAL
`NAME
`NO.
`COMP1
`2
`COMP2
`14
`
`I/O
`I/O
`
`O
`O
`
`Error amplifier output. Connect feedback network to this pin and INVx for compensation of control loop.
`Error amplifier output. Connect feedback network to this pin and INVx for compensation of control loop.
`
`DDR
`
`ENBL1
`
`ENBL2
`
`GND
`INV1
`INV2
`LL1
`LL2
`OUT1_D
`OUT2_D
`OUT1_U
`OUT2_U
`OUTGND1
`OUTGND2
`
`6
`
`9
`
`10
`
`7
`1
`15
`28
`18
`27
`19
`29
`17
`26
`20
`
`I
`
`I
`
`I
`
`O
`I
`I
`I/O
`I/O
`O
`O
`O
`O
`O
`O
`
`DDR selection pin. If this pin is grounded, the device runs in DDR Mode. The error amplifier reference for VO2
`is (VO1_VDDQ)/2, the REF_X output voltage becomes (VO1_VDDQ)/2 and skip mode is disabled for VO2,
`Also, VREG5 is turned off when both ENBLx are at low in this mode. If this pin is at 2.2-V or higher, the device
`runs in ordinary dual SMPS mode (dual mode), then the error amplifier reference for VO2 is connected to inter-
`nal 0.85-V reference, the REF_X output voltage becomes 10 V, VREG5 is kept on regardless of ENBLx status.
`CAUTION: Do not toggle DDR while ENBL1 or ENBL2 are high. (See Table 2)
`
`TTL Enable Input. If ENBLx is greater than 2.2 V, then the VREG5 is enabled (DDR mode) and the SMPS of
`that channel attempts to turn on. If both ENBL1 and ENBL2 are low then the 10-V (or (VO1_VDDQ)/2 output)
`that channel attempts to turn on. If both ENBL1 and ENBL2 are low then the 10-V (or (VO1_VDDQ)/2 output)
`voltage as well as the oscillator are turned off. (See Table 2)
`Signal ground pin.
`
`Error amplifier inverting input. Also input for skip comparator, and OVP/UVP comparators.
`Error amplifier inverting input. Also input for skip comparator, and OVP/UVP comparators.
`
`Switch-node connection for high-side driver and overcurrent protection circuitry.
`Switch-node connection for high-side driver and overcurrent protection circuitry.
`
`Synchronous N-channel MOSFET driver output.
`Synchronous N-channel MOSFET driver output.
`
`High-side N-channel MOSFET driver output.
`High-side N-channel MOSFET driver output.
`
`Ground return for OUTx_D.
`Ground return for OUTx_D.
`
`www.ti.com
`
`7
`
`Petitioners
`Ex. 1040, p. 7
`
`
`

`

`TPS51020
`
`ą
`SLUS564B − JULY 2003 − REVISED DECEMBER 2003
`
`TERMINAL FUNCTIONS (continued)
`TERMINAL
`NAME
`NO.
`
`
`
`I/OI/O
`
`
`
`DESCRIPTIONDESCRIPTION
`
`PGOOD
`
`12
`
`O
`
`REF_X
`
`8
`
`O
`
`REG5_IN
`
`SSTRT1
`
`SSTRT2
`
`SKIP
`
`TRIP1
`
`TRIP2
`
`VBST1
`VBST2
`
`VO1_VDDQ
`
`VO2
`
`VREG5
`
`VIN
`
`21
`
`3
`
`13
`
`4
`
`25
`
`23
`
`30
`16
`
`5
`
`11
`
`22
`
`24
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`I
`
`I
`
`I
`
`O
`
`I
`
`Power good output. This is an open drain pull-down pin for power good. It remains low during soft-start until
`both outputs become within ±7.5%. If INV1 or INV2 is out of regulation, or VREG5V goes under UVLO then this
`pin goes low. The internal delay timer counts 2048 clks at low to high (by design, no delay for high to low). If
`ENBLx is low, and the power good output is high, then the power good signal for that channel is ignored.
`10-V N-channel MOSFET bias or (VO1_VDDQ)/2 reference output. If dual mode is selected (DDR > 2.2 V)
`then this pin provides a low 10-V current (< 2 mA) bias, dropped down from VIN, for the SO – S5 switched
`N-channel MOSFETs. If DDR mode is selected (DDR = GND) then this pin becomes (VO1_VDDQ)/2 capable
`of 3 mA source current. This bias/reference is shut off when ENBL1 and ENBL2 are both low. (See Table 2)
`External 5V regulator Input. If this pin is above 4.7 V, then the 5 V circuit bias switches from the VREF5 to the
`supply presented to REG5_IN.
`
`Soft-start/frequency select input. Connect a capacitor between SSTRTx and ground for adjusting the softstart
`time. A constant current fed to this capacitor ramps the reference during startup. Frequency selection is de-
`time. A constant current fed to this capacitor ramps the reference during startup. Frequency selection is de-
`scribed in Table 1. The soft-start capacitor is discharged upon UVLO/OVP/UVP, or when ENBLx is asserted
`low.
`Skip mode selection pin. Ground for automatic control between PWM mode in heavy load and hysteretic op-
`eration in light load. Tie high for PWM only operation for the entire load condition. If DDR is grounded, then skip
`mode is disabled for Channel 2.
`
`Channel 1 overcurrent trip point voltage input. Connect a resistor between TRIP1 and the high-side N-channel
`MOSFET input conversion voltage for high-side N-channel MOSFET UVP current limit shut down. Connect
`resistor between TRIP1 and GND for low-side N-channel MOSFET overcurrent latch shutdown.
`
`Channel 2 overcurrent trip point voltage input. Connect a resistor between TRIP2 and the high-side N-channel
`MOSFET input conversion voltage for high-side N-channel MOSFET UVP current limit shut down with a 180°
`channel phase shift. Connect resistor between TRIP2 and GND for low-side N-channel MOSFET over current
`latch shut-down. The oscillator voltage ramp adjustment (the feed-forward feature) for channel 2 is disabled
`when this pin is tied to ground via a resistor.
`
`Supply Input for high-side N-channel FET driver. Typically connected via charge pump from LLx.
`Supply Input for high-side N-channel FET driver. Typically connected via charge pump from LLx.
`
`Output discharge pin. Connect this pin to the SMPS output when discharge is required for power down. The
`
`output is discharged to at least 0.3 V before the channel can start-up again. Ground this pin when discharge isoutput is discharged to at least 0.3 V before the channel can start-up again. Ground this pin when discharge is
`not required. When grounded, corresponding channel disables the low side N-channel MOSFET during start-
`not required. When grounded, corresponding channel disables the low side N-channel MOSFET during start-
`up until the high side N-channel FET attempts to turn on. If DDR is low, then the VO1_VDDQ pin must be con-
`nected to the VDDQ output since this pin works as the VDDQ feedback to generate the VTT reference voltage
`and VO2 should be connected to GND since VTT must remain in a high-impedance state during S3 mode.
`Internal, 60-mA, 5-V regulator output. DDR, ENBL1 or ENBL2 high ( > 2.2V) turns on the 5 V regulator.
`High-voltage input. Typically the battery voltage. This pin serves as inputs for the VREF5 regulator, the REF_X
`regulator and positive input for overcurrent comparators. Precaution should be taken for tracing between this
`pin and the high-side N-channel MOSFET drain where positive node of TRIPx resistors are located.
`
`Table 2. Reference Regulator Control
`
`ENBL1
`
`ENBL2
`
`VREF5
`
`REF_X
`
`OSC
`
`MODE
`
`DDR
`
`DDR
`
`DDR
`
`DDR
`
`DUAL
`
`DUAL
`
`DUAL
`
`DUAL
`
`DDR
`
`LOW
`
`LOW
`
`LOW
`
`LOW
`
`HIGH
`
`HIGH
`
`HIGH
`
`HIGH
`
`LOW
`
`LOW
`
`HIGH
`
`HIGH
`
`LOW
`
`LOW
`
`HIGH
`
`HIGH
`
`LOW
`
`HIGH
`
`LOW
`
`HIGH
`
`LOW
`
`HIGH
`
`LOW
`
`HIGH
`
`OFF
`
`ON
`
`ON
`
`ON
`
`ON
`
`ON
`
`ON
`
`ON
`
`OFF
`
`OFF
`
`VO1_DDR
`2
`VO1_DDR
`2
`OFF
`
`10 V
`
`10 V
`
`10 V
`
`OFF
`
`ON
`
`ON
`
`ON
`
`OFF
`
`ON
`
`ON
`
`ON
`
`8
`
`www.ti.com
`
`Petitioners
`Ex. 1040, p. 8
`
`
`

`

`FUNCTIONAL BLOCK DIAGRAM
`
`TPS51020
`
`ą
`SLUS564B − JULY 2003 − REVISED DECEMBER 2003
`
`Shows Channel 1 (VO1_VDDQ) and the supporting circuitry.
`
`www.ti.com
`
`9
`
`Petitioners
`Ex. 1040, p. 9
`
`
`

`

`TPS51020
`
`ą
`SLUS564B − JULY 2003 − REVISED DECEMBER 2003
`
`PWM OPERATION
`
`APPLICATION INFORMATION
`
`The PWM control block utilizes a fixed-frequency, feed-forward, voltage-mode control scheme with a
`wide-bandwidth, low-impedance output error amplifier as the voltage servo control block. This scheme allows
`the highest efficiency down conversion while maintaining excellent line regulation and fast transient response.
`Loop compensation is programmed by connecting a filter network between the COMPx pin and the INVx pin.
`The wide bandwidth error amplifier handles conventional Type II compensation or Type III compensation when
`using ceramic capacitors for the converter output. For channel one, the reference signal for the control loop is
`always a precision 0.85-V internal reference, while the channel two loop reference is either the 0.85-V reference
`or, in the case of DDR mode, one half the VO1_VDDQ voltage, (VO1_VDDQ)/2. The output signal of the error
`amplifier appears at the COMPx pin and is compared to a buffered version of the 0.6-V oscillator ramp. When
`TRIP2 pin is tied to VIN through a resistor, the voltage ramp is further modulated by the input voltage, VIN, to
`maintain a constant modulator gain. If the TRIP2 pin is connected to ground through a resistor, then the voltage
`ramp remains fixed regardless of VIN value.
`
`The oscillator frequency is internally fixed and can be selected at 270 kHz, 360 kHz or 470 kHz by insertion of
`a clamping resistor on the SSTRTx pin per Table 1. For example, 470 kHz can be attained when both SSTRTx
`voltages exceed 3.5 V, as described in WAVEFORM1. The controller begins with 270 kHz in the first stage of
`the softstart, and then increases to 470 kHz at the steady state. When 270 kHz is selected, both of SSTRTx
`voltages are kept below 3.5 V so that the frequency is the same 270 kHz for the entire operation.
`
`Two channels are operated in 180 degrees out-of-phase interleave switching mode. This interleaving helps
`reduce the input current ripple requirement for the input capacitor. However, because the PWM loop determines
`both the turn-off AND turn-on of the high-side MOSFET, this 180 degree operation may not be apparent by
`looking at the LLx nodes only. Rather, the turn-off cycle of one channel always corresponds to the turn-on cycle
`of the other channel and vise-versa. As a result, input ripple is reduced and dynamic response is improved over
`a broad input voltage range.
`
`MAXIMUM DUTY CYCLE
`
`Because most notebook applications typically run from three to four cell Li−Ion or run from a 20-V adapter, 100%
`duty cycle operation is not required. Rather, the TPS51020 is optimized for low duty ratio step-down conversion.
`As a result of limiting the duty cycle, the flying BST capacitor is refreshed reliably and the low-side over current
`detection circuitry is capable of detecting an overcurrent condition even if the output is stuck between the
`regulation point and UVP. The maximum duty cycle for each operating frequency is 88% for 270 kHz, 85% for
`360 kHz and 82% for 470 kHz.
`
`It should be noted that if the system is operating close to maximum (or minimum) duty cycle, it may be difficult
`for the converter to respond quickly during line/load transients or state changes (such as frequency switching
`during soft start or PWM to SKIP mode transitions). This slow response is due to the dynamic range of the COMP
`pin and is usually not a result of poor phase compensation. In the case of minimum duty cycle operation, the
`slow response is due to the minimum pulse width of the converter (100 ns TYP). In this case (counter intuitively),
`it may be advisable to slow down the switching frequency of the converter in order to improve response time.
`
`10
`
`www.ti.com
`
`Petitioners
`Ex. 1040, p. 10
`
`
`

`

`TPS51020
`
`ą
`SLUS564B − JULY 2003 − REVISED DECEMBER 2003
`
`APPLICATION INFORMATION
`
`SKIP MODE OPERATION
`
`If the SKIP pin is set HIGH, the SMPS operates in the fixed PWM mode. While a LOW signal is applied, the
`controller operates in autoskip mode. In the autoskip mode, the operation changes from constant frequency
`PWM mode to an energy-saving skip mode automatically by detecting the edge of discontinuous current mode.
`During the skip mode, the hysteretic comparator monitors output voltage to trigger high side on at the next
`coming oscillator pulse after the lower level is detected. Several sequential pulses may be seen, especially in
`the intermediate load level, before output capacitor is charged up to the higher level and waits for next cycle.
`In the skip mode, frequency varies with load current and input voltage.
`
`Skip mode for SMPS_2 is disabled regardless of the SKIP pin status if DDR mode is selected (see Dual Mode
`and DDR Mode section). This is because current sink capability is required for VTT, so that rectifying MOSFET
`needs to be kept on when the inductor current flows inversely. SMPS_1 is still capable of skip mode operation
`while DDR Mode.
`
`CASCADE CONFIGURATION
`
`If the TRIP2 pin is tied through a resistor to the input voltage, the TPS51020 assumes that the conversion voltage
`for channel two is the VIN voltage, usually VBATT. Conversely, if TRIP2 is tied through a resistor to ground, the
`controller assumes that the conversion voltage for channel two is the output voltage of channel one or some
`other stable bus voltage.
`
`DUAL MODE AND DDR MODE
`
`TPS51020 provides one-chip solution for system power supply, such as for 5 V, 3.3 V or 1.8 V, and a dual
`switcher DDR power supply. By simply selecting DDR signal and some external configuration change following
`the instructions below, TPS51020 gives a complete function set required for the DDR termination supply such
`as VDDQ/2 tracking VTT source/sink capability and VTT reference output.
`If DDR is set high ( > 2.2 V), the TPS51020 runs in dual mode, that is, each converter produces an independent
`output voltage with respect to the internal 0.85-V reference. Bypass REF_X to ground by 0.01-µF. The
`VO1_VDDQ or VO2 terminal can be connected to either to their corresponding switcher output or ground,
`depending on customer’s choice of using or not using the output discharge function (See Softstop). The 10-V
`reference output can be used as FET switch biasing for power control during sleep states (see Figure 5). During
`this dual mode, selection of autoskip mode or PWM mode made by SKIP applies to both SMPS_1 and SMPS_2.
`
`If DDR is set low ( < 0.3V), the TPS51020 operates as a dual switcher DDR supply; VDDQ from SMPS_1 and
`VTT from SMPS_2 (DDR Mode). In this mode, the reference voltage for SMPS_2 is switched to (VO1_VDDQ)/2
`to track exactly half the voltage of SMPS_1, divided by internal resistors. VO1_VDDQ should be connected to
`SMPS_1 output terminal to accomplish this, while VO2 connection is still flexible to the customer’s choice of
`softstop. REF_X outputs the (VO1_VDDQ)/2 voltage after a buffer (5-mA max). SKIP controls only SMPS_1
`and SMPS_2 is forced to operate in PWM mode so that current can be sink from the output. Power source of
`SMPS_2 can either be the battery voltage (independent configuration), or the VDDQ (cascade configuration)
`by user’s preference. When using the independent configuration, TRIP2 needs to be connected to the VIN node
`via trip resistor. In case of cascade configuration, tie TRIP2 to GND via trip resistor (see Figure 7).
`
`CAUTION:Do NOT toggle DDR HIGH while ENBL1 or ENBL2 is high (see Table 2). REF_X
`output switches to high voltage (10 V) and be applied to VTTREF directly
`
`www.ti.com
`
`11
`
`Petitioners
`Ex. 1040, p. 11
`
`
`

`

`TPS51020
`
`ą
`SLUS564B − JULY 2003 − REVISED DECEMBER 2003
`
`APPLICATION INFORMATION
`
`5-V LINEAR REGULATOR (VREG5)
`
`The VREG5 voltage is the bias for all the low voltage circuitry in the TPS51020 as well as the DC boost voltage
`for the MOSFET gate drivers. Total available current is 60 mA. Bypass this pin to GND by 4.7-µF. The under
`voltage lockout (UVLO) circuit monitors the output of this regulator to protect internal circuitry from low input
`voltages. If 5 V is applied to REG5_IN from either the SMPS output or an alternate 5 V, then the linear regulator
`is turned off and the VREG5 pin is switched over to REG_IN. This operation enhances the efficiency of the
`overall power supply system because the bulk of the quiescent current now runs from the 5-V output instead
`of VIN (VBAT). In this configuration, ensure that VREG5_IN is less than or equal to VVIN.
`
`EXTERNAL 5V INPUT (REG5_IN)
`
`When a 5-V bus is available, VIN does not need to be connected to the battery. In this configuration, VIN should
`be connected to REG5_IN.
`
`LOW-SIDE N-CHANNEL FET DRIVER
`
`The low-side driver is designed to drive high current low RDS(on) N-channel MOSFET(s). The maximum drive
`voltage is 5.5 V. The drive capability is represented by its internal resistance, which are 3 Ω for VREG5 to
`OUTx_D and 2.5 Ω for OUTx_D to OUTGNDx. A dead time is internally generated between top MOSFET off
`to bottom MOSFET on, and bottom MOSFET off to top MOSFET on, in order to prevent shoot through.
`
`The low-side driver is typically turned off during all fault modes except for OVP. When an OVP condition exists,
`the low-side driver of the offending channel turns on and attempts to blow the protection fuse of the input supply.
`During power up the low-side driver is kept off until the high side driver attempt to turn on once. In this fashion,
`the TPS51020 can power up into a precharged output voltage, if so desired.
`
`HIGH-SIDE N-CHANNEL FET DRIVER
`
`The high-side driver is designed to drive high current, low RDS(on) N-channel MOSFET(s). When configured as
`a floating driver, a 5-V bias voltage is delivered from VREG5 supply. The instantaneous drive current is supplied
`by the flying capacitor between VBSTx and LLx pins, 0.1-µF ceramic for typical applications. The boost diodes
`are integrated and are sufficient for enhancing the high-side MOSFET. However, external boost diodes can also
`be added from VREG5 to each VBSTx in case higher gate-to-source votlage is required.
`The drive capability is represented by its internal resistance, which are as follows: 3 Ω for VBST to OUTx_U
`and 2.5 Ω for OUTx_U to LLx. The maximum voltage that can be applied between OUTx_U pin and OUTGNDx
`pin is 35 V.
`
`12
`
`www.ti.com
`
`Petitioners
`Ex. 1040, p. 12
`
`
`

`

`TPS51020
`
`ą
`SLUS564B − JULY 2003 − REVISED DECEMBER 2003
`
`ENABLE AND SOFT-START
`
`APPLICATION INFORMATION
`
`Each SMPS is switched into standby mode separately by grounding the corresponding ENBLx pin. The 5-V
`supply is enabled if either the DDR, ENBL1 or ENBL2 pin(s) goes high ( >2.2 V).
`
`Softstart of each SMPS is achieved by slowly ramping the error amplifier reference voltage by following a
`buffered version of the SSTRTx pin voltage. Designers can achieve their own start-up sequencing by simply
`provide external timing signals since the startup times do not depend on the load current. The softstart time is
`programmable by external capacitor connected from SSTRTx pin to the ground. Each SSTRTx pin sources
`constant current, typically 2.3 µA. The output voltage of the SMPS ramps up from 0 V to its target regulation
`voltage as the SSTRTx pin voltage increases from 0 V to 1.2 V. This gives the softstart time formula to be,
`TSSTRT (sec) 2.3 10*6
`1.2
`
`CSSTRT (Farads) +
`
`The soft-start capacitor is discharged upon UVLO, OVP or UVP is detected as well as ENBLx is set low.
`
`OUTPUT DISCHARGE (SOFT-STOP)
`
`When an SMPS is turned off by ENBLx asserted low or the part enters a fault mode, both top and bot