IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS,
`INC.; and MICRON TECHNOLOGY TEXAS LLC,
`Petitioners,
`
`v.
`
`NETLIST, INC.,
`Patent Owner.
`
`Case No. IPR2022-00418
`U.S. Patent No. 8,301,833
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 8,301,833
`
`Petitioners
`Ex. 1022, p. Cover
`
`

`

`Petition for IPR re U.S. Patent No. 8,301,833
`
`TABLE OF CONTENTS
`
`Page
`Introduction ........................................................................................................ 1
`I.
`II. Requirements for Inter Partes Review .............................................................. 1
`A. Certification ................................................................................................... 2
`Identification of Challenge ............................................................................ 2
`B.
`III. The ’833 Patent .................................................................................................. 2
`A. Effective Filing Date ...................................................................................... 2
`B. Level of Ordinary Skill in the Art .................................................................. 4
`C. Overview ........................................................................................................ 5
`D. Relevant Prosecution History ........................................................................ 7
`E. Related Patents ............................................................................................... 8
`IV. Claim Construction ............................................................................................ 9
`V. Detailed Discussion of the Grounds for Unpatentability ................................... 9
`A. Overview of the Principal Prior Art ............................................................. 10
`1. Best (Ex. 1006) ......................................................................................... 10
`a. Prior Art Status ...................................................................................... 10
`b. Overview of Best .................................................................................. 12
`2. Bonella (Ex. 1008) .................................................................................... 14
`3. Mills (Ex. 1009) ........................................................................................ 17
`B. Ground 1: Under the Doctrine of Collateral Estoppel, Claims 1 and 15 are
`Unpatentable and Netlistis Estopped From Relitigating those Adjudicated Issues
`
`18
`C. Ground 2: Claims 1, 3-17, and 19-30 Are Obvious Over Best in View of
`Bonella and Mills ................................................................................................. 24
`1. Claims 1 and 15 ........................................................................................ 24
`a. Preambles .............................................................................................. 25
`b. Operating a “Volatile Memory Subsystem” at a “First Clock
`Frequency” ................................................................................................... 26
`c. Operating a “Non-Volatile Memory Subsystem” at a “Second Clock
`Frequency” ................................................................................................... 29
`
`ii
`
`Petitioners
`Ex. 1022, p. ii
`
`

`

`Petition for IPR re U.S. Patent No. 8,301,833
`
`d. Operating the “Volatile Memory Subsystem” at a “Third Clock
`Frequency” ................................................................................................... 34
`2. Claim 16 ................................................................................................... 38
`3. Claim 17 ................................................................................................... 42
`4. Claims 3 and 19 ........................................................................................ 44
`5. Claims 4 and 20 ........................................................................................ 46
`6. Claims 5 and 21 ........................................................................................ 47
`7. Claims 6 and 22 ........................................................................................ 47
`8. Claims 7 and 23 ........................................................................................ 48
`9. Claims 8 and 24 ........................................................................................ 51
`10. Claims 9 and 25 ........................................................................................ 52
`11. Claims 10 and 26 ...................................................................................... 53
`12. Claims 11 and 27 ...................................................................................... 53
`13. Claims 12 and 28 ...................................................................................... 54
`14. Claims 13 and 29 ...................................................................................... 55
`15. Claims 14 and 30 ...................................................................................... 58
`D. No Secondary Considerations Exist ............................................................ 60
`VI. The Parallel Litigation Does Not Warrant Denying Institution ....................... 60
`VII. Past IPRs Do Not Warrant Denying Institution ............................................... 63
`VIII. Mandatory Notices ....................................................................................... 64
`A. Real Parties-in-Interest ................................................................................. 64
`B. Related Proceedings ..................................................................................... 64
`C. Lead and Backup Counsel ........................................................................... 65
`D. Electronic Service ........................................................................................ 65
`IX. Fees ................................................................................................................... 65
`X. Conclusion ........................................................................................................ 66
`
`iii
`
`Petitioners
`Ex. 1022, p. iii
`
`

`

`Petition for IPR re U.S. Patent No. 8,301,833
`
`TABLE OF AUTHORITIES
`
` Page(s)
`
`Cases
`Amazon.com, Inc. v. M2M Solutions LLC,
`IPR2019-01204, Paper 43 (PTAB January 20, 2021) ........................................ 22
`Apple Inc. v. Fintiv, Inc.,
`IPR2020-00019, Paper 11 (PTAB Mar. 20, 2020) ....................................... 60, 62
`Apple, Inc. v. SEVEN Networks, LLC,
`IPR2020-00156, Paper 10 (PTAB June 15, 2020) ....................................... 61, 62
`Dynamic Drinkware, LLC v. Nat’l Graphics, Inc.,
`800 F.3d 1375 (Fed. Cir. 2015) ...................................................................... 3, 10
`General Plastic Industrial Co. v. Canon Kabushiki Kaisha.,
`IPR2016-01357, Paper 19 (PTAB Sept. 6, 2017) ............................................... 63
`Hyatt v. Boone,
`146 F.3d 1348 (Fed. Cir. 1998) ............................................................................ 3
`Micron Tech., Inc. v. Godo Kaisha IP Bridge 1,
`IPR2020-01007, Paper 15 (PTAB December 7, 2020) ...................................... 62
`Mobile Tech, Inc. v. InVue Security Products Inc.,
`IPR2018-01138, Paper 28 (PTAB Dec. 5, 2019) ......................................... 22, 23
`Nevro Corp. v. Boston Scientific Neuromodulation Corp.,
`IPR2019-01313, Paper 74 (PTAB January 19, 2021) ........................................ 19
`Ohio Willow Wood Co. v. Alps South, LLC,
`735 F.3d 1333 (Fed. Cir. 2013) .............................................................. 18, 21, 22
`RimFrost AS v. Aker Biomarine Antarctic AS,
`IPR2018-01178, Paper 34 (PTAB Jan. 13, 2020) .............................................. 19
`Rimfrost AS v. Aker Biomarine Antarctic AS,
`IPR2018-01730, Paper 35 (PTAB March 6, 2020) ............................................ 19
`Sand Revolution II, LLC v. Cont’l Intermodal Grp–Trucking LLC,
`IPR2019-01393, Paper 24 (June 16, 2020) ......................................................... 62
`iv
`
`Petitioners
`Ex. 1022, p. iv
`
`

`

`Petition for IPR re U.S. Patent No. 8,301,833
`
`Shure Inc. v. Clearone, Inc.,
`PGR2020-00079, Paper 14 (February 16, 2021) ................................................ 62
`Thorne Research, Inc. v. Trustees of Dartmouth College,
`IPR2021-00268, Paper 21 (PTAB June 10, 2021) ................................. 19, 23, 24
`VirnetX Inc. v. Apple, Inc.,
`909 F.3d 1375 (Fed. Cir. 2018) .......................................................................... 19
`VMware, Inc. v. Intellectual Ventures I LLC,
`IPR2020-00470, Paper 13 (PTAB August 18, 2020) ......................................... 60
`Statutes
`35 U.S.C. § 102 ...................................................................................... 10, 12, 14, 17
`35 U.S.C. § 103 .................................................................................................... 2, 18
`35 U.S.C. § 119 .......................................................................................................... 3
`35 U.S.C. § 112 .......................................................................................................... 3
`35 U.S.C § 314(a) .................................................................................................... 63
`Other Authorities
`37 C.F.R. § 42 ............................................................................................................ 1
`
`v
`
`Petitioners
`Ex. 1022, p. v
`
`

`

`Petition for IPR re U.S. Patent No. 8,301,833
`
`TABLE OF ABBREVIATIONS AND CONVENTIONS
`
`Abbreviation
`
`Meaning
`
`’321 Application U.S. Provisional Application No. 60/912,321
`
`’586 Application U.S. Provisional Application No. 60/941,586
`
`’692 IPR
`
`SK hynix Inc. et al. v. Netlist, Inc., IPR2017-00692, Paper 25
`(PTAB July 5, 2018) (Final Written Decision)
`
`’831 Patent
`
`U.S. Patent No. 8,874,831
`
`’833 Patent
`
`U.S. Patent No. 8,301,833
`
`’916 Application U.S. Patent Application No. 12/240,916
`
`Ashmore
`
`U.S. Patent App. Pub. No. 2006/0212651
`
`Best
`
`U.S. Patent App. Pub. No. 2010/0110748 to Best
`
`Bonella
`
`U.S. Patent App. Pub. No. 2007/0136523 to Bonella
`
`Dec.
`
`Long
`
`Mills
`
`Declaration of Ron Maltiel (Ex. 1003)
`
`U.S. Patent No. 7,421,552 to Long
`
`U.S. Patent No. 6,026,465 to Mills
`
`vi
`
`Petitioners
`Ex. 1022, p. vi
`
`

`

`Petition for IPR re U.S. Patent No. 8,301,833
`
`PETITIONER’S EXHIBIT LIST
`
`Ex. No.
`
`Brief Description
`
`1001
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`1008
`
`1009
`
`1010
`
`1011
`
`1012
`
`1013
`
`1014
`
`1015
`
`1016
`
`U.S. Patent No. 8,301,833
`
`File History of U.S. Patent No. 8,301,833
`
`Declaration of Ron Maltiel
`
`Curriculum Vitae of Ron Maltiel
`
`U.S. Provisional Application No. 60/941,586
`
`U.S. Patent App. Pub. No. 2010/0110748 to Best
`
`U.S. Provisional Application 60/912,321 to Best
`
`U.S. Patent App. Pub. No. 2007/0136523 to Bonella
`
`U.S. Patent No. 6,026,465 to Mills
`
`U.S. Patent App. Pub. No. 2006/0212651 to Ashmore
`
`U.S. Patent No. 7,421,552 to Long
`
`Netlist’s Proposed Claim Constructions in Netlist, Inc. v.
`Micron Technology, Inc. et al., Case No. 6:21-cv-00430
`(W.D. Tex.)
`
`Micron’s Proposed Claim Constructions in Netlist, Inc. v.
`Micron Technology, Inc. et al., Case No. 6:21-cv-00430
`(W.D. Tex.)
`
`Filed Stipulations of Petitioners for U.S. Patent No. 8,301,833
`in Netlist, Inc. v. Micron Technology, Inc. et al., Case No.
`6:21-cv-00430 (W.D. Tex.)
`
`U.S. Patent No. 8,874,831
`
`U.S. Patent App. Pub. No. 2003/0028733 to Tsunoda
`
`vii
`
`Petitioners
`Ex. 1022, p. vii
`
`

`

`Petition for IPR re U.S. Patent No. 8,301,833
`
`Ex. No.
`
`1017
`
`1018
`
`1019
`
`1020
`
`1021
`
`1022
`
`Brief Description
`
`JEDEC Standard, DDR2 SDRAM Specification, JESD79-2B
`(Jan. 2005)
`
`JEDEC Standard, DDR SDRAM Specification, JESD79 (Jun.
`2000)
`
`Intel, 1.8 Volt Intel StrataFlash® Wireless Memory (L18)
`(Apr. 2003)
`
`Scheduling Order, Netlist, Inc. v. Micron Technology, Inc. et
`al., Case No. 6:21-cv-00430 (W.D. Tex.), ECF No. 30
`
`Judge Albright, ORDER GOVERNING PROCEEDINGS –
`PATENT CASES (Ver. 3.5.1)
`
`Proof of Service of Summons and Complaint in Netlist, Inc. v.
`Micron Technology, Inc. et al., Case No. 6:21-cv-00430
`(W.D. Tex.)
`
`viii
`
`Petitioners
`Ex. 1022, p. viii
`
`

`

`Petition for IPR re U.S. Patent No. 8,301,833
`
`I.
`
`Introduction
`Petitioners request inter partes review (“IPR”) of claims 1, 3-17, and 19-30
`
`(“Challenged Claims”) of U.S. Patent No. 8,301,833 (“’833 Patent”).
`
`The independent Challenged Claims (1 and 15) are unpatentable based on the
`
`effect of collateral estoppel. These claims are near identical, in relevant part, to claim
`
`15 in related U.S. Patent No. 8,874,831 (“’831 Patent”)—which the PTAB
`
`previously invalidated as obvious in IPR2017-00692, Paper 25 (PTAB July 5,
`
`2018). The present Petition asserts the same obviating prior art combination as in
`
`IPR2017-00692, and the Board should invalidate the claims here as it did in the prior
`
`well-reasoned opinion.
`
`The remaining dependent Challenged Claims (3-14, 16-17, and 19-30), add
`
`nothing to the validity analysis, and are therefore unpatentable, as they merely recite
`
`well-known components and features that have been included in commonplace
`
`memory systems well prior to the ’833 Patent’s priority date.
`
`II.
`
`Requirements for Inter Partes Review
`This Petition complies with all statutory requirements, as well as 37 C.F.R.
`
`§§ 42.104, 42.105, and 42.15, and should be accorded a filing date pursuant to 37
`
`C.F.R. § 42.106. The required fee is being paid electronically through PTAB E2E.
`
`Petitioners
`Ex. 1022, p. 1
`
`

`

`Petition for IPR re U.S. Patent No. 8,301,833
`
`A. Certification
`Pursuant to 37 C.F.R. § 42.104(a), Petitioners certify that the ’833 Patent is
`
`available for IPR and Petitioners are not barred or estopped from requesting an IPR
`
`challenging the claims on the grounds identified herein.
`
`B.
`Identification of Challenge
`Under 37 C.F.R. §§ 42.104(b) and 42.22, Petitioners request that the Board
`
`institute this IPR on claims 1, 3-17, and 19-30 of the ’833 Patent and cancel those
`
`claims as unpatentable for obviousness under pre-AIA 35 U.S.C. § 103 on the
`
`following grounds:
`
`Ground
`
`Claims
`
`Basis for Unpatentability
`
`1
`
`2
`
`1 and 15
`
`Unpatentable as obvious under the doctrine of
`collateral estoppel
`
`1, 3-17, and
`19-30
`
`Obvious over Best (Ex. 1006) in view of Bonella
`(Ex. 1008) and Mills (Ex. 1009)
`
`
`III. The ’833 Patent
`A. Effective Filing Date
`The ’833 Patent resulted from Application No. 12/240,916 (“’916
`
`Application”), filed September 29, 2008, a continuation of Application No.
`
`12/131,873, filed on June 2, 2008 (abandoned). The ’833 Patent claims priority to
`
`Provisional Application No. 60/941,586 (“’586 Application”) (Ex. 1005), filed on
`
`June 1, 2007.
`
`
`
`2
`
`Petitioners
`Ex. 1022, p. 2
`
`

`

`Petition for IPR re U.S. Patent No. 8,301,833
`
`The Challenged Claims are not entitled to the benefit of the ’586
`
`Application’s June 1, 2007 filing date because the ’586 Application does not provide
`
`written description. 35 U.S.C. §§ 119(e), 112 (pre-AIA). Netlistcannot show1 from
`
`the disclosure of the ’586 Application that the inventors were in “possession” of the
`
`invention, i.e., that the written description “include[s] all of the limitations” of the
`
`claims or that “any absent text is necessarily comprehended in the description
`
`provided and would have been so understood at the time the patent application was
`
`filed.” Hyatt v. Boone, 146 F.3d 1348, 1354-55 (Fed. Cir. 1998).
`
`Netlist cannot make the requisite showing here. Specifically, claims 1 and 15,
`
`from which all the remaining Challenged Claims depend, recite at least the following
`
`features that lack written description support in the ’586 Application2:
`
`• “the volatile memory subsystem further being operable at a third clock
`
`frequency when the memory system is in the second mode of operation,
`
`the third clock frequency being less than the clock first frequency.”
`
`
`1 Dynamic Drinkware, LLC v. Nat’l Graphics, Inc., 800 F.3d 1375, 1378-81 (Fed.
`
`Cir. 2015) (patent owner burden to show entitlement to provisional filing date).
`
`2 The features listed correspond to claim 15, but the corresponding features of claim
`
`1 (which are not reproduced to avoid redundancy) also lack written description
`
`support in the ’586 Application.
`
`
`
`3
`
`Petitioners
`Ex. 1022, p. 3
`
`

`

`Petition for IPR re U.S. Patent No. 8,301,833
`
`In fact, the ’586 Application does not even include the words “clock” or “frequency,”
`
`much less disclose anything remotely sufficient to show possession of volatile and
`
`non-volatile memory subsystems being operable at the clock frequencies recited in
`
`claims 1 and 15. See Dec., ¶¶ 55-56.
`
`
`
`Further, the remaining Challenged claims all depend from either claim 1 or
`
`claim 15, and lack written description support in the ’586 Application for the same
`
`reasons. The Challenged Claims are accordingly entitled to a priority date no earlier
`
`than June 2, 2008.3
`
`B.
`Level of Ordinary Skill in the Art
`As of June 2008 (or June 2007), a person of ordinary skill in the art
`
`(“POSITA”) in the ’833 Patent’s field would have been a person with a bachelor’s
`
`degree in materials science, electrical engineering, computer engineering, computer
`
`science, or in a related field and at least one year of experience with the design or
`
`development of semiconductor non-volatile memory circuitry or systems. See Dec.,
`
`¶¶ 48-52.
`
`
`3 As identified in §V.A.1-3, the references at issue herein are prior art even if the
`
`’833 Patent is entitled to claim priority to June 1, 2007.
`
`
`
`4
`
`Petitioners
`Ex. 1022, p. 4
`
`

`

`Petition for IPR re U.S. Patent No. 8,301,833
`
`C. Overview
`The ’833 Patent discloses a memory system that communicates with a host,
`
`such as a disk controller of a computer system. Ex. 1001, Abstract. The memory
`
`system can include volatile and non-volatile memory and a controller configured to
`
`backup the volatile memory using the non-volatile memory in the event of a trigger
`
`condition. Id. In order to power the system in the event of a power failure or
`
`reduction, the memory system can include a secondary power source such as a
`
`capacitor bank. Id. Figure 1 shows an example memory system:
`
`
`
`5
`
`
`
`Petitioners
`Ex. 1022, p. 5
`
`

`

`Petition for IPR re U.S. Patent No. 8,301,833
`
`Id., Fig. 1, 3:16-17; Dec., ¶¶ 57-58.
`
`The volatile memory system can be operated at a reduced frequency during
`
`backup and/or restore operations to improve efficiency of the system and save
`
`power. Ex. 1001, 4:41-44. Figure 9 depicts an example method of operating a
`
`volatile memory subsystem at a reduced rate in a backup mode:
`
`Id., Fig. 9, 3:45-48; see id., 17:39-18:13; Dec., ¶ 58.
`
`
`
`
`
`6
`
`Petitioners
`Ex. 1022, p. 6
`
`

`

`Petition for IPR re U.S. Patent No. 8,301,833
`
`D. Relevant Prosecution History
`During prosecution, the claims were initially rejected as obvious in view of
`
`the Li and Oshikiri references. Ex. 1002, 166-172. Netlist responded by arguing that
`
`the art merely showed “different processing speeds,” not “different memory
`
`subsystem operation frequenc[ies].” Id., 134-149. The Examiner disagreed,
`
`explaining that the claims were “not directed to the operating speed of a memory,
`
`but instead … to the operating speed of a memory subsystem.” Id., 123. Netlist
`
`submitted claim amendments in response, specifying a “first clock frequency,” a
`
`“second clock frequency,” and a “third clock frequency.” Id., 107-117.
`
`The claims were again rejected as obvious, over the Li and Cope references.
`
`Id., 59-73. The Examiner also rejected what are now claims 2 and 18 as indefinite
`
`because they recited “approximately equal” clock frequencies. Id. Netlist responded
`
`by amending the claims to replace the word “approximately” with “substantially,”
`
`stating that “in practice there will always be a difference” between clock frequencies.
`
`Id. Netlistalso argued that Cope “cannot be used to describe two modes of operation,
`
`where a DRAM in a first mode operates at a first clock frequency and in a second
`
`mode operates at another frequency.” Id., 71. The Examiner subsequently withdrew
`
`the rejections. Id., 1.
`
`Three previous IPR petitions (by third parties not related to Petitioners) were
`
`filed against the ’833 Patent. None of these prior petitions involved the Best
`
`
`
`7
`
`Petitioners
`Ex. 1022, p. 7
`
`

`

`Petition for IPR re U.S. Patent No. 8,301,833
`
`(Ex.1006) prior art that Petitioners rely upon as their primary prior art reference
`
`herein. In IPR2014-00994, filed by SanDisk Corporation, the Board construed the
`
`term “clock frequency” and ultimately denied review of claims 1-30 (Paper 8). In
`
`IPR2014-01370, filed by SMART Modular Technologies, the Board denied review
`
`of claims 1-30 (Paper 13). In IPR2017-00649, filed by SK hynix, the Board denied
`
`review of claims 1-30 (Paper 7).
`
`E. Related Patents
`U.S. Patent No. 8,874,831 (“’831 Patent”) resulted from Application No.
`
`13/559,476, filed July 26, 2012, a continuation-in-part of the ’916 Application (now
`
`the ’833 Patent). Like the ’833 Patent, the ’831 Patent alleges a claim of priority to
`
`the ’586 Application. The ’831 Patent’s Claim 15, which recites almost verbatim
`
`claims 1 and 15 of the ’833 Patent, was invalidated in a Final Written Decision by
`
`the Board as obvious over Best, Mills, and Bonella. See SK hynix Inc. et al. v. Netlist,
`
`Inc., IPR2017-00692, Paper 25 at 31-40 (PTAB July 5, 2018) (“’692 IPR”).4
`
`
`4 The ’692 IPR Final Written Decision also found claim 15 obvious over “Best,
`
`Mills, Roy, and Bonella” (Paper 25 at 40), but “Roy” was used to disclose elements
`
`not relevant to the present Petition and is not included as a ground herein.
`
`
`
`8
`
`Petitioners
`Ex. 1022, p. 8
`
`

`

`Petition for IPR re U.S. Patent No. 8,301,833
`
`IV. Claim Construction
`The Board construes claims under the same standard used in civil actions in
`
`federal district court. The district court for the related litigations has not yet
`
`construed the claim terms.
`
`The parties’ proposed constructions from the related litigations are set forth
`
`in Exs. 1012-1013. These construction disputes from the related litigations do not
`
`affect the outcome of this Petition with respect to any claim.
`
`The Board has previously construed, under the broadest reasonable
`
`interpretation standard, the claim term “clock frequency” to require “identification
`
`of a clock running at a particular frequency.” IPR2014-00994, Paper 8 at 6. This
`
`interpretation is consistent with the ’833 Patent’s specification. See, e.g., Ex. 1001,
`
`17:25-18:13; Dec., ¶ 136. Petitioners have applied this interpretation below and
`
`shown how the claims are invalid under any reasonable interpretation of the claim
`
`terms.
`
`V. Detailed Discussion of the Grounds for Unpatentability
`The Challenged Claims are unpatentable based on two grounds. Ground 1
`
`establishes that claims 1 and 15 are unpatentable under the doctrine of collateral
`
`estoppel. Ground 2 establishes that the Challenged Claims are obvious over Best in
`
`view of Bonella and Mills.
`
`
`
`9
`
`Petitioners
`Ex. 1022, p. 9
`
`

`

`Petition for IPR re U.S. Patent No. 8,301,833
`
`A. Overview of the Principal Prior Art
`1.
`Best (Ex. 1006)
`a.
`Prior Art Status
`Best was filed on October 15, 2009, is related to PCT/US08/60566, filed April
`
`17, 2008, and claims priority to a provisional application (60/912,321) (“’321
`
`Application”) (Ex. 1007) filed on April 17, 2007. Best is prior art under 35 U.S.C. §
`
`102(e) (pre-AIA) for two reasons. First, as explained above in §III.A, the earliest
`
`effective filing date of the ’833 Patent’s claims is June 2, 2008. Second, the ’321
`
`Application provides written description support for Best’s claims, therefore
`
`entitling Best to the priority date (April 17, 2007 filing date) of the ’321 Application.
`
`See Dynamic Drinkware, 800 F. 3d at 1381-82. Best is therefore prior art under §
`
`102(e) regardless of whether the ’833 Patent is entitled to its alleged June 1, 2007
`
`priority date.
`
`Best and the ’321 Application contain essentially identical written
`
`descriptions, as can be seen in Appendix A to Mr. Maltiel’s report (Ex. 1003). Best’s
`
`paragraphs correspond to the ’321 Application as follows (Dec., ¶ 68):
`
`Best (Ex. 1006)
`
`’321 Application (Ex. 1007)
`
`¶2
`¶¶3-11
`¶¶12-31
`¶¶32-33
`¶34
`
`
`
`
`
`10
`
`¶2
`¶3
`¶¶4-23
`¶24
`¶25
`
`Petitioners
`Ex. 1022, p. 10
`
`

`

`Petition for IPR re U.S. Patent No. 8,301,833
`
`The ’321 Application was also filed with the same 40 claims filed in Best,
`
`explicitly providing written description support for each claim, and includes the
`
`same set of figures. Compare Ex. 1006, claims 1-40, Figs. 1-7, with Ex. 1007, 27-
`
`29 (claims 1-40), 37-38 (Figs. 1-7).
`
`The ’321 Application provides written description support for each of Best’s
`
`claims. Each element of Best’s claim 1, for example, has written description support
`
`in the ’321 Application. For example, the ’321 Application discloses:
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`• a “memory device disposed within an integrated circuit (IC) package,”
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`see, e.g., Ex. 1007, ¶8; Dec., ¶ 71;
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`• “a first storage die having an array of volatile storage cells,” see, e.g.,
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`Ex. 1007, 37 (Fig. 2); Dec., ¶ 71;
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`• “a second storage die having an array of non-volatile storage cells,”
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`see, e.g., Ex. 1007, 37 (Fig. 2); Dec., ¶ 71;
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`• “a shared interface circuit to receive information associated with a
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`memory access operation to be performed within the memory device
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`and to select, according to the information, either the first storage die
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`or the second storage die to be accessed in the memory access
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`operation,” see, e.g., Ex. 1007, ¶¶7, 9; Dec., ¶ 71.
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`As Dr. Maltiel explains in greater detail in his expert declaration, each of
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`Best’s other claims are similarly supported in the ’321 Application to the same extent
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`Petition for IPR re U.S. Patent No. 8,301,833
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`and same manner as in Best. Dec., ¶¶ 72-111. Best is therefore entitled to the April
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`17, 2007 filing date of the ’321 Application and qualifies as § 102(e) prior art to the
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`’833 Patent.
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`b. Overview of Best
`Best discloses a composite, hybrid memory device including a first volatile
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`storage die and a second non-volatile storage die disposed within an integrated
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`circuit package. Best, Abstract. The device includes a shared interface circuit to
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`receive memory access commands directed to the first storage die and the second
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`storage die and to convey read and write data between an external data path and the
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`first and second storage dice. Id. Figure 1A illustrates an embodiment of this hybrid
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`memory device:
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`Id., Fig. 1A, ¶4; Dec., ¶ 112.
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`Petition for IPR re U.S. Patent No. 8,301,833
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`As shown in Figure 1A, the non-volatile storage IC 101 is implemented by a
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`Flash memory die, and the volatile storage IC 103 is implemented by a DRAM die.
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`Best, [0013]. This embodiment is further described by Figures 2 and 3. Dec., ¶¶ 113-
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`114. Best teaches that Figure 3 further describes the embodiment of Figure 2, which
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`itself further describes the embodiment of Figure 1A, such that Figures 1A, 2, and 3
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`describe a single embodiment. Id., ¶ 114. For example, Figure 1A illustrates “an
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`embodiment of a hybrid, composite memory device 100 having … shared-interface
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`IC 105.” Best, [0013]. Figure 1B illustrates an alternative embodiment that puts the
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`location of shared-interface 105 inside the Flash memory, but otherwise the shared
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`interface’s functionality is the same. Id., [0016]. Figure 2 “illustrates an embodiment
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`… with the shared interface circuitry shown in greater detail,” id., [0017] (emphasis
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`added), and thus further describes the shared interface described as part of Figure
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`1A. Figure 3 “illustrates an embodiment of a data control/steering circuit 150 that
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`may be used to implement the data control/steering circuit 131 of FIG. 2.” Id., [0021]
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`(emphasis added). Figure 3 (and its associated description) thus further describes the
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`functionality of Figure 2 (and its associated description), which itself further
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`describes the functionality of Figure 1A (and its associated description). Dec., ¶ 114.
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`Best discloses two alternative ways that memory addresses are mapped to the
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`volatile and non-volatile storage dies. In the Figure 4 hybrid storage embodiment,
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`“non-overlapping address ranges apply to each of the storage dice 101 and 103 to
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`form” a contiguous address space. Best, [0017]. In the alternative Figure 7 “Shadow
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`Operation” embodiment, “some or all of the volatile memory address range may
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`overlap with the non-volatile memory address range to enable an operation referred
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`to herein as memory shadowing.” Id., [0024]. A POSITA would understand that
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`Best’s functionality in Figures 1-3 would operate the same in the “Shadow
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`Operation” embodiment except that the address ranges may overlap so as to enable
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`memory shadowing as described. Dec., ¶ 115.
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`2.
`Bonella (Ex. 1008)
`Bonella, filed on December 8, 2006, claims priority to a provisional
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`application (11/635,926) filed on December 8, 2005. Bonella is thus prior art under
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`35 U.S.C. § 102(e) (pre-AIA).
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`Bonella discloses a memory module including a volatile memory, a non-
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`volatile memory, and a controller that provides address, data, and control interfaces
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`to the memories and to a host system, such as, for example, a personal computer.
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`Bonella, [0006]. Bonella teaches that this hybrid memory module fills the
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`performance gap between main memory and a hard disk drive, and “can reduce
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`overall power consumption on laptops.” Id., [0065]; Dec., ¶ 118.
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`Figure 1 is a high-level system block diagram of an illustrative memory
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`module of Bonella:
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`
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`Figure 1 shows an illustrative memory module with “an Express Card
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`Interface; a memory module controller; a DRAM memory; a FLASH memory; and
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`a voltage regulator (and/or one or more power transistors),” as well as “optional
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`Uninterruptible Power Supply (UPS) capacitors or battery (for emergency shut-
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`down operations); and various other electrical components … used for well-known
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`miscellaneous functions in electronic products such as memory modules.” Bonella,
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`[0029]; Dec., ¶¶ 119-120. Bonella discloses that the memory module implements
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`the DDR2 DRAM Specification and the NAND Flash Specification, but can be
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`modified
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`to
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`implement different
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`interfaces and conform with alternative
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`specifications. Bonella, [0036]-[0037]; Dec., ¶ 121.
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`Bonella teaches that using a combination of storage types can “gain dramatic
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`improvements in operational performance and storage capacity,” but that doing so
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`requires “special embedded operational functions” in order to allow the memory
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`module to operate independently so as to limit interference with normal system
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`operation. Bonella, [0025]. These functions include Flash write leveling, DRAM
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`write buffer flushing to Flash, Flash flushing to HDD, device failure management, a
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`power loss algorithm, security management, etc. Id., [0092]-[0108]; Dec., ¶ 122.
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`Bonella teaches that its hybrid memory includes a DRAM write buffer that is
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`occasionally backed up to the internal Flash memory to ensure data integrity in case
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`of a power loss. Id., [0096]. This write buffer flushing can be triggered by a power
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`loss event, which then causes Bonella’s “Power loss algorithm” to be executed. Id.,
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`[0101]. During the execution of the power loss algorithm, Bonella’s memory relies
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`on backup power such as, for example, power supply capacitors. Id., [0029]. The
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`memory maintains a sufficiently large power reserve to write the data to Flash
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`memory. Id., [0033]; Dec., ¶¶ 123-126.
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`Bonella also teaches that the hybrid memory module includes “Power State
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`Aware” functionality that allows the module to significantly reduce power
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`consumption when required. Bonella, [0045]. For example, Bonella teaches a
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`“Power Level 5” state that allows for full function, full performance operation. Id.,
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`[0047]. Bonella also teaches a “Power Level 4” s