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`SILICON PROCESSING
`FOR
`THE VLSI ERA
`
`VOLUME 1:
`
`PROCESS TECHNOLOGY
`
`Second Edition
`
`STANLEY WOLF Ph.D.
`
`RICHARD N. TAUBER Ph.D.
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`LATTICE PRESS
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`Sunset Beach, California
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`DISCLAIMER
`
`This publication is based on sources and information believed to be reliable, but the
`authors and Lattice Press disclaim any warranty or liability based on or relating lo the
`contents of this publication.
`
`Published by:
`
`LATTICE PRESS
`Post Office Box 340
`Sunset Beach, California 90742, U.S.A.
`
`Cover design by Roy Montibon, New Archetype Publishing, Los Angeles, CA.
`
`Copyright © 2000 by Lattice Press.
`All rights reserved. No part of this book may be reproduced or transmitted in any form
`or by any means, electronic or mechanical, including photocopying, recording or by any
`information storage and retrieval system without written permission from the publisher,
`except for the inclusion of brief quotations in a review.
`
`Library of Congress Cataloging in Publication Data
`Wolf, Stanley and Tauber, Richard N.
`
`Silicon Processing for the VLSI Era
`Volume l : Process Technology
`
`Includes Index
`I. Integrated circuits-Very large scale
`integration. 2. Silicon. I. Title
`
`ISBN 0-9616721-6-1
`
`9 8 7 6 5 4 3 2
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`PRINTED IN THE UNITED STATES OF AMERICA
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`DETAILED TABLE OF CONTENTS
`
`PREFACE
`PROLOGUE
`1. SILICON: SINGLE-CRYSTAL GROWTH & WAFER PREPARATION
`1.1 TERMINOLOGY OF CRYSTAL STRUCTURE, 1
`1.2 THE MANUFACTURE OF SINGLE-CRYSTAL SILICON, 5
`1.2.1 From Raw Material to Electronic Grade Polysilicon
`1.3 CZOCHRALSKI (CZ) CRYSTAL GROWTH, 8
`1.3.1 Czochralski Crystal Growth Sequence
`1.3.2 Incorporation of Impurities into the Crystal (Normal Freezing)
`1.3.3 Modifications Encountered to Normal Freezing in CZ Growth
`1.3.4 Czochralski Silicon Growing Equipment
`1.3.4.l Furnace
`1.3.4.2 Crystal Pulling Mechanism
`1.3.4.3 Ambient Control
`1.3.4.4 Control System
`1.3.5 Analysis of Czochralski Silicon in Ingot Form
`1.3.5.1 Oxygen & Carbon Measurements in Si Using IR Absorbance Spectroscopy
`1.4 FLOAT-ZONE SINGLE-CRYSTAL SILICON, 20
`1.5 FROM INGOT TO FINISHED WAFER: SLICING; ETCHING; POLISHING, 22
`1.6 SPECIFICATIONS OF SILICON WAFERS FOR ULSI, 25
`1.6.1 Electrical Specifications
`1.6.2 Mechanical/Dimensional Specifications
`1.6.3 Chemical/Structural Specifications
`1.6.4 Surface/Near Surface Specifications
`1.7 THE ECONOMICS OF SILICON WAFERS, 29
`1.8 TRENDS IN SILICON CRYSTAL GROWTH AND ULSI WAFERS, 31
`REFERENCES, 32
`PROBLEMS, 34
`2. CRYSTALLINE DEFECTS AND GETTERING
`2.1 CRYSTALLINE DEFECTS IN SILICON, 36
`2.1.1 Point Defects
`2.1.2 One-Dimensional Defects (Dislocations)
`2.1.3 Area Defects (Stacking Faults)
`2.1.4 Volume Defects
`2.1.4.1 Classical Homogeneous 3-D Nucleation Theory
`2.1.4.2 Nucleation of Volume Defects in Silicon Ingots
`2.2 INFLUENCE OF DEFECTS ON DEVICE PROPERTIES, 53
`2.2.1 Leakage Currents in pn Junctions
`2.2.2 Gate Oxide Quality
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`2.2.3 Wafer Resistance to Warpage
`2.3 CHARACTERIZATION OF CRYSTAL DEFECTS, 55
`2.4 OXYGEN IN SILICON, 57
`2.5 GETTERING, 58
`2.5.1 Basic Gettering Pinciples
`2.5.2 Extrinsic Gettering
`2.5.3 Intrinsic Gettering
`2.5.4 Gettering with Oxygen Precipitates
`2.5.5 Summary of Gettering
`REFERENCES, 67
`PROBLEMS, 69
`3. VACUUM TECHNOLOGY FOR ULSI APPLICATIONS
`3.1 FUNDAMENTAL CONCEPTS OF GASES AND VACUUMS, 70
`3.2 PRESSURE UNITS, 7 1
`3.3 VACUUM PRESSURE RANGES, 72
`3.3. J Mean Free Path and Gas Flow Regimes
`3.4 THE LANGUAGE OF GAS/SOLID INTERACTIONS, 73
`3.5 TERMINOLOGY OF VACUUM PRODUCTION AND PUMPS, 75
`3.5.1 Vacuum Pump Types
`3.5.2 Pumping Speed and Conductance
`3.5.3 Throughput
`3.6 ROUGH PUMPS, 8 1
`3.6. l Oil-Sealed Rotary Mechanical Pumps
`3.6.2 Vacuum Pump Oils for Semiconductor Processing
`3.6.3 Roots Pumps
`3.6.4 Dry Mechanical Pumps
`3.7 HIGH VACUUM PUMPS I: CRYOGENIC PUMPS, 87
`3.7.1 Cryopump Operation
`3.7.2 Cryopump Regeneration
`3.8 HIGH VACUUM PUMPS II: TURBOMOLECULAR PUMPS, 92
`3.9 TOTAL PRESSURE MEASUREMENT, 95
`3.9.1 Capacitance Manometers
`3.9.2 Thermocouple Gauges
`3.9.3 Pirani Gauges
`3.9.4 Ionization (High Vacuum) Gauges
`3. 10 MEASUREMENTS OF PARTIAL PRESSURE: Residual Gas Analyzers, 98
`3.10. l Operation of Residual Gas Analyzers (RGA)
`3.10.2 RGAs and Non-High Vacuum Applications: Differential Pumping
`3.10.3 Interpretation of RGA Spectra
`3.10.4 RGA Specification List
`REFERENCES, 102
`PROBLEMS, 103
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`104
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`119
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`CONTENTS
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`4. BASICS OF THIN FILMS
`4.1 THIN FILM GROWTH, 105
`4.1.1 Thin Film Nucleation
`4.1.2 The Structure of Thin Films
`4.2 MECHANICAL PROPERTIES OF THIN FILMS, 108
`4.2.1 Adhesion
`4.2.2 Stress in Thin Films
`4.2.3 Other Mechanical Properties
`4.3 ELECTRICAL PROPERTIES OF METALLIC THIN FILMS, 113
`4.3 .1 Measurement of the Electrical Properties of Thin Films
`4.3.2 Electrical Transport in Thin Films
`REFERENCES, 118
`PROBLEMS, 118
`5. CONTAMINATION CONTROL AND CLEANING TECHNOLOGY FOR ULSI
`5.1 TYPES OF CONTAMINATION IN IC FABRICATION, 119
`5.2 SOURCES OF CONTAMINATION IN IC PROCESSING, 120
`5.3 THE EFFECTS OF CONTAMINATION ON ULSI DEVICES, 121
`5.4 CONTAMINATION PREVENTION MEASURES, 122
`5.4.1. Cleanroom Design and Minienvironments
`5.4.2 Gowning Procedures
`5.4.3 Ultrapure Chemicals
`5.4.4 De-Ionized (DI) Water
`5.4.5 Machine-Design and Wafer Handling Techniques
`5.4.6 Process Modifications
`5.5 WAFER CLEANING TECHNIQUES FOR ULSI, 128
`5.5.1 Wet-Chemical Removal of Film Contaminants
`5.5.1.l FEOL Wet-Cleaning - RCA Clean
`5.5.1.2 Modifications to the RCA Clean
`5.5.1.3 Ozone-containing Water
`5.5.1.4 Wet Cleaning of Metal-Coated Wafers (BEOL)
`5.5.1.5 Spray Processing
`5.5.2 Vapor-Phase and Dry Cleaning
`5.5.2.1 Vapor-Phase Cleans
`5.5.2.2 Ozone/UV Dry Cleans
`5.5.3 Photoresist Removal
`5.6 PARTICLE REMOVAL, 134
`5.6.1 Vibrational Scrubbing (Ultrasonic and Megasonic)
`5.6.2 Particle Removal by Brush Scrubbing
`5.6.3 Particle Removal by Liquid Jet spraying
`5.6.4 Particle Removal by Cryosol Spray Techniques
`5.6.5 Particle Removal by DUV-Laser Irradiation
`5.7 RINSING AND DRYING WAFERS, 139
`5.7.1 Rinsing
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`5.7.2 Wafer Drying after Rinse
`5.7.2.l Spin-Dryers
`5.7.2.2 lsopropyl-Alcohol (IPA) Vapor Dryers
`5.7.2.3 Hot DI-Water Drying
`5.7.2.4 Marangoni Drying
`5.8 PARTICLE DETECTION ON WAFER SURFACES, 143
`5.8. l Automatic Laser Particle Counters for Detecting Particles on Wafers
`5.8.2 Automatic Defect Classification (ADC)
`REFERENCES, 146
`PROBLEMS, 148
`6. CHEMICAL VAPOR DEPOSITION of AMORPHOUS & POLYCRYSTALLINE FILMS 149
`6. 1 BASIC ASPECTS OFCHEMlCAL VAPOR DEPOSITION, 150
`6. I. I Grove's S implified CVD-Film-Growlh Model
`6.1.2 Gas Flow and Gas-Phase Mass Transfer
`6.1.2.1 Gas Flow in CVD Reactors
`6.1.2.2 The Stagnant Layer Model
`6. l.2.3 Boundary Layer Theory
`6.2 CHEMICAL VAPOR DEPOSJTION SYSTEMS, 162
`6.2. l Components of CVD Systems
`6.2. 1.1 Gas Sources and Delivery Systems for CVD
`6.2.1.2 Mass-flow Con1rollers
`6.2. 1.3 Heating Sources for CVD Reaction Chambers
`6.2.2 Terminology ofCYD Reactor Design
`6.2.3 Atmospheric Pressure CVD Reactors
`6.2.4 Low Pressure Chemical Vapor Deposition Reactors
`6.2.4. 1 Horizontal-Tube LPCVD Batch Reactors (Hot Wall)
`6.2.5 Plasma Enhanced CVD: Physics, Chemistry, & Reactor Desjgns
`6.2.S.1 Parallel-PJate Cold-Wall Batch PECVD Reactors
`6.2.5.2 Mini-Batch Radial Cold-Wall PECVD Reactors
`6.2.5.3 Single-Wafer Cold-Wall PECVD Reactors
`6.3 POLYCRYSTALLINE SILICON: PROPBRTIES and CVD METHODS, 180
`6.3. I Properties of Polysilicon Thin Films
`6.3. 1. 1 Physical Structure and Mechanical Properties of Poly-Si
`6.3.1.2 Electrical Properties of Polysilicon
`6.3.2 Chemical Vapor Deposilion of Polysilicon
`6.3.2.1 Deposition Parameters
`6.3.2.2 Structure of Polysilicon - Deposition Condition Dependence
`6.3.3 Doping Techniques for Polysilicon
`6.3.3. 1 Diffusion Doping of Polysilicon
`6.3.3.2 Io n Implantation Doping of Polysilicon
`6.3.3.3 In Situ Doping of Polysilicon
`6.4 PROPERTIES and DEPOSITION OF CVD Si02, 189
`6.4.1 Chemfoal Reactions for CVD Si0 2 Formation
`6.4. 1. l Low-Temperature Silane-Based CVD Si(½
`6.4.1.2 Medium-Temperature LPCVD TEOS Si02
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`6.4.1.3 Low-Temperature PECVD TEOS
`6.4.1.4 Ozone TEOS
`6.4.2 Step Coverage of As-Deposited CVD SiO2 Films
`6.4.3 CVD & Applications of Undoped and Doped SiO2 Films
`6.4.3.1 Undoped CVD SiO2
`6.4.3.2 Phosphosilicate Glass (PSG)
`6.4.3.3 Borophosphosilicate Glass (BPSG)
`6.5 PROPERTIES AND CHEMICAL VAPOR DEPOSITION OF SILICON NITRIDE, 202
`6.6 OTHER DIELECTRIC FILMS DEPOSITED BY CVD, 206
`6.6.1 Silicon Oxynitrides
`6.7 CVD OF METALS, SILICIDES, AND NITRIDES FOR ULSI APPLICATIONS, 207
`6.7.1 CVD of Tungsten (W)
`6. 7 .1.1 CVD Tungsten Chemistry
`6.7.1.2 Blanket CVD Wand Etchback
`6.7.2 Chemical Vapor Deposition of Tungsten Silicide (WSix)
`6. 7.3 CVD of Titanium Nitride (TiN)
`6.7.4 CVD of Aluminum
`REFERENCES, 220
`PROBLEMS, 224
`7 SILICON EPITAXIAL GROWTH and SILICON ON INSULATOR
`7.1 THE DEVICE APPLICATIONS OF EPITAXY, 226
`7.1.1. Why Do We Use CMOS Epitaxial Wafers?
`7.2 GROWTH OF EPITAXIAL LAYERS, 228
`7.2.1 Atomistic Model of Film Growth
`7.3 CHEMICAL REACTIONS USED IN SILICON EPITAXY, 230
`7.4 PROCESS CONSIDERATIONS FOR EPITAXIAL DEPOSITION, 233
`7.4.1 Silicon Precursors
`7.4.2 Doping of the Epitaxial Films
`7.4.3 Intentional Doping
`7.4.4 Unintentional Doping (Autodoping and Solid State Diffusion)
`7.5 DEFECTS IN EPITAXIAL FILMS, 238
`7.5.l Wafer Preparation
`7.5.2 Defects Induced During Epitaxial Deposition
`7.5.3 Pattern Shift, Distortion, and Washout
`7.6 LOW-TEMPERATURE EPITAXY PROCESSES, 243
`7.7 SELECTIVE EPITAXIAL GROWTH (SEG), 245
`7.8 EPITAXIAL DEPOSITION EQUIPMENT, 247
`7.9 CHARACTERIZATION OF EPITAXIAL FILMS, 251
`7. 9 .1 Optical Inspection of Epitaxial Film Surfaces
`7.9.2 Electrical Characterization
`7.9.3 Epitaxial Film Thickness Measurements
`7.9.4 Infrared Reflectance Measurement Techniques
`7.9.4.1 ASTM Technique of Epi Layer Thickness Measurement with IR Reflectance
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`225
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`7.9.5 Fourier-Transfonn Infrared (FTIR) Spectroscopy
`7.10 SILICON-ON-INSULATORS (SOI), 256
`7.10. 1 Silicon-on-Sapphire (SOS)
`7.10.2 SIMOX
`7.10.3 Wafer Bonding
`REFERENCES, 261
`PROBLEMS, 264
`8. THERMAL OXIDATION OF SINGLE-CRYSTAL SILICON
`8.1 THE PROPERTIES OF SILICA GLASSES, 267
`8.2 OXIDATION KINETICS: THE DEAL-GROVE MODEL, 268
`8.2. l The Deal-Grove (or Linear-Parabolic) Model
`8.3 FACTORS WHIC H AFFECT THE ONE-DIMENSIONAL OXIDATION RATE, 276
`8.3. l Crystal Orientation Effects on Oxide Growth Rates
`8.3.2 Dopant Effects on Oxidation Growth Rates
`8.3.3 Water Effects During Dry Oxidation
`8.3.4 The Dependence of Oxidation Rates on CWorinc
`8.3.5 Effect of Pressure on Oxidation Rates
`8.3.5.1 High Pressure Oxidation (HrPOX):
`8.3.5.2 Low Pressure Oxidation
`8.4 THE INITIAL OXIDATION STAGE AND THE GROWTH OF THIN OXIDES, 284
`8.4. l Experimental Results for Thin Oxide Growth
`8.4.2 Growing Thin Oxides
`8.5 THE NATURE OF THE Si-SiO2 INTERFACE, 288
`8.5.1 Pixed Oxide Charge
`8.5.2 Mobile Ionic Charge
`8.5.3 Interface Trap Charge
`8.5.4 Oxide Trapped Charge
`8.6 STRESS IN SILICON DIOXIDE, 296
`8.7 DOPANT IMPURITY REDISTRIBUTION DURING OXIDATION, 296
`8.8 OXIDATION OF POLYSILICON, 298
`8.9 THE OXIDA TJON OF SILICON NITRIDE, 299
`8. 10 THERMAL NITRIDATION OP SILICON AND SILICON DIOXIDE, 299
`8.11 TWO-DIMENSIONAL OXIDE-GROWTH EFFECTS, 300
`8.1 1. l Birds Beak Encroachment
`8.11.2 LOCOS Induced Gate Thinning
`8. 11.3 Trench Corner Rounding
`8.11.4 Gate Birds Beak
`8.12 OXIDATION SYSTEMS, 303
`8.12. 1 Thennal Budget
`8.12.2 Thermal Processing Equipment (Tools)
`8. 12.3 Furnaces
`8. I 2.4 Horizontal Furnaces
`8.12.5 Vertical Furnaces
`8. 12.6 Anatomy of a Vertical Furnace
`8. 12. 7 Fast-Ramp Furnaces
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`8.12.8 Rapid Thermal Processing
`8.12.9 RTP Systems
`8.12.10 High Pressure Oxidation (HIPOX) Systems
`8.13 THICKNESS MEASUREMENTS OF OXIDE FILMS, 314
`8.13.1 Optical Measurements of Oxide Film Thickness
`8.13.2 Electrical Measurement of Oxide Film Thickness
`8.13.3 Physical Thickness Measurement of Oxide Films
`8.14 TRENDS IN THIN OXIDE GROWTH, 317
`8.14.1 Limitations of Silicon Dioxide
`8.14.2 Reliability Limits for Thin Oxides
`8.14.3 Fowler Nordheim (F-N) Tunneling
`8.14 4 Alternative Gate Insulator Materials for MOSFETs
`REFERENCES, 320
`PROBLEMS, 322
`9. DIFFUSION in SILICON
`9.1 THE MATHEMATICS OF DIFFUSION, 325
`9.1.1 Fick's First Law
`9.1.2 Fick's Second Law
`9 .1.3 Solutions to Fick's Second Law
`9.1.3.1 Chemical Pre-Deposition
`9.1.3.2 Drive-In Diffusion
`9.1.3.3 Drive-In From An Ion Implantation Predeposition
`9 .1.4 Concentration Dependence of the Diffusion Coefficient
`9.2 DEFECTS AND DOPANT DIFFUSION, 322
`9.2.1 Point Defects in Silicon
`9.2.2 Temperature Dependence of the Diffusion Coefficient Under Intrinsic
`Conditions
`9.2.3 Intrinsic Diffusion Coefficients
`9.2.4 Fast Diffusers in Silicon
`9.3 ATOMISTIC MODELS OF DIFFUSION, 336
`9.4 DIFFUSION MODELLING, 339
`9.4.1 SUPREM III:
`9.4.2 SUPREM III Models for B, As, P, and Sb Diffusion
`9.4.3 Modeling Intrinsic Diffusion
`9.4.3.1 Boron
`9.4.3.2 Arsenic
`9.4.3.3 Phosphorus
`9.4.3.4 Antimony
`9.4.4 Modeling Extrinsic Diffusion
`9.4.5 Modeling Diffusion with SUPREM IV
`9.5 DIFFUSION IN POLYCRYSTALLINE SILICON, 346
`9.6 DIFFUSION IN SILICON DIOXIDE, 347
`9.6.1 Boron Penetration of Thin Gate Oxides
`9.7 ANOMALOUS DIFFUSION EFFECTS, 348
`9. 7 .1 Electric Field Enhancement
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`9.7.2 Emitter Push Effect
`9.7.3 Lateral Diffusion Under Oxide Windows
`9.7.4 Oxidation-Enhanced Diffusion (OED)
`9.7.5 Transient Enhanced Diffusion (IBO)
`9.8 DIFFUSION SYSIBMS AND DIFFUSION SOURCES, 357
`9.8.1 Advanced Diffusion Technologies
`9.8. 1.1 Rapid Vapor Doping (RVD)
`9.8.1.2 Gas Immersion Laser Doping (GILD)
`9.9 MEASUREMENT TECHNIQUES FOR DIFFUSED LAYERS, 359
`9.9. 1 Sheet Resistance Measurements
`9.9.2 Capacitance-Voltage (C-V) Measurements
`9.9.3 Spreadi_ng Resistance Profiling (SRP)
`9.10 JUNCTION DEPTH MEASUREMENTS: PHYSICAL TECHNIQUES, 363
`9.10. l Angle Lap and Stain
`9.10.2 Groove and Stain
`9.10.3 Secondary Ion Mass Spectroscopy
`9.10.4 Two-Dimensional Depth Profiling
`REFERENCES, 367
`PROBLEMS, 370
`10. ION IMPLANTATION for ULSI
`I 0.1 ADV ANT AGES (AND PROBLEMS) OF ION IMPLANTATION, 372
`10.1.1 Advantages
`l 0.1.2 Problems/Limitations of Ion Implantation
`10.2 IMPURITY PROFILES OF IMPLANTED IONS, 374
`10.2.1 Definitions Associated with Ion Implantation Profiles
`10.2.2 Theory of Ion Stopping
`10.2.3 Models for Implantation Profiles in Amorphous Solids
`10.2.3.1 Higher Moment Distributions for Implant Profiles in Amorphous Material
`10.2.4 Implanting Into Single Crystal Materials: Channeling
`'I0.2.5 Calculating Implantation Profiles: Boltzmann Transport Equation
`and Monte Carlo Approaches
`10.2.5.1 Monte Carlo Calculations
`10.3 ION IMPLANTATION DAMAGE ACCUMULATION & ANNEALING IN SILICON, 386
`10.3.l Implantation Damage in Silicon
`10.3.2 Primary Crystalline Defect Damage
`10.3.3 Amorphous Layer Damage
`10.3.4 Electrical Activation and Implantation Damage Annealing
`10.3.4.1 Electrical Activation of Implanted Impurities
`10.3.4.2 Annealing of Primary Crystalline Damage
`10.3.4.3 Annealing of Amorphous Layers
`10.3.4.4 Dynamic Annealing Effects
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`10.3.4.5 Diffusion of Implanted Impurities
`10.4 ION IMPLANTATION EQUIPMENT, 396
`10.4.1 Components of an Ion Implantation System
`10.4.2 Ion Implanter Types
`10.4.2.1 Medium-Current Im planters
`10.4.2.2 High-Current Implanters
`10.4.2.3 Low-Energy Implanters
`10.4.2.4 High-Energy Implanters
`10.4.2.5 High-Angle Im planters
`10.4.3 Ion Implantation Equipment System Limitations
`10.4.3.1 Elemental and Particulate
`10.4.3.2 Dose Monitoring Inaccuracies due to Beam Charge-state
`10.4.3.3 Implantation Mask Problems
`10.4.3.4 Wafer Charging During Implantation
`10.4.3.5 Machine-to-Machine Dose Matching
`10.4.3.6 "Scan Lock-Up" and Scanned-beam Machines
`10.4.3.7 Micro-Uniformity Dose Errors
`10.4.4 Ion Implantation Safety Considerations
`10. 5 CHARACTERIZATION OF ION IMPLANTATION, 412
`10.5.1 Measurement oflmplantation Dose and Dose Uniformity
`10.5 .1.1 Implantation Dose Measurements
`10.5.1.2 Implantation Dose Uniformity and Diagnosis of Implanter
`10.5.2 Measurement of Implantation Depth Profiles
`10.5.3 Measurement of Implantation Damage and Annealing Efficacy
`10.6 EXAMPLES OF ION IMPLANTATION PROCESS APPLICATIONS, 417
`10.6.1 Selecting Masking Layer Materials and Thickness
`10.6.2 Implanting Through Surface Layers
`10.6.3 Threshold-Voltage Control in MOS Devices
`10.6.4. Shallow Junction Formation by Ion Implantation
`10.6.5 High-Energy Implantation
`10.6 6 Fabrication of SOI materials
`10.6.7 New Techniques For Doping
`10.6.7.1 Molecular Ions
`10.6.7.2 Plasma Doping or Plasma Immersion Ion Implantation
`10.6.7.3 Laser Doping
`REFERENCES, 428
`PROBLEMS, 432
`11. ALUMINUM THIN FILMS AND PHYSICAL VAPOR DEPOSITION IN ULSI 434
`11.1 ALUMINUM THIN FILMS IN ULSI, 435
`11.2 SPUTTER DEPOSITION FOR ULSI, 438
`11.2.1 Introduction to Glow Discharge Physics
`11.2.2 The Creation of Glow Discharges
`11.2.3 Structure of Self-Sustaining Glow Discharges and Their Dark Spaces
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`11.2.4 Obstructed Glow Discharges & Dark-Space Shielding
`11.3 THE PHYSICS OF SPUTTERING, 443
`11.3. l The Billiard Ball Model of Sputtering
`11.3 2 Sputter Yield
`11.3.3 Selection Criteria for Process Conditions and Sputter Oas
`11.3.4 Secondary Electron Production for Sustaining the Discharge
`11.3.5 Sputter Deposited Film Growth
`11.3.6 Species that Strike the Wafer During Film Deposilfon
`11.4 RADIO-FREQUENCY (RF) GLOW DISCHARGES, 450
`11.5 MAGNETRON SPUTIERING, 456
`11.5. I Magnetron Sputter Sources for ULSI
`11.5.1.1 Evolution of Planar Circular Sputtering Sources
`11.5.1.2 Deposition Rate and Thickness Uniformity with Circular Planar Magnctrons:
`• 11.6 VLSI AND ULSI SPUTTER DEPOSITION EQUIPMENT, 461
`11.6. 1 The Components of a Generic Sputtering System
`11 .6.1 . 1 Sputtering Targets
`1.1.6. I .2 Vacuum Pumps for Sputtering Systems
`I I .6. 1.3 Power Supplies for Sputtering Systems
`11.6.1.4 The Gas Supply for Sputtering Systems
`11.6.2 Commercial Sputtering Systems for 125-mm and 150-mm Wafers
`11.6.3 Commercial Sputtering Systems for 200-mm Wafers
`1 l.7 PROCESS CONSIDERATIONS IN SPUTTER DEPOSITION, 468
`11.7. l Sputter Deposition of Alloy Films
`11.7.2 The Effects on the Sputter Process of the Transport of the Vaporized
`Atoms Between the Target and the Substrate
`11.7.3 Wafer Heating During Sputter Deposition
`11.7.4 Faceting and Trenching
`11.7.5 Particle Generation in Sputtering Processes
`11.7.6 Reactive Sputtering
`11.8 STEP COVERAGE & VIA/CONTACT HOLE FILLING BY SPUTTERING, 475
`11.8.1 Sputter Deposition of Barrier Layer Films into Contact Holes and Vias
`11.8.1.1 Sputter Deposition with Collimators
`11.8.1.2 Long-Throw Collimated sputtering
`11.8.1.3 Ionized Magnetron Sputter Deposition
`1 1.9 FUTURE TRENDS IN SPUTTER DEPOSITION PROCESSES, 483
`11.10 MET AL FILM THICKNESS MEASUREMENT, 483
`REFERENCES, 485
`PROBLEMS, 487
`12. LITHOGRAPHY I: OPTICAL PHOTORESIST and PROCESS TECHNOLOGY
`12.1 BASIC PHOTORESIST TERMINOLOGY, ·488
`12.2 PHOTORESIST MATERIAL PARAMETERS, 490
`12.2. 1 Resolution
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`488
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`12.2.1.1 Resolution - Contrast
`12.2.1.2 Resolution - Swelling, Proximity Effects, and Resist Thickness
`12.2.2 Sensitivity
`12.2.3 Etch Resistance and Thermal Stability
`12.2.4 Adhesion
`12.2.5 Solids Content and Viscosity
`12.2.6 Particulates and Metals Content
`12.2.7 Flash Point and TLV Rating
`12.2.8 Process Latitude and Consistency
`12.2.9 Shelf-Life
`12.3 OPTICAL PHOTORESIST MATERIAL TYPES, 500
`12.3 .1 Positive Optical Photoresists
`12.3.2 Negative Optical Photoresists
`12.3.3 Chemically-Amplified Deep-UV Resists
`12.3.4 Multilayer Resist Processes
`12.3.4. l Si-CARL Process
`12.3.5 Contrast Enhancement Layers
`12.3.6 Silylation-Based Processes for Surface Imaging
`12.3.6.1 DESIRE
`12.3.6.2 PRIME
`12.3. 7 The Predicted Role of Multilayer and Surface Imaging Technologies
`12.4 PHOTORESIST PROCESSING, 510
`12.4.1 Resist Processing: Dehydration Baking and Priming
`12.4.2 Resist Processing: Spin Coating
`12.4.3 Resist Processing: Soft-Bake
`12.4.4 Resist Processing: Exposure
`12.4.4.1 Standing Waves
`12.4.4.2 Linewidth Variation as Resist Crosses Steps
`12.4.4.3 Swing Curves and CD Variation with Resist Thickness
`12.4.2.4 Reflective Notching
`12.4.2.4 Dyed Photoresists
`12.4.2.6 Anti-Reflective Coatings (ARCs)
`12.4.2.7 Bottom Anti-Reflective Coatings (BARCs)
`12.4.2.8 Top Anti-Reflective Coatings (TARs)
`12.4.5 Resist Processing: Post-Exposure Bake
`12.4.6 Resist Processing: Development
`12.4. 7 Resist Processing: After-Develop Inspection
`12.4.7.1 Linewidth Variation and Control
`12.4.7.2 Linewidth Measurements
`12.4.8 Resist Processing: Post-Development-Bake
`12.4.9 Resist Processing: Photostabilization of Resists
`12.5 PHOTORESIST PROCESSING SYSTEMS, 538
`REFERENCES, 541
`PROBLEMS, 544
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`13. LITHOGRAPHY II: OPTICAL ALIGNERS and PHOTOMASKS
`13.l TIIB HISTORY (AND FUTURE) OF MICROLITHOGRAPHY, 546
`13.2 BASICS OF OPTICAL SCIENCE FOR MICROLITHOGRAPHY, 548
`13.2.1 Basic Terminology of Plane Waves of Light
`13.2.2 Diffraction, Numerical Aperture, and Resolution
`13.2.2.1 Resolution of the Optical System
`13.2.2.2 Resolution - The Rayleigh Criterion
`13.2.2.3 Resolution - The Optical Grating
`13.2.2.4 Resolution - Fourier Optics Perspective
`13.2.2.S Coherence in Optical Systems
`13.2.2.6 Resolution - Modulation Transfer Function
`13.2.2.7 Resolution - Impact of the Depth of Focus:
`13.2.2.8 A General Resolution Criterion - The Pocus-Exposure Process Window:
`13.2.3 Resolution Enhancement Techniques Involving the Stepper Optical System
`I 3.2.3. l Off-Axis Illumination:
`13.2.3.2 Multiple Exposures Through Focus (FLEX)
`13.3 PATTERN REGISTRATION, 582
`13.3.1 Definition of Alignment and Overlay
`13.3.2 Interfield and Intrafield Overlay Errors
`13.3.3 Intcrfield Errors
`13.3.4 Intraficld Errors
`13.3.5 Overlay Metrology
`13.4 OPTICAL LITHOGRAPHY EXPOSURE SYSTEMS, 588
`13.4.1 Light Sources and Illumination Systems for Optical Lithography
`13.4.1.1 Mercury Arc Lamps
`13.4.1.2 The Arc-Lamp Illumination System
`13.4.1.3 Excimer Laser DUY light Sources
`13.5 OPTICAL PROJECTION SYSTEMS, 595
`I 3.5.1 I: 1 Scanning Projection Aligners
`13.5.2 Reduction Step-and-Repeat Projection Aligners (Reduction Steppers)
`13.5.3 Non-Reduction Step-and-Repeat Projection Aligners (IX Steppers
`13.5.4 Step-and-Scan Projection Systems
`13.5.5 Stepper Wafer Handling System
`13.5.6 Temperature, Vibration, and Environmental Control of Steppers
`13.6 ALIGNMENT SYSTEMS IN STEPPERS, 605
`13.6.1 Off-Axis AJignment Systems
`13.6.2 Through-the-Lens Alignment Systems
`13.6.3 Alignment Marks and Their Detection
`13.6.4 Alignment Strategies
`13.7 MECHANICAL ASPECTS OF STEPPER WAFER STAGES, 610
`13.7.1 Wafer Stage Positioning and Wafer Chuck Design
`13.7.2 Automatic Focussing Systems in Steppers
`13.7.3 Automatic Leveling Systems
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`13.8 MASK AND RETICLE FABRICATION, 615
`13.8.1 Terminology and History of Photomasks
`13.8.2 Fabrication of Photomasks and Reticles
`13.8.2.1 Glass Quality and Preparation
`13.8.2.2 Glass Coating (Chrome)
`13.8.2.3 Mask Imaging (Resist Application and Processing)
`13.8.2.4 Pattern Generation
`13.8.3 Mask and Reticle Defects and Their Detection and Repair
`13.8.3.1 Repairing Defects in Masks and Reticles
`13.8.4 Pellicles
`13.8.4.1 Inspecting Masks and Reticles with Pellicles Attached
`13.8.5 Critical Dimension and Registration Inspection of Masks and Reticles
`13.8.6 Storage, Transport, and Loading of Reticles into the Stepper
`13.8.7 Optical Proximity Correction (OPC)
`13.8.8 Phase Shift Masks (PSM)
`13.9 MICROLITHOGRAPHY TRENDS, 635
`13.9.1 The Limits of Optical Lithography
`13.9.2 Non-Optical Microlithographic Technologies
`13.9.2.1 Electron Beam Direct-Write Lithography
`13.9.2.2 Electron Beam Projection Lithography (SCALPEL)
`13.9.2.3 Extreme Ultra-Violet Reflective Projection Lithography (EUV)
`13.9.2.4 Proximity X-Ray Lithography
`13.9.2.5 Ion-Beam Projection Lithography
`REFERENCES, 650
`PROBLEMS, 654
`14. DRY ETCHING FOR VLSI
`14.1 THE TERMINOLOGY OF ETCHING, 656
`14.1. l Bias, Tolerance, Etch Rate, and Anisotropy
`14.1.2 Selectivity, Over-Etch, and Feature Size Control
`14.1.3 Determining the Required Selectivity with Respect to Mask Materials, Sfm
`14.1.4 Determining Required Selectivity With Respect to Substrate, Sfs
`14.1.5 Combined Impact of the Requirements of Anisotropy and Selectivity
`14.1.6 Loading Effects and Microloading
`14.2 TYPES OF DRY-ETCHING PROCESSES, 666
`14.3 BASIC PHYSICS AND CHEMISTRY OF PLASMA ETCHING, 667
`14.3.1 The Reactive-Gas Glow Discharge
`14.3.2 Electrical Aspects of Glow Discharges
`14.3.3 Heterogeneous (Surface) Reaction Considerations
`14.3.4 Parameter Control in Plasma Processes
`14.4 ETCHING SILICON & SILICON DIOXIDE IN FLUOROCARBON PLASMAS, 673
`14.4.1 The Fluorine-to-Carbon-Ratio Model
`14.5 ANISOTROPIC ETCHING AND CONTROL OF EDGE PROFILE, 678
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`14.6 DRY-ETCHJNG VARIOUS TYPES OF MATERIALS IN ULSI APPLICATIONS, 681
`14.6.1 Silicon Dioxide (SiO2)
`14.6. 1.1 Shaping the Sidewlls of Contact Holes and Vias by Dry-Etching
`14.6. 1.2 Etching 0.25 µm (and Smaller) Contact Holes and Aspect-Ratio
`Dependent Etching Effects (ARDE)
`14.6.1.3 Via Veil Removal After Via Etching
`14.6.2 Silicon Nitride
`14.6.3 Polysilicon
`14.6.4 Refractory Metal Silicides and Polycides
`14.6.5 Aluminum and Aluminum Alloys
`14.6.6 Organic Films
`14.7 PROCESS MONITORING AND END POINT DETECTION, 696
`14.7. l Laser Interferometry and Laser Reflectance
`14.7.2 Optical Emission Spectroscopy
`14.8 DRY-ETCH EQUIPMENT CONFIGURATIONS, 698
`14.8.1 Batch Commercial D ry-Etch System Configurations
`14.8. 1.1 Barrel Etchers
`14.8.1.2 Parallel Electrode (Planar) Reactors
`14.8.1.3 Cylindrical Batch Etch Reactors (Hexode Etchers)
`14.8.2 Single-Wafer Etchers
`14.8.2.1 Single-Wafer Parallel Plate Reactors
`14.8.2.2 Magnetic-Enlianccd Reactive Ion Etchers (MREIH)
`14.8.2.3 Downstream Etchers
`14.8.3 High-Density Plasma Sources
`14.8.3.1 ECR Plasma Sources
`14.8.3.2 Helicon Plasma Sources
`14.8.3.3 Inductive (or Transformer) Coupled Plasma Sources
`14.8.3.4 Helical-Resonator Plasma Sources
`14.8.3.5 High Density Plasma Sources in ULSI Fabrication
`14.8.3.6 Electrostatic Chucks
`14.9 MISCELLANEOUS PROCESSING ISSUES RELATED TO DRY-ETCHJNG, 711
`14.9.l Plasma Etching Safety Considerations
`14.9.2 Contamination Arising from Dry-Etch Processes
`14.9.3 Damage Arising from Dry-Etch Processes
`14.9.3.1 Oxide Damage During Polysilicon or Metal Etch Processes
`REFERENCES, 7 15
`PROBLEMS, 718
`15. MULTILEVEL INTERCONNECTS for ULSI
`15. 1 THE NEED FOR MULTILEVEL-INTERCONNECT TECHNOLOGY, 719
`15. 1.1 Interconnect Limitations of ULSI
`15. L.1.1 Functional Density
`15.1.1.2 Propagatio n Delay
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`719
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`15.1.2 Problems Associated with Multilevel-Interconnect Processes
`15.1.3 Terminology of Multilevel-Interconnect Structures
`15.2 MATERIALS FOR MULTILEVEL INTERCONNECT TECHNOLOGIES, 724
`15.2.1 Conductor Materials for Multilevel Interconnects
`15.2.1.1 Requirements of VLSI Conductor Materials
`15.2.2 Dielectric Materials for Multilevel Interconnects
`15.2.2.1 Requirements of Dielectric Layers in Multilevel Interconnects
`15.3 PLANARIZATION OF INTERLEVEL DIELECTRIC LAYERS, 727
`15.3.1 Terminology of Planarization in Multilevel Interconnects
`15.3.1.1 Degree of Planarization
`15.3.1.2 The Need for Dielectric Planarization
`15.3.1.3 The Price of Increasing the Degree of Dielectric Planarization
`15.3.1.4 Design Rules Related to Intermetal Dielectric-Formation and Planarization
`15.3.2 Step-Height Reduction of Underlying Topography
`15.3.2.1 Provide a Semi-Planar Surface over Local-Interconnect Levels
`15.3.2.2 CVD Si02 and Bias-Sputter Etchback
`15.3.3 Planarization through Sacrificial-Layer Etchback
`15.3.3.l Sacrificial-Etchback Process Problems
`15.4 DOUBLE-LEVEL-METAL (DLM) INTERCONNECTS FOR 1-µm CMOS, 739
`15.5 CHEMICAL MECHANICAL POLISHING (CMP), 741
`15.5.1 The History of CMP
`15.5.2 Modeling the Mechanisms of CMP
`15.5.2.1 Metal CMP Mechanisms
`15.5.2.2 Silicon Dioxide CMP Mechanisms
`15.5.2.3 CMP of Low-k Dielectrics
`15.5.3 CMP Equipment
`15.5.3.1 CMP Polishing Tools
`15.5.3.2 CMP Consumables (Polishing Pads)
`15.5.3.3 CMP Consumables (Slurries)
`15.5.3.4 Slurry Distribution Systems
`15.5.3.5 Endpoint Detection
`15.5.3.6 Cleaning Issues in CMP
`15.5.3.7 CMP Metrology
`15.5.3.8 CMP Polisher Tool Reliability
`15.5.3.9 CMP Systems and Process Integration
`15.5.4 Miscellaneous Problems of CMP
`15.5.4.1 Dishing
`15.5.4.2 Thickness Non-Uniformity Within a Wafer After CMP
`15.5.4.3 Economic Considerations: Throughput and Cost of Ownership
`15.6 METAL DEPOSITION AND VIA FILLING, 770
`15.6.1 Conventional Approach to Contact and Via Fabrication
`15.6.2 Advanced Via Processing (Vertical Vias and Complete Filling of Vias by Metal)
`15.6.3 Processing Techniques that Allow for Vertical Vias
`15.6.3.1 CVD-W Plugs
`15.6.3.2 Filling Vias with Al Deposited by Sputtering
`15.6.3.3 Filling Vias by Electroplating of Cu
`15.7 TRIPLE-LEVEL-METAL (TLM) INTERCONNECTS FOR 0.5-µm CMOS, 779
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`15.8 COPPER FOR ULSI INTERCONNECTS, 779
`15.8.1 Process Integration Issues of Cu
`15.8.2 CVD of Copper (Cu)
`15.8.3 Electroplating and Electroless-Plating of Copper
`15.9 SPIN-ON GLASS (SOG), 785
`15.9. 1 SOG Process Integration:
`15.9.2 The Etchback SOG Process
`15.9.3 The Noo-Etchback SOG Process
`15.10 LOW-k DIELECTRICS, 791
`I 5.10.1 Process Integration Issues of Low-k Dielectrics
`15.10.2 First Generation Low-k Dielectrics (2.8 < k < 3.5)
`15.10.3 Second-Generation Low-k Dielectrics (2.5 < k < 2.8)
`15.10.3.1 2..s-Gen Spin-On Dielectrics with 2.5 < k< 2.8
`15.10.3.2 2nd Gen-CVD Dielectrics with 2.5 < k < 2.8
`15. 10.4 Ultra-Low-k Dielectrics (k < 2.0)
`15. 1 I HIGH-DENSITY-PLASMA CVD (HDP-CVD) OF DIELECTRIC FILMS, 795
`15.12 DAMASCENE AND DUAL-DAMASCENE INTERCONNECT STRUCTURES, 797
`15.13 DAMASCENE INTERCONNECT STRUCTURE FOR 0.25 µm CMOS, 799
`REFERENCES 801
`PROBLEMS 806
`16. CMOS PROCESS INTEGRATION
`16.1 INTRODUCTION TO CMOS TECHNOLOGY, 807
`16. 1.1 Historical Evolution of CMOS
`16. l.2 The Operation of CMOS Inverters
`16.2 PROCESS SEQUENCES FOR CMOS: 1.2 µm- 0.5 µm GENERATIONS, 8 I 6
`16.2.1 Starting Material
`16.2.2 Formation of Wells and Channel Stops:
`16.2.3 Definition of Active and Field Regions
`16.2.4 'Threshold-Adjust Implantation Step
`16.2.5 Gate Oxide Growth
`16.2.6 Polysilicon Deposition and Patterning
`16.2. 7 Formation of Source/Drain Regions
`16.2.8 Pre-metal Oxide Deposition and Contact Formation
`16.2.9 Metal Deposition and Patterning
`16.2.10 Intermetal Dielectric Deposition and Via Patterning
`16.2.11 Metal 2 Deposition and Patterning
`16.2.12 Passivation Layer and Pad Mask
`16.3 PROCESS FLOW FOR 0.25 µm CMOS, 828
`16.3.l Starting Material
`16.3.2 Formation of the Shallow-Trench-Isolation Structure
`16.3.3 Formation of Retrograde Wells and Carrying Out of VT-Adjust Implants
`16.3.4 Formation of the Gate Oxide
`16.3.5 Formation of the Gate-Stack Structures
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`16.3.6 Formation of the Source/Drain Junctions
`16.3.7 Salicide Formation
`16.3.8 Pre-metal Dielectric Deposition and Contact Formation
`16.3.9 Interconnect Structure Formation
`REFERENCES 838
`PROBLEMS 839
`17. ASSEMBLY AND PACKAGING FOR ULSI
`17.1 WAFER SORT, 841
`17.2 WAFER BACKSIDE PREPARATION, 842
`17.3 DIE SEPARATION, 842
`17.4 DIE ATTACH, 845
`17.4.1 Die-Attach-Related Reliability Issue