United States Patent 19
`Takagi
`
`|I||||III
`US005481688A
`5,481,688
`11) Patent Number:
`(45) Date of Patent:
`Jan. 2, 1996
`
`54 INFORMATION PROCESSING SYSTEM
`HAVING AN ADDRESSTRANSLATION
`TABLE LOADED WITH MAN/EXPANDED
`MEMORY PRESENCE BITS
`
`75 Inventor: Hitoshi Takagi, Tokyo, Japan
`(73) Assignee: NEC Corporation, Tokyo, Japan
`
`21 Appl. No.: 20,369
`(22 Filed:
`Feb. 22, 1993
`30
`Foreign Application Priority Data
`Feb. 21, 1992
`JP
`Japan .................................... 4-035198
`(51) Int. Cl. ................................. G06F 12/10
`52 U.S. Cl. ..................... 395/418; 395/419; 364/DIG. 1
`58 Field of Search ..................................... 395/425, 375,
`395/275, 400
`
`56
`
`References Cited
`U.S. PATENT DOCUMENTS
`4,279,014 7/1981 Cassonnet et al. ..................... 395/400
`4,476,524 10/1984 Brown et al. ........................... 395/425
`4,669,043 5/1987 Kaplinsky ...
`... 395/425
`5,129,070 7/1992 Dorotte .........
`... 395/400
`5,182,799
`l/1993 Tamura et al. .......................... 395/400
`5,233,700 8/1993 Takagi ..................................... 395/400
`5,237,668 8/1993 Blandy et al. .......................... 395/400
`5,347,636 9/1994 Ooi et al. ............................ 395/400X
`FOREIGN PATENT DOCUMENTS
`0214870 3/1987 European Pat. Off..
`
`
`
`OTHER PUBLICATIONS
`Enterprise System Architecture/390 Principles of Operation
`Publication No. IBM SA22-720-0, Oct. 1990, pp. 7-39 to
`7-41.
`
`Primary Examiner-Michael A. Whitefield
`Attorney, Agent, or Firm-Foley & Lardner
`
`ABSTRACT
`57
`An information processing system has a main memory unit,
`an expanded memory unit, and an instruction processing
`unit producing a virtual address. An address translation
`table, namely, a page table stores page table words which
`include main/expanded memory presence bits indicating to
`which memory unit of the main memory unit and the
`expanded memory unit real pages are stored. Preferably, the
`instruction processing unit may include an access type
`determiner for determining an access type for at least one
`operand. The access type indicates which memory unit is the
`optimum one for the operand. Instead of the access type
`determiner, the instruction processing unit may include
`segment descriptor registers for storing segment descriptors
`having expanded memory bits indicating which memory
`units are the optimum ones for the segments. In place of the
`access type determiner, the instruction processing unit may
`include virtual space registers for indicating virtual space
`numbers identifying a plurality of virtual spaces and an
`access type determining circuit for determining which
`memory unit is the optimum one for a designated virtual
`space.
`
`4 Claims, 10 Drawing Sheets
`
`223,
`
`208
`207
`II SERE
`
`FOR 1ST OPERAND
`FOR ST
`228 OPERAND
`
`FOR2ND OFPERAND
`
`FOR2ND
`OPERAND
`
`ACCESS TYPE. O. MAN MEMORY ACCESS
`ACCESS TYPE - 1 EXPANDED MEMORY ACCESS
`
`LzLabs GmbH. Ex. 1023-1
`
`

`

`U.S. Patent
`
`Jan. 2, 1996
`
`Sheet 1 of 10
`
`5,481,688
`
`(IP)
`
`INSTRUCTION
`PROCESSING UNIT
`
`ADDRESS
`TRANSLATION UNIT
`
`21
`
`
`
`
`
`
`
`
`
`
`
`
`
`EXPANDED
`MEMORY UNIT
`
`LzLabs GmbH. Ex. 1023-2
`
`

`

`U.S. Patent
`
`Jan. 2, 1996
`
`Sheet 2 of 10
`
`5,481,688
`
`
`
`INSTRUCTION
`1st 8:ERAND
`2NESEIRD2
`
`15 1
`
`y2
`
`2. 200
`2O
`-?'
`
`DONT CARE
`
`OP : INSTRUCTION CODE
`Xi INDEX REGISTER NUMBER FOR OPERAND i
`Di : SEGMENT DESCRIPTOR REGISTER NUMBER FOR OPERAND i
`yi: ADDRESS FOR OPERAND i
`L. : TRANSFER LENGTH SPECIFYING REGISTER NUMBER
`
`
`
`MNEMONIC
`
`OOOOOO 101
`OOOOOO 1111
`
`MOVE MAN MEMORY TO
`EXPANDED MEMORY PAGED
`MOVE EXPANDED MEMORY TO
`MAIN MEMORY PAGED
`
`LOGIC FOR ACCESS TYPE DETERMINER
`OP = OOOOOO 1101 --> ST OPERAND MAIN MEMORY ACCESS
`2ND OFPERAND EXPANDED MEMORY ACCESS
`OP = 000 0001111 -> 1ST OPERAND EXPANDED MEMORY ACCESS
`2ND OFERAND MAN MEMORY ACCESS
`
`F. G. 2
`
`LzLabs GmbH. Ex. 1023-3
`
`

`

`U.S. Patent
`
`Jan. 2, 1996
`
`Sheet 3 of 10
`
`5,481,688
`
`200
`
`
`
`202
`201
`D2 y2
`x2 op. xID y
`--
`--
`SEGMENT DESCRIPTOR REGISTERS 206
`20||NDEX REGISTERS
`24RFF 2O7
`208
`fEEFI E
`205 H || |
`|
`| 21o
`VIRTUAL SPACE
`H- YS
`REGISTERS (WSR)
`212 N.
`213
`
`
`
`
`
`
`
`
`
`
`
`OOOOOO 1101
`1111
`
`2.
`0
`1
`O
`
`1
`0 DETERMI
`NER
`
`219
`217
`WSNP OFFSET
`OFFSET
`P:
`WSN
`VIRTUAL ADDRESS AccESS TYPE VIRTUAL ADDRESS ACCESS TYPE
`FOR 1ST OPERAND
`FOR 2ND OFERAND
`FOR 2ND
`FOR 1ST
`228 OPERAND
`OPERAND
`TRANSFER DATA ENGTH
`ACCESS TYPE - O MAIN MEMORY ACCESS
`ACCESS TYPE - 1 EXPANDED MEMORY ACCESS
`
`220
`
`F. G. 3
`
`LzLabs GmbH. Ex. 1023-4
`
`

`

`U.S. Patent
`
`Jan. 2, 1996
`
`Sheet 4 of 10
`
`5,481,688
`
`F. G. 4A
`
`O
`
`
`
`20
`
`29 32
`
`FG. 4B
`MEANING OF FLAG FIELD
`
`BIT 20
`21
`22
`23
`24
`25
`26
`27
`28
`
`MEANING OF '1"
`READABLE
`WRITABLE
`EXPANDED MEMORY BIT
`LOADING FOR CACHE MEMORY
`EXTENDED VIRTUAL SPACE MODE
`EXECUTABLE
`PRIVLEGE
`BOUND FELD IS WALD
`PRESENCE OF SEGMENT
`
`LzLabs GmbH. Ex. 1023-5
`
`

`

`U.S. Patent
`
`Jan. 2, 1996
`
`Sheet S of 10
`
`5,481,688
`
`101
`
`VIRTUAL ADDRESS (VA)
`
`PDBR: PAGE TABLE
`DIRECTORY
`BASE
`REGISTER
`WSPTD VIRTUAL
`SPACE
`PASEABLE
`DIRECTORY
`PTB : PAGEABLE'
`BASE
`PT PAGE TABLE
`
`
`
`MAIN MEMORY
`REAL PAGES
`
`-
`
`EXPANDED MEMORY
`REAL PAGES
`
`-
`
`LzLabs GmbH. Ex. 1023-6
`
`

`

`U.S. Patent
`
`Jan. 2, 1996
`
`Sheet 6 of 10
`
`5,481,688
`
`F.G. 6A
`
`O
`MAN MEMORY REAL PAGE ADDRESS
`
`27 293031 35
`of c
`
`F.G. 6B
`
`O
`
`EXPANDED MEMORY REAL
`PAGE ADDRESS
`
`27 29.30 31 35
`P C
`
`LzLabs GmbH. Ex. 1023-7
`
`

`

`U.S. Patent
`
`Jan. 2, 1996
`
`Sheet 7 of 10
`
`5,481,688
`
`O
`
`27 29 3031 35
`
`EP c - PTw
`
`305
`PAGE PRESENCE
`CHECK CKT
`
`OK OR MPF OR SF
`
`MPF : MISSING PAGE FAULT
`SF SECURITY FAULT
`
`F. G. 7
`
`
`
`LzLabs GmbH. Ex. 1023-8
`
`

`

`5,481,688
`
`agvsay—>Jd
`
`ALIYM—Wh=adi
`
`
`
` SUYM—A—qgvsyO=a4i0=ONGJI
`
`6Old
`
`U.S. Patent
`
`WOu4dNOS
`
`Jan. 2, 1996
`
`Sheet 8 of 10
`
`€¢ WaWW
`
`LzLabs GmbH. Ex. 1023-9
`
`LzLabs GmbH. Ex. 1023-9
`
`

`

`U.S. Patent
`
`Jan. 2, 1996
`
`Sheet 9 of 10
`
`5,481,688
`
`200
`201
`202
`-XCPIXIDI-IID I
`INDEX REGISTERS
`
`2O3 254 N
`227
`
`
`
`VIRTUAL SPACE La E
`FEERs is
`212s
`213-
`
`\ Y - Y /
`
`y2
`
`215
`
`VY-Y /
`
`217
`/? WSN PI offset
`off SET
`WSN P
`ACCESS TYPE VIRTUAL ADDRESS ACCESS TYPE
`VIRTUAL ADDRE
`FOR 1ST
`FOR 2ND OPERAND
`FOR 2ND
`FOR ST OPERAND
`228 OPERAND
`OPERAND
`
`220
`
`TRANSFER DATA LENGTH
`
`ACCESS TYPE - O MAN MEMORY ACCESS
`ACCESS TYPE 1 EXPANDED MEMORY ACCESS
`
`FG. IO
`
`LzLabs GmbH. Ex. 1023-10
`
`

`

`U.S. Patent
`
`Jan. 2, 1996
`
`Sheet 10 of 10
`
`5,481,688
`
`200
`201
`X: OPT KID Y I
`--
`20INDEX REGISTERS
`2: F. 20;
`
`22
`
`
`
`2O2
`ILID: y
`--
`SEGMENT DESCRIPTOR REGISTERS 206
`-208
`
`
`
`209
`
`10
`
`VIRTUAL SPACE L
`REGISTERS (WSR) H
`212-Ea
`213
`
`
`
`
`
`V Y -
`
`1 /
`
`
`
`V 1
`
`y2 21b
`1/
`215
`
`WSN P
`
`217
`219
`off SEth-2WSNI PI6ffset
`
`VIRTUAL ADDRESS ACCESS TYPE VIRTUAL ADDRESS ACCESS TYPE
`FOR 1ST OPERAND
`FOR ST
`FOR 2ND OPERAND
`FOR 2ND
`228 OPERAND
`OPERAND
`
`220
`
`ACCESS TYPE - O MAIN MEMORY ACCESS
`ACCESS TYPE is 1 EXPANDED MEMORY ACCESS
`
`F. G.
`
`LzLabs GmbH. Ex. 1023-11
`
`

`

`5,481,688
`
`1
`INFORMATION PROCESSING SYSTEM
`HAVING AN ADDRESS TRANSLATION
`TABLE LOADED WITH MAN/EXPANDED
`MEMORY PRESENCE BITS
`
`10
`
`15
`
`BACKGROUND OF THE INVENTION
`This invention relates to an information processing sys
`tem and, in particular, to a method of designating an area for
`storing data and a mapping of a virtual space to a real
`memory unit.
`As is well known in the art, an expanded memory unit
`(EXPMEM) is a storage arrangement positioned between a
`main memory unit (MN MEM) and an external memory unit
`(EXT MEM) such as a disk. A combination of the main
`memory unit and the expanded memory unit is referred to as
`the real memory unit. The expanded memory unit can only
`be operable at an access speed lower than that of the main
`memory unit, though the storage capacity thereof is much
`20
`larger than that of the main memory unit. It is expected that
`the performance of the information processing system will
`be improved by using the expanded memory unit as the area
`for storing the data which is so far stored in the external
`memory unit. For example, the expanded memory unit can
`be used as a temporary memory for a file or a swapped area
`for virtual memory control.
`It is assumed that the main memory unit is operable at a
`main access speed AS(MN) and has a main storage capacity
`SC(MN), the expanded memory unit is operable at an
`expanded access speed AS(EXP) and has an expanded
`storage capacity SCOEXP), and the external memory unit is
`operable at an external access speed AS(EXT) and has an
`external storage capacity SC(EXT). The following relation
`ships generally hold for the access speed and the storage
`capacity of the main memory unit, the expanded memory
`unit and the external memory unit:
`AS(MN)2AS(EXP)2ASOEXT), and
`
`25
`
`30
`
`35
`
`SC(MN)sSC(EXP)sSC(EXT).
`The expanded memory unit is assigned with addresses
`which are independent of those assigned to the main
`memory unit. The addresses assigned to the main memory
`unit are called main memory real addresses while the
`addresses assigned to the expanded memory unit are referred
`to as expanded memory real addresses.
`Inasmuch as the main memory unit, the expanded
`memory unit and the external memory unit are related to
`each other, it is necessary to effectively control allocation of
`data among those memory units in order to improve the
`performance of the information processing system while
`taking a full advantage of the expanded memory unit. With
`respect to this, the present invention is directed to provide a
`control arrangement which enables the effective control for
`allocating the data and, in particular, to provide a control
`arrangement which enables the effective control even when
`the virtual space control, which is only for the main memory
`unit in the prior art, is also applied to the expanded memory
`unit.
`The U.S. Pat. No. 4476,524 issued to Brown et al
`discloses some prior art regarding the method for controlling
`memory contents stored in the expanded memory unit and
`how a programmer recognizes addresses in the expanded
`memory unit. The prior art disclosed in the above-mentioned
`patent allows the programmer to recognize only real
`addresses of addresses in the expanded memory unit. In the
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`information processing system providing multiprogram
`ming where a plurality of programs are run by a plurality of
`users, a control program (for instance, an operating system)
`for controlling the information processing system controls
`the memory contents in the expanded memory unit. A
`method of controlling the memory contents in the expanded
`memory unit by the control program is as follows:
`1. A user or a program who would like to access the
`memory contents stored in the expanded memory unit
`requests that of the control program.
`2. The control program checks justice of the request from
`the user or the program who sent the request, following
`which it provides access.
`As is apparent from the above description, whenever the
`user or the program accesses the memory contents stored in
`the expanded memory unit, the prior art disclosed in the
`above patent requires him or it to do so via the control
`program. As a result, it takes a long time for processing the
`memory contents stored in the expanded memory unit in the
`prior art, which only results in degradation of the processing
`performance.
`A virtual storage control system allows the main memory
`unit to enlarge a logical storage space, to protect the stored
`contents, to use data among programs in common, and to
`effectively use resources by reallocating data on the real
`memory unit. Through the above-mentioned method of
`controlling the memory contents stored in the expanded
`memory unit via the control program, degraded performance
`of the system will result because of the necessity of doing it
`via the control program.
`If it is possible to apply the virtual storage control system
`which is, at present, only for the main memory unit to the
`expanded memory unit and allow the system to control data
`by a single control system, it is expected to build a fast, high
`security, flexible information processing system while tak
`ing full advantage of the main memory unit, the expanded
`memory unit and the external memory unit.
`One example of applying a conventional virtual storage
`control system to the expanded memory unit is disclosed in
`a reference SA22-7201-0 issued by International Business
`Machines Corporation (October 1990), pages 7-39 to 7-41,
`under the title of "Enterprise Systems Architecture/390:
`Principles of Operation'. An information processing system
`disclosed in the above-mentioned reference comprises a
`page table (an address translation table) for storing page
`table words where the correspondence is defined between
`virtual page addresses and main memory page addresses.
`That is, the information processing system carries out
`address translation for translating a virtual page address into
`a main memory page address by using the page table. When
`a real page corresponding to a virtual page search is absent
`in the main memory unit, a page-invalid bit in the page table
`represents "1". In such a case, the information processing
`system carries out additional address translation to deter
`mine to which unit the real page in question is to be stored,
`the expanded memory unit or the external memory unit.
`Thus, this technique requires the additional address transla
`tion on accessing the contents stored in the expanded
`memory unit or the external memory unit. In addition, a
`system control program is activated when the real page is
`absent in the main memory unit. This program is substan
`tially modified as a result of the additional address transla
`tion. Such modification is, however, accompanied by deg
`radation of performance of the program itself. The
`performance of this program has important effects on that of
`the information processing system and therefore the addition
`address translation adversely affects the performance of the
`information processing system.
`The access of the page table or, if necessary, the subse
`quent additional address translation only reveals in which
`memory units is the real page stored. The memory unit
`
`LzLabs GmbH. Ex. 1023-12
`
`

`

`5,481,688
`
`3
`storing the real page in question is, however, not always the
`optimum one for it. Another processing is required for
`determining the optimum memory unit for the real page in
`accordance with attributes of data (operands) and frequency
`of access. Thus, it is desired to provide means enabling
`judgement in which memory units should be the data to be
`accessed by a program stored.
`SUMMARY OF THE INVENTION
`It is therefore an object of this invention to provide an
`information processing system which enables systematic
`control of an expanded memory unit as well as a main
`memory unit based on a virtual storage control system.
`It is another object of this invention to provide an infor
`nation processing system of the type described, which is
`capable of effectively reallocating stored contents between
`the main memory unit and an external memory unit at a high
`speed.
`Other objects of this invention will become clear as the
`description proceeds.
`According to a first aspect of this invention, an informa
`tion processing system comprises a main memory unit
`operable at a relatively high speed and having a relatively
`Small storage capacity, and an expanded memory unit oper
`able at a relatively low speed and having a relatively large
`Storage capacity, a combination of the main memory unit
`and the expanded memory unit being operable as a real
`memory unit. The information processing system further
`comprises an instruction processing unit producing a virtual
`address, and an address translation table for translating the
`virtual address into a real address. The address translation
`table stores page table words, each of which includes a real
`page address corresponding to a virtual page address, a
`main/expanded memory presence bit corresponding to the
`real page address and a page presence bit corresponding to
`the real page address. The main/expanded memory presence
`bit indicates to which memory unit of the main memory unit
`and the expanded memory unit a real page, indicated by the
`real page address is to be loaded.
`The page presence bit indicates whether the real page is
`present in the real memory unit. The main memory unit is
`accessible when the main/expanded memory presence bit
`indicates that the real page should be stored in the main
`memory unit and the page presence bit indicates presence of
`the real page in the real memory unit. The expanded memory
`unit is accessible when the main/expanded memory presence
`bit indicates that the real page should be stored in the
`expanded memory unit and when the page presence bit
`indicates presence of the real page in the real memory unit.
`The real page is loaded into the main memory unit after
`production of a missing page fault when the main/expanded
`memory presence bit indicates that the real page should be
`stored in the main memory unit and when the page presence
`bit indicates absence of the real page in the real memory
`unit. The real page is loaded into the expanded memory unit
`after production of the missing page fault when the main/
`expanded memory presence bit indicates that the real page
`should be stored in the expanded memory unit and the page
`presence bit indicates absence of the real page in the real
`memory unit.
`According to a second aspect of this invention, an infor
`mation processing system comprises a main memory unit
`operable at a relatively high speed and having a relatively
`Small Storage capacity, an expanded memory unit operable
`at a relatively low speed and having a relatively large storage
`capacity, and an instruction processing unit for processing an
`
`55
`
`60
`
`65
`
`O
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`4
`instruction word for accessing at least one operand to
`produce a virtual address. A combination of the main
`memory unit and the expanded memory unit is operable as
`a real memory unit. The instruction processing unit includes
`access type determining means for determining an access
`type for the at least one operand on the basis of information
`included in the instruction word. The access type indicates
`which memory unit of the main memory unit and the
`expanded memory unit is the optimum one for the at least
`one operand. The access type determining means produces
`an access type bit indicating the access type. An address
`translation table translates the virtual address into a real
`address. The address translation table stores page table
`words, each of which include a real page address corre
`sponding to a virtual page address, a main/expanded
`memory presence bit corresponding to the real page address,
`and a page presence bit corresponding to the real page
`address. The main/expanded memory presence bit indicating
`to which memory unit of the main memory unit and the
`expanded memory unit a real page is to be loaded. The page
`presence bit indicates whether the real page is present in the
`real memory unit. The main memory unit is accessible when
`the main/expanded memory presence bit indicates that the
`real page should be stored in the main memory unit and the
`page presence bit indicates presence of the real page in the
`real memory unit. The expanded memory unit is accessible
`when the main/expanded memory presence bit indicates that
`the real page should be stored in the expanded memory unit
`and when the page presence bit indicates presence of the real
`page in the real memory unit. The real page is loaded into the
`main memory unit after production of a missing page fault
`when the main/expanded memory presence bit indicates that
`the real page should be stored in the main memory unit and
`when the page presence bit indicates absence of the real page
`in the real memory unit. The real page is loaded into the
`expanded memory unit after production of the missing page
`fault when the main/expanded memory presence bit indi
`cates that the real page should be stored in the expanded
`memory unit and the page presence bit indicates absence of
`the real page in the real memory unit.
`According to a third aspect of this invention, an informa
`tion processing system comprises a main memory unit
`operable at a relatively high speed and having a relatively
`Small storage capacity, an expanded memory unit operable
`at a relatively low speed and having a relatively large storage
`capacity, and an instruction processing unit including seg
`ment descriptor registers for storing segment descriptors
`defining segments which are logical data blocks. The seg
`ment descriptors include start virtual addresses, segment
`sizes, and expanded memory bits indicating which of the
`main memory unit and the expanded memory unit is the
`optimum one for the segments.
`According to a fourth aspect of this invention, an infor
`mation processing system comprises a main memory unit
`operable at a relatively high speed and having a relatively
`Small storage capacity, an expanded memory unit operable
`at a relatively low speed and having a relatively large storage
`capacity and an instruction processing unit including means
`for indicating virtual space numbers for identifying a plu
`rality of virtual spaces and means for specifying which of the
`main memory unit or the expanded memory unit is the
`optimum one for holding information which resides in a
`designated virtual space.
`BRIEF DESCRIPTION OF THE DRAWING
`FIG. 1 is a block diagram of a central processing system
`of a single processor in an information processing system to
`which the present invention is applicable;
`
`LzLabs GmbH. Ex. 1023-13
`
`

`

`5,481,688
`
`S
`FIG. 2 shows a format of a data transfer instruction for
`transferring data between a main memory unit and an
`expanded memory unit, in which the data transfer instruc
`tion is executed on the central processing system depicted in
`FIG. 1;
`FIG. 3 is a block diagram of an instruction processing unit
`used in the central processing system depicted in FIG. 1;
`FIG. 4A shows a format of a segment descriptor stored in
`a segment descriptor register for use in the instruction
`processing unit depicted in FIG. 3;
`FIG. 4B shows a format of a Flag field of the segment
`descriptor illustrated in FIG. 4A;
`FIG. 5 is a block diagram for use in describing operation
`of address translation in the information processing system
`according to the present invention;
`FIG. 6A shows a format of a page table word (PTW) for
`the main memory unit for use in the central processing
`system depicted in FIG. 1;
`FIG. 6B shows a format of another page table word
`(PTW) for the expanded memory unit for use in the central
`processing system depicted in FIG. 1;
`FIG. 7 is a view for use in describing operation of
`presence check on the basis of an access type and a main/
`25
`expanded memory presence bit E and a page presence bit P
`both of which are included in a page table word (PTW);
`FIG. 8 is a circuit diagram of a page presence check
`circuit depicted in FIG. 7;
`FIG. 9 is a block diagram of a memory control unit used
`in the central processing system depicted in FIG. 1;
`FIG. 10 is a block diagram of another instruction pro
`cessing unit used in the central processing system depicted
`in FIG. 1; and
`FIG. 11 is a block diagram of still another instruction
`processing unit used in the central processing system
`depicted in FIG. 1.
`
`15
`
`10
`
`20
`
`30
`
`35
`
`6
`memory control unit 23 receives readout data/status from the
`main memory unit 24 via a readout data/status bus 61. The
`memory control unit 23 supplies the main memory unit 24
`with writing data via a writing data bus 62. The memory
`control unit 23 supplies the expanded memory unit 25 with
`an expanded memory address EMA and a command via an
`address bus 63 and a command bus 64, respectively. The
`memory control unit 23 receives readoutdata/status from the
`expanded memory unit 25 via a readout data/status bus 65.
`The memory control unit 23 supplies the expanded memory
`unit 25 with writing data via a writing data bus 66.
`FIG.2 shows a format of a data transfer instruction. The
`data transfer instruction is an instruction for carrying out
`data transfer between the main memory unit 24 and the
`expanded memory unit 25 that is executed on the central
`processing system depicted in FIG. 1. In the example being
`illustrated, the data transfer instruction is classified into two
`instructions, that is, a first data transfer instruction indicative
`of transfer of data from the main memory unit 24 to the
`expanded memory unit 25 and a second data transfer instruc
`tion indicative of transfer of data from the expanded
`memory unit 25 to the main memory unit 24. The first data
`transfer instruction is called an MMEP instruction while the
`second data transfer instruction is referred to as an MEMP
`instruction. Each data transfer instruction consists of an
`instruction word 200, a first operand descriptor 201, and a
`second operand descriptor 202. The instruction word 200
`comprises an OP field indicative of operation of the instruc
`tion in question, an X1 field indicative of the number of an
`index register for a first operand, and an X2 field indicative
`of the number of another index register for a second oper
`and. The first operand descriptor 201 comprises a first
`descriptor (D1) field indicative of a segment descriptor for
`the first operand, a y1 field indicative of an operand location
`for the first operand, and an L field indicative of a transfer
`length of data. Similarly, the second descriptor 202 com
`prises a second descriptor (D2) field indicative of another
`segment descriptor for the second operand and a y2 field
`indicative of another operand location for the second oper
`and.
`Turning to FIG. 3, description will proceed to the instruc
`tion processing unit 21 used in the central processing system
`depicted in FIG. 1. The instruction processing unit 21
`processes the data transfer instruction illustrated in FIG. 2 to
`generate first and second virtual addresses for the first and
`the second operands and first and second access type bits a1
`and a2 for the first and the second operands.
`The instruction processing unit 21 is supplied with the
`data transfer instruction illustrated in FIG. 2. The instruction
`processing unit 21 comprises index registers 203 each of
`which stores a base address for the operand and so on. In the
`index registers 203, an index register 204 is indicated by the
`X2 field in the instruction word 200 while another index
`register 205 is indicated by the X1 field in the instruction
`word 200. The instruction processing unit 21 further com
`prises segment descriptor registers 206.
`Turning to FIGS. 4A and 4B, each of the segment
`descriptor registers 206 stores segment descriptor defining
`segments which are logical data blocks. The segment
`descriptor comprises Base and Bound fields indicative of
`location and a size in a virtual space of the segment,
`respectively, and a W field indicative of a virtual space
`register number of a virtual space register (WSR) for storing
`a virtual space number (WSN). The segment descriptor
`further includes a Flag field indicative of an attribute of the
`segment. The attribute of the segment is shown in FIG. 4B.
`
`40
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`Referring to FIG. 1, description will be given generally as
`regards a central processing system of a signal processor in
`an information processing system according to the present
`invention. The central processing system comprises an
`45
`instruction processing unit (IP) 21, an address translation
`unit (AT) 22, a memory control unit (MC) 23, a main
`memory unit (MM) 24, and an expanded memory unit (EM)
`25. A combination of the main memory unit 24 and the
`expanded memory unit 25 is called a real memory unit.
`The instruction processing unit 21 supplies the address
`translation unit 22 with a virtual address VA and a command
`via an address bus 51 and a command bus 52, respectively.
`The instruction processing unit 21 receives readout data/
`status from the address translation unit 22 via a readout
`data/status bus 53. The instruction processing unit 21 sup
`plies the address translation unit 22 with writing data via a
`writing data bus 54. The address translation unit 22 supplies
`the memory control unit 23 with a real address and a
`command via an address bus 55 and a command bus 56,
`respectively. The address translation unit 22 receives readout
`data/status from the memory control unit 23 via a readout
`data/status bus 57. The address translation unit 22 supplies
`the memory control unit 23 with writing data via a writing
`data bus 58. The memory control unit 23 supplies the main
`memory unit 24 with a main memory address MMA and a
`command via an address bus 59 and a command bus 60. The
`
`50
`
`55
`
`60
`
`65
`
`LzLabs GmbH. Ex. 1023-14
`
`

`

`5,481,688
`
`10
`
`15
`
`20
`
`30
`
`35
`
`40
`
`7
`Turning back to FIG. 3, the D1 field in the first operand
`descriptor 201 indicates one of the segment descriptor
`registers 206 that stores a W field 207 and a Base field 208
`while the D2 field in the second operand descriptor 202
`indicates another one of descriptor registers 206 that stores
`another W field 209 and another. Base field 210. The
`instruction processing unit 21 comprises virtual space reg
`isters 211. In the virtual space registers 211, a virtual space
`register 212 is indicated by the W field 207 while another
`virtual space register 213 is indicated by the W field 209.
`The instruction processing unit 21 yet comprises first and
`second adders 214 and 215 and an access type determiner
`216. The first adder 214 is supplied with contents of the
`index register 205, the Base field 208, and the y1 field of the
`first operand descriptor 201. The first adder 214 adds the
`contents of the index register 205, the Base field 208, and the
`y1 field to produce a first intra-virtual space address which
`includes a P# field, where Pit represents a page number and
`an offset field. A combination of the first intra-virtual space
`address and the virtual space number WSN in the virtual
`space register 212 composes the first virtual address for the
`first operand that is stored in a first virtual address register
`217. The access type determiner 216 is supplied with the OP
`25
`field of the instruction word 200. The access type determiner
`216 determines a first access type for the first operand on the
`basis of the OP field to produce a first access type bit al.
`indicative of the first access type that is stored in a first
`access type register 218.
`Likewise, the second adder 215 is sup lied with contents
`of the index register 204, the Base field 210, and they2 field
`of the second operand descriptor 202. The second adder 215
`adds the contents of the index register 204, the Base field
`210 and the y2 field to produce a second intra-virtual space
`address which includes another Pi field and another offset
`field. A combination of the second intra-virtual space
`address and the virtual space number WSN in the virtual
`space register 213 composes the second virtual address for
`the second operand that is stored in a second virtual address
`register 219. The access type determiner 216 also determines
`the second access type for the second operand on the basis
`of the OP field to produce a second access type bit a2
`indicative of the second access type that is stored in a second
`access type register 220. Each of the first and the second
`access type bits a1 and a2 is a bit for indicating which
`memory unit is the optimum one for the operand, the main
`memory unit 24 or the expanded memory unit 25. In the
`manner as shown in FIG. 2, the access type is determined
`based on a table as follows:
`
`45
`
`50
`
`TABLE
`ACCESS TYPE
`
`1st operand
`
`2nd operand
`
`OP field
`
`(binary)
`
`000 0001101 MAIN MEMORY
`ACCESS
`000 000 1111 EXPANDED
`MEMORYACCESS
`
`EXPANDED
`MEMORYACCESS
`MAIN MEMORY
`ACCESS
`
`In addition, the L field in the first operand descriptor 201
`indicates, as one of the index registers 203, an index register
`227 which stores a transfer data length signal indicative of
`a transfer data length 1. The transfer data length signal is
`stored in a transfer data length register 228.
`
`55
`
`60
`
`65
`
`8
`As described above, the instruction processing unit 21
`generates the first and the second virtual addresses for the
`first and the second operands and the first and the second
`access type bits a1 and a2 for the first and the second
`operands. Instructions other t