United States Patent (19)
`Smith, Jr.
`
`54 MODE INDEPENDENT SUPPORT OF
`FORMAT CONVERSION INSTRUCTIONS
`FOR HEXADECIMAL AND BINARY
`FLOATING POINT PROCESSING
`
`Inventor: Ronald Morton Smith, Jr., Wappingers
`Falls, N.Y.
`Assignee: International Business Machines
`Corporation, Armonk, N.Y.
`
`Appl. No.: 922,731
`Filed:
`Sep. 3, 1997
`Related U.S. Application Data
`
`Division of Ser. No. 414,247, Mar. 31, 1995, Pat. No.
`5,687,359.
`Int. Cl. ...................................................... G06F 7/38
`U.S. Cl. ............... 395/563; 364/715.03; 364/748.01;
`395/570
`Field of Search ......................... 364/715.03, 748.01;
`395/563,570
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`USOO588998OA
`Patent Number:
`11
`(45) Date of Patent:
`
`5,889,980
`Mar. 30, 1999
`
`5,268.855 12/1993 Mason et al. ...................... 364/748.19
`
`Primary Examiner Kenneth S. Kim
`Attorney, Agent, Or Firm-Lynn L. Augspurger
`
`57
`
`ABSTRACT
`
`A computer System having multiple floating point modes
`and common instructions for each mode in order to imple
`ment operations in a mode independent manner. A computer
`System includes two floating point modes Supported by a
`common Set of instructions for implementing operations,
`Said instructions thereby being mode independent. The com
`puter System includes a means for Storing information for
`Specifying the current floating point mode, and a floating
`point unit adapted to execute any one instruction from
`among the common Set of instructions in accordance with
`the Stored rounding mode and the operation associated with
`Said instruction, thereby providing for mode independent
`operation. In an embodiment of the present invention, the
`floating point mode is either binary floating point or hexa
`decimal floating point.
`
`4,949,291 8/1990 Saini .................................. 364/715.03
`
`4 Claims, 5 Drawing Sheets
`
`CON
`MNE- CURRENT
`INSTRUCTION | MONIC
`MODE | SOURCE VERT | ARCET
`CONVERT
`FEER | HFP
`R. S.
`Yes |
`F
`FROM BP
`BFP
`B S
`O
`U.7
`FBDR | HFP
`B L
`YES | H E
`---
`BFP
`E
`O
`U
`HER
`HFP
`H
`O
`
`CONVERT
`
`FHDR
`-m
`BER
`
`TBDR
`
`Hip
`BFP
`HFP
`BFP
`HFP
`BFP
`THER | HFP
`BFP
`HFP
`BFP
`
`THDR
`
`O
`H
`B LR
`YES
`H L
`B SRZ
`H L | YES
`UZ
`B S
`O
`H
`YES : B LR
`B L
`O
`H S | NO | UZ
`B S
`YES : H LE
`HL
`O
`U
`B L
`YES | H LE
`
`-
`Y
`CONVERT
`O BFD
`
`CONVER
`| TO HFF
`i
`
`EXPLANAION:
`
`B BINARY FLOATING-POINT (BFP)
`E EXACT RESULT
`H HEXADECIMAL FLOATING-POINT (HFP)
`L LONG FORMAT (64. BITS)
`R ROUNDED RESULT
`S SHORT FORMAT (32 BITS)
`T TRUNCATED RESULT
`Z 32 ZEROS APPENDED TO SHORT FORMAT (64. BITS)
`U SOURCE IS PLACED UNCHANGED IN THE TARCET
`
`LzLabs GmbH. Ex. 1011-1
`
`

`

`U.S. Patent
`
`Mar. 30, 1999
`
`Sheet 1 of 5
`
`5,889,980
`
`
`
`
`
`
`
`
`
`MAN
`STORAGE
`
`r CPU CPU CPU
`102 N-104 N-106 N-108
`
`TO
`MAN
`STORAGE
`
`
`
`LzLabs GmbH. Ex. 1011-2
`
`

`

`U.S. Patent
`
`Mar. 30, 1999
`
`Sheet 2 of 5
`
`5,889,980
`
`
`
`O
`
`A
`52
`
`lowel slo S. Elooooooo
`
`1 MWPA SC C MASK PO O O O O O O
`18 20
`1
`12
`16
`24
`3.
`
`5
`
`8
`
`NSTRUCTION ADDRESS
`
`G.5
`
`65
`
`LMCD R1, D2(X2, B2)
`RXE, LONG OPERANDS
`58 //RX, B, D,
`f
`IG.5
`
`O
`
`16
`
`24 28 32 36
`
`47
`
`MNEMONC R1,R2
`OP CODE
`
`RRE)
`//////// R1 || R2
`16
`24 28 31
`
`O
`
`MNEMONC
`FBER
`FBDR
`
`OP CODE OPERANDS
`'B338
`SHORT OPERAND, LONG RESULT
`'B548
`LONG
`
`FIG.6A
`
`RRE
`
`51
`
`MNEMONC R1,R2
`OP CODE
`|//////// R.
`28
`16
`24,
`OP CODE OPERANDS
`B33B
`SHORT OPERAND, LONG RESULT
`"B34B'
`LONG
`FIG.6B
`
`O
`MNEMONC
`THER
`THDR
`
`LzLabs GmbH. Ex. 1011-3
`
`

`

`U.S. Patent
`
`Mar. 30, 1999
`
`Sheet 3 of 5
`
`5,889,980
`
`BYTE |
`
`1
`
`2
`
`3.
`
`BITS
`O
`1
`2
`5
`4
`5-7
`
`O
`1
`2
`5
`4.
`5-7
`
`O-7
`
`
`
`O
`-5
`7
`
`-T-
`
`VALUE
`
`FUNCTION
`BFP-NVALID-DAA MASK
`BFP-DIVISION-BY-ZERO MASK
`BFP-OVERFLOW MASK
`BFP-UNDERFLOW MASK
`BFP-NEXACT MASK
`(UNASSIGNED)
`
`BFP-NVALD-DATA FLAG
`BFP-DVISION-BY-ZERO FLAG
`BFP-OVERFLOW FLAG
`BFP-UNDERFLOW FLAG
`BFP-NEXACT FLAG
`(UNASSIGNED)
`
`DATA-EXCEPTION CODE (DXC)
`
`QNAN MODE
`(UNASSIGNED)
`ROUNDING MODE
`ROUND TO NEAREST
`ROUND TO ZERO
`ROUND UP
`ROUND DOWN
`
`LzLabs GmbH. Ex. 1011-4
`
`

`

`U.S. Patent
`
`Mar. 30, 1999
`
`Sheet 4 of 5
`
`5,889,980
`
`MNEMONIC R1,R2
`
`RRE
`
`O
`MNEMONC
`FHER
`
`FHDR
`
`24, 28 31
`16
`OP CODE OPERANDS
`'B33A
`LONG OPERAND, SHORT RESULT
`WITH 32 ZEROS APPENDED
`LONG
`
`B34A
`
`FIG.7A
`
`RRE
`MNEMONIC R1,R2
`OP CODE | //////// R1||R2
`16
`24 28 31
`OP CODE OPERANDS
`B539
`LONG OPERAND, SHORT RESULT
`WITH 32 ZEROS APPENDED
`LONG
`
`'B549
`FIG.7B
`
`O
`MNEMONC
`TBER
`
`TBDR
`
`LzLabs GmbH. Ex. 1011-5
`
`

`

`U.S. Patent
`
`Mar. 30, 1999
`
`Sheet 5 of 5
`
`5,889,980
`
`
`
`
`
`FBDR
`
`
`
`CONVERT
`FROM - FP
`
`|
`
`CONVERT
`TO BFP
`
`CON
`MNE- CURRENT
`INSTRUCTION | MONIC | MODE | SOURCE VERT | TARGET
`CONVERT
`FEER
`HFP
`B S
`NO | UZ
`FROM BFP
`BFP
`B S
`YES
`H LE
`HFP
`B L
`Brp
`E L | No
`U
`FHER | HFP
`H L | NO
`B SRZ
`BFP
`H L | YES
`FHDR | HFE | H L | No | U
`BFP
`H
`YES
`B LR
`TBER | HFP | H L || Yes | B sRz
`EFP
`B
`NO
`UZ
`TBDR | HFP
`H L
`YES
`B LR
`BFP
`B
`NO
`U
`H S
`NO
`UZ
`B S
`L
`B L
`
`CONVERT
`TO HFP
`
`THER
`
`BFP
`HFP
`BFP
`
`YES
`
`H LE
`
`EXPLANATION:
`
`B BINARY FLOATING-POINT (BFP)
`E EXACT RESULT
`H HEXADECIMAL FLOATING-POINT (HFP)
`L LONG FORMAT (64. BITS)
`R ROUNDED RESULT
`S SHORT FORMAT (32 BITS)
`T TRUNCATED RESULT
`Z 32 ZEROS APPENDED TO SHORT FORMAT (64. BITS)
`U SOURCE IS PLACED UNCHANCED IN THE TARGET
`
`FIG.8
`
`LzLabs GmbH. Ex. 1011-6
`
`

`

`5,889,980
`
`1
`MODE INDEPENDENT SUPPORT OF
`FORMAT CONVERSION INSTRUCTIONS
`FOR HEXADECIMAL AND BINARY
`FLOATING POINT PROCESSING
`
`This is a divisional of application Ser. No. 08/414,247
`filed Mar. 31, 1995, now issued U.S. Pat. No. 5,687,359.
`
`FIELD OF THE INVENTION
`The present invention relates to computer Systems and,
`more particularly, to a computer architecture providing
`hexadecimal and binary floating point modes and including
`instructions for implementing operations mode indepen
`dently.
`
`15
`
`2
`formats and will also require conversions of data between
`the two modes. Also, it may be appreciated that in the mixed
`environment, it will be necessary to provide math libraries
`for both modes. In Some cases, the exact Sequence of code
`for the two modes will of necessity be different, but in other
`cases it may be possible and desirable to provide program
`modules which can operate in either mode.
`It is recognized, therefore, that a computer System that
`provides multiple floating point modes presents unique
`problems in order to provide for mode-independent
`applications, and thus requires instructions for implementing
`operations to Support Veritable mode independent operation.
`SUMMARY OF THE INVENTION
`The present invention provides for mode-independent
`code in a computer System having multiple floating point
`modes. In an embodiment of the present invention, a com
`puter System includes two floating point modes Supported by
`a common Set of instructions for implementing operations,
`Said instructions thereby being mode independent. The com
`puter System includes a means for Storing information for
`Specifying the current floating point mode, and a floating
`point unit adapted to execute any one instruction from
`among the common Set of instructions in accordance with
`the Stored rounding mode and the operation associated with
`Said instruction, thereby providing for mode independent
`operation.
`In an implementation, there is provided an instruction,
`referred to hereinbelow as the instruction LOAD MODAL
`CONSTANT, for implementing operation which loads either
`of two different 8-byte values from Storage depending on the
`current floating-point mode. Thus, the program can Set up a
`hexadecimal and a binary constant and load the appropriate
`value as a function of the current mode. All instructions
`added to solve special problems for the IEEE format are also
`defined to operate in the HFP mode and to provide consistent
`answerS Such that in most cases the output of a compiler can
`be independent of the mode. There is also provided in an
`embodiment of the present invention, instructions for imple
`menting operations which convert between the BFP and
`HFP formats. These instructions, referred to hereinbelow as
`CONVERT FROM BFP, CONVERT FROM HFP, CON
`VERT TO BFP, and CONVERT TO HFP, are designed in
`Such a way that the program can convert between data in a
`known format to data in the current format without requiring
`the program to be aware of what the current format is.
`BRIEF DESCRIPTION OF THE DRAWINGS
`Additional aspects, features, and advantages of the inven
`tion will be understood and will become more readily
`apparent when the invention is considered in the light of the
`following description made in conjunction with the accom
`panying drawings, wherein:
`FIG. 1 illustrates a conventional Shared memory computer
`System which may be employed to implement the present
`invention;
`FIG. 2 Schematically depicts functional components
`included in a CPU which may be employed in accordance
`with the present invention;
`FIG. 3 illustrates the format of a 64 bit program status
`word (PSW), including a bit for indicating a binary or
`hexadecimal floating point mode, in accordance with an
`embodiment of the present invention;
`FIG. 4 illustrates the format of a floating-point-control
`(FPC) register, in accordance with an embodiment of the
`present invention;
`
`BACKGROUND OF THE INVENTION
`In the ensuing description of the prior art and the present
`invention, the following are herein incorporated by refer
`CCC.
`“Enterprise Systems Architecture/390 Principles of
`Operation,” Order No. SA22-7201-02, available
`through IBM branch offices, 1994;
`“IEEE standard for binary floating-point arithmetic,
`ANSI/IEEE Std 754-1985,” The Institute of Electrical
`and Electronic Engineers, Inc., New York, August
`1985; and
`Commonly assigned U.S. patent application Ser. No.
`08/414,250 to Eric Mark Schwarz, et al., filed Mar. 31, 1995,
`now issued U.S. Pat. No. 5,687,106, and entitled “Imple
`mentation of Binary Floating Point Using Hexadecimal
`Floating Point Unit”.
`Previous hardware implementations of floating-point
`arithmetic have provided various radixes, including binary,
`decimal, or hexadecimal. But only a Single radix was
`Supported in any particular implementation. AS future
`machines are built, they must be compatible with previous
`machines, and must also provide Support for new formats. A
`new requirement emerges to provide hardware Support for
`more than one format. For example, there is a requirement
`to support both the IBM System/360 hexadecimal and the
`IEEE binary floating-point formats.
`Providing a computer with both modes permits more
`flexibility in handling applications, and permits a Smoother
`transition between old applications and data using one mode
`and new applications and data in the new mode. Several
`approaches to providing Support for two floating-point for
`mats can be considered. One approach would be to provide
`Separate registers and instructions for each format. This
`approach would keep the problems of complexity and inter
`action between the two modes to a minimum, but it does not
`provide for the Synergistic effects of an integrated Solution.
`In the hereinabove cited, commonly assigned U.S. Patent
`Application to Schwarz et al., a computer System is
`described, including a floating point processor unit, in which
`the same instructions and registers are used for two floating
`point formats, along with a mode to control which format is
`to be used. The two modes specifically described therein are
`the IBM S/390 hexadecimal floating-point (HFP) mode and
`the IEEE 754 binary floating-point (BFP) modes. The con
`cept of mode independent code reduces the problems asso
`ciated with compiler Support of both modes and also permits
`program modules to be written which cart be called in both
`modes. However, this also present Several unique problems
`which must be solved.
`For example, it may be appreciated that there will be
`applications which must operate on data in both types of
`
`25
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`LzLabs GmbH. Ex. 1011-7
`
`

`

`3
`FIG. 5 illustrates the format of a LOAD Modal Constant
`mode independent instruction, in accordance with the
`present invention;
`FIG. 6A and FIG. 6B illustrate separate instructions for
`implementing a mode independent operation of converting a
`floating point number from BFP to HFP, in accordance with
`the present invention;
`FIG. 7A and FIG. 7B illustrate separate instructions for
`implementing a mode independent operation of converting a
`floating point number from HFP to BFP, in accordance with
`the present invention; and
`FIG. 8 summarizes the BFP-HFP instructions for imple
`menting mode independent operations of converting a float
`ing point number between HFP and BFP in accordance with
`the present invention.
`DETAILED DESCRIPTION OF THE
`INVENTION
`FIG. 1 illustrates a conventional shared memory computer
`System including a plurality of central processing units
`(CPUs) 102-108 all having access to a common main
`storage 110. FIG. 2 schematically depicts functional com
`ponents included in a CPU from FIG.1. Instruction unit 200
`fetches instructions from common main Storage 110 accord
`ing to an instruction address located in the program Status
`word (PSW) register 202 and appropriately effects execution
`of these instructions. Instruction unit 200 appropriately
`hands off retrieved floating point instructions to floating
`point processor unit 204, along with Some of the operands
`that may be required by the floating point processor unit to
`execute the instruction. Floating point (FP) Processor unit
`204 includes all necessary hardware to execute the floating
`point instruction Set, and preferably, in accordance with an
`embodiment of the present invention, Supports both Binary
`and Hexadecimal floating point formats. FP processor unit
`204 is coupled to floating point (FP) registers 206, which
`contain floating point operands and results associated with
`FP processor unit 204 processing, and is also coupled to
`general registers 208. FP processor unit 204 is also coupled
`to floating point control (FPC) register 210, which prefer
`ably includes mask bits in addition to those provided in the
`PSW, as well as bits indicating the floating point mode. In
`a multi-user application, FPC register 210 is under control of
`the problem State.
`FIG. 3 illustrates the format of a 64 bit PSW as Stored in
`PSW register 202. In a multi-user application, the Supervisor
`state saves the PSW for a given problem state when taking
`interruption to dispatch another problem State. It can be seen
`that PSW includes program mask bits 20–23.
`FP-Mode Bit in PSW
`Bit 24 of the PSW is the FP-mode bit. In accordance with
`an embodiment of the present invention whereby both
`binary and hexadecimal floating point modes are Supported,
`when the bit is zero, the CPU is in the hexadecimal-floating
`point (HFP) mode, and floating-point operands are inter
`preted according to the HFP format. When the bit is one, the
`CPU is the binary-floating-point (BFP) mode, and floating
`point operands are assumed to be in the BFP format. Some
`floating-point instructions operate the same in either mode.
`When an instruction is executed which is not available in
`the current FP mode, a Special-operation exception is rec
`ognized.
`FPC Register
`As illustrated in detail by FIG. 4, the floating-point
`control (FPC) register 210 is a 32-bit register, which con
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`5,889,980
`
`15
`
`25
`
`4
`tains the mode (i.e., rounding mode), mask, flag, and code
`bits. For this implementation, by way of example, the
`rounding mode is represented by the last to bits of the last
`byte. Round to nearest, round to Zero, round up, and round
`down modes are Supported.
`A preferred System for practicing the present invention is
`further described in the above-cited, commonly assigned
`U.S. Patent Application to Schwarz et al., in which a floating
`point dataflow for an a Floating point processor unit imple
`menting both IEEE 754 Binary and IBM S/390 Hexadecimal
`is shown. In accordance with the present invention, instruc
`tions are included that are common to HFP and BFP modes
`(e.g., one ADD instruction for both HFP and BFP), the
`instructions appropriately implementing an operation
`according to the current mode indicated by the current FP
`mode. A number of instructions, including LOAD FPINTE
`GER and Several radix conversion instructions, are provided
`as examples of an embodiment of implementing and Sup
`porting mode independent operation according to the present
`invention, which is not limited thereto.
`FIG. 5 illustrates the format of a LOAD Modal Constant
`instruction which may be executed by FP Processor Unit
`204. Execution of this instruction results in a first or second
`of a pair of operands (each representing the same numerical
`value, e.g., constant, but in different architected States, i.e.,
`binary and hex) located in storage as addressed by the
`Second operand (including a combination of a base address
`according to a value located in a register identified B and
`an offset specified by D) being placed in the first-operand
`location R, which identifies a floating point register 206. In
`accordance with an embodiment of the present invention,
`the first of the pair is chosen if the current FP mode is HFP.
`and the second is chosen if the current mode is BFP, the
`mode being indicated by the FP-mode bit in PSW register
`202. More particularly, in this implementation, the first of
`the pair of Storage operands is located at address A and the
`Second at A+8, where A is the Second-operand address
`designated by the instruction.
`The operation is performed without inspecting the con
`tents of the Second operand; no arithmetic exceptions are
`recognized. AcceSS exceptions may or may not be recog
`nized for the Storage location of the operand that is not
`Selected.
`It may be appreciated, therefore, that the instruction
`LOAD MODAL CONSTANT simplifies writing mode
`independent programs. It Selects one of a pair of Storage
`operands, depending on whether the FP mode is HFP or BFP.
`Thus, if the first of the pair is a constant in the HFP format
`and the second is the same number in the BFP format, the
`instruction will load the value appropriate for the current
`mode, So that it can be used by Subsequent arithmetic
`operations. Accordingly, there is no need for Separate
`instructions for loading either HFP or BFP constants, or for
`a programmer/program to know which mode is the current
`mode.
`Radix Conversion
`In accordance with an embodiment of the present
`invention, in order to provide mode independent Support of
`HFP and BFP architectures, a number of radix conversion
`instructions are also included.
`FIG. 6A and FIG. 6B illustrate separate instructions for
`implementing a mode independent operation of converting a
`floating point number from BFP to HFP, if necessary,
`according to the FP mode indicated by the FP-mode bit in
`PSW register 202.
`If the floating-point radixe of Source and target differ, the
`operand located in the Second-operand location R2 which
`
`LzLabs GmbH. Ex. 1011-8
`
`

`

`S
`identifies a floating point register 206 is converted from the
`binary floating-point (BFP) format to the hexadecimal
`floating-point (HFP) format, and the result normalized and
`rounded to Zero (truncated), and then placed in the first
`operand location R which identifies a floating point register
`206.
`It is therefore understood that no conversion takes place
`if the current FP mode is BFP and the instruction is CON
`VERT FROM BFP, or if the current FP mode is HFP and the
`instruction is CONVERT TO HFP. Instead, the second
`operand is placed unchanged in the first-operand location,
`except that, for FBER and THER, the second operand is
`extended to fill the first-operand location by appending 32
`ZeroS on the right.
`The sign of the result is the Sign of the Second operand.
`If the Second operand has a Sign bit of one and all other
`operand bits are Zeros, the result also is a one followed by
`all ZeroS.
`When the conversion takes place and the characteristic of
`the hexadecimal intermediate result is negative, the final
`result is all Zeros, but with the same sign as the Second
`operand, and no exception is recognized. Accordingly, it
`may be appreciated that a mode independent instruction is
`appropriately executed in accordance with the Stored mode
`and the operation effected by the instruction.
`FIG. 7A and FIG. 7B illustrate separate instructions for
`implementing a mode independent operation of converting a
`floating point number from HFP to BFP, if necessary,
`according to the FP mode indicated by the FP-mode bit in
`PSW register 202.
`If the floating-point radixes of Source and target differ, the
`operand located in the Second-operand location R2 which
`identifies a floating point register 206 is converted from the
`hexadecimal floating-point (HFP) format to the binary
`floating-point (BFP) format, and the result rounded accord
`ing to the current rounding mode (e.g., as specified by the
`last two bits stored in the FPC register 210) binary floating
`point (BFP) format to the hexadecimal floating-point (HFP)
`format, and the result normalized and rounded to Zero
`(truncated), and the rounded result is then placed in the
`first-operand location R which identifies a floating point
`register 206. Short results are extended to fill the first
`operand location by appending 32-Zeros on the right.
`No conversion occurs if the current FP mode is HFP and
`the instruction is CONVERT FROM HFP, or if the current
`FP mode is BFP and the instruction is CONVERT TO BFP.
`Instead, the Second operand is placed unchanged in the
`first-operand location.
`The sign of the result is the Sign of the Second operand.
`If the Second operand has a Sign bit of one and all other
`operand bits are Zeros, the result also is a one followed by
`all ZeroS.
`If the conversion is to occur for FHER and TBER, and if
`the biased exponent of the rounded result would be too large
`to fit into the target format, a data exception (conversion
`DXC4) is recognized. If the biased exponent is negative, the
`result is denormalized, and no exception is recognized. No
`data exception is recognized when no conversion takes
`place.
`In accordance with the hereinabove described radix con
`version instructions, it may therefore be appreciated that
`these BFP-HFP conversion instructions provide for conver
`Sions of data between binary and hexadecimal formats. AS
`defined, the current FP mode determines the radix of the
`Source and the mode named by the instruction determines
`the radix of the target, or Vice versa, depending on the
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`5,889,980
`
`15
`
`25
`
`6
`instruction. Conversion from binary to hexadecimal, or from
`hexadecimal to binary, only takes place when Source and
`target radix differ. If Source and target radix are the same, the
`data are merely moved from the Source register to the target
`register without conversion. For example, CONVERT
`FROM BFP performs conversions if the current FP mode is
`HFP, but not if the current mode is BFP. These and other
`aspects of the radix-conversion instructions are Summarized
`in FIG. 8.
`In order to retain full precision, the BFP-HFP conversion
`instructions convert binary operands in the Short format to
`hexadecimal operands in the long format, rather than con
`Verting short to short. Using a long hexadecimal result
`Subsequently as a short operand requires no extra conversion
`StepS.
`Conversely, conversion to short binary numbers requires
`hexadecimal operands in the long format; a short hexadeci
`mal operand should be extended to long by ensuring that the
`right half of the register is cleared. This avoids unrepeatable
`rounding errors in the binary result due to "garbage' data left
`over from previous use. Thus, the entire register should be
`cleared before loading a short hexadecimal operand from
`Storage for conversion to binary.
`Also note that, conversion of finite short binary numbers
`to the long hexadecimal format is exact. Since both exponent
`and fraction of the target have Sufficient bits, there is no
`rounding, Overflow, or underflow, and nonzero results are
`normalized.
`When conversion takes place, the Source and target are
`governed by the rules of their respective formats, regardless
`of the current FP mode. Thus, BFP infinities and NaNs are
`detected if the source operand is in the BFP format.
`Likewise, the BFP rounding mode applies if the results in the
`BFP format, and the result is always rounded to zero
`(truncated) if it is in the HFP format. When no conversion
`take place, these rules do not apply. No rounding takes place,
`and Special entities are not detected.
`When the result of converting the Source operand cannot
`be represented in the target format, a data exception
`(conversion, DXC 4) is recognized, and a program interrup
`tion occurs. This interruption cannot be masked off, So that
`an exception-handling program may take appropriate action.
`The BFP-HFP format-conversion instructions recognize
`data exceptions with DXC 4. Although the result may
`actually underflow, overflow, or be inexact, the arithmetic
`exceptions for those conditions are not used. Instead, Stan
`dard numeric defaults are Supplied to underflow and inexact;
`and for Overflow a program interruption for data occurs. The
`assumption is that Such conversions will generally be per
`formed before or between applications, when a Sophisticated
`application environment with Specific exception handlers
`would not usually be available, but the interruption for
`conversion makes it convenient to provide installation
`defined results where a Standard default does not exist.
`Although the above description provides many
`Specificities, these enabling details should not be construed
`as limiting the Scope of the invention, and it will be readily
`understood by those perSons Skilled in the art that the present
`invention is Susceptible to many modifications, adaptations,
`and equivalent implementations without departing from this
`Scope and without diminishing its attendant advantages. It is
`therefore intended that the present invention is not limited to
`the disclosed embodiments but should be defined in accor
`dance with the claims which follow.
`What is claimed is:
`1. A computer System including two floating point modes
`Supported by a common Set of instructions for implementing
`
`LzLabs GmbH. Ex. 1011-9
`
`

`

`7
`operations, program use of Said instructions thereby being
`floating point mode independent, Said System comprising:
`a storage device including Stored value information for
`Specifying one of Said two floating point modes,
`floating point processor unit adapted to execute an
`operation based on any one instruction from among
`Said common Set of instructions in accordance with the
`floating point mode specified by a specific Stored value
`Specifying one of Said two stored floating point modes,
`thereby providing for floating point mode independent
`program use of the instructions,
`wherein when Said floating point processor unit executes
`an instruction that identifies a Stored value of Said
`Stored value information which designates Said one of
`Said two Stored floating point modes as a Source float
`ing point format or a destination floating point format
`as an instruction declared format, Said floating point
`processor unit converts the identified Stored value into
`Said Stored floating point mode format only in the event
`that Said instruction designates Said Source floating
`point format and this designated Source floating point
`format is different from the Stored floating point mode,
`and Said floating point processor unit converts the
`
`5
`
`15
`
`5,889,980
`
`8
`identified Stored value into Said designated destination
`floating point format only in the event that Said instruc
`tion designates the destination floating point format and
`the destination floating point format is different from
`the Stored floating point mode, whereby the mode of an
`operand Specified for processing depends on the float
`ing mode Specified in the instruction Specifying
`declared format without requiring a program providing
`Said instruction with Said declared format to have need
`to identify the Specific Stored value Specifying one of
`Said two Stored floating point modes.
`2. The computer System according to claim 1, wherein
`Said Source or destination floating point format is binary
`floating point format or hexadecimal floating point format.
`3. The computer System according to claim 1, wherein
`Said instruction designates the Source floating point format
`as one of Said floating point formats from which to convert
`the stored value.
`4. The computer System according to claim 1, wherein
`Said instruction designates the destination floating point
`format as one of Said floating point formats to which to
`convert the Stored value.
`
`LzLabs GmbH. Ex. 1011-10
`
`

`

`UNITED STATES PATENT ANDTRADEMARK OFFICE
`CERTIFICATE OF CORRECTION
`
`PATENT NO. : 5,889,980
`DATED
`March 30, 1999
`INVENTOR(S) : Ronald Morton Smith, Jr.
`
`It is certified that error appears in the above-identified patent and that said Letters Patent is hereby
`corrected as shown below:
`
`Title page, item 19) should read -- Smith, Sr. --
`Title page, item (75) "Ronald Morton Smith, Jr." should read --
`Ronald Morton Smith, Sr. --
`
`Signed and Sealed this
`Twenty-seventh Day of February, 2001
`
`Attesting Officer
`
`Acting Director of the United States Patent and Trademark Office
`
`NCHOLAS P. GODC
`
`LzLabs GmbH. Ex. 1011-11
`
`