UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`LzLabs GmbH,
`
`Petitioner
`
`v.
`
`INTERNATIONAL BUSINESS MACHINES CORPORATION
`
`Patent Owner
`____________
`
`IPR2023-00274
`Patent 8,713,289
`____________
`
`
`
`
`
`
`
`DECLARATION OF IAN JESTICE PERTAINING TO PETITION FOR
`INTER PARTES REVIEW OF U.S. PATENT NO. 8,713,289
`
`
`LzLabs GmbH. Ex. 1003-1
`
`

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`IPR of U.S. Patent 8,713,289
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`
`TABLE OF CONTENTS
`
` 
`
` 
`
` 
`
`INTRODUCTION ........................................................................................... 1 
`I. 
`EXPERIENCE AND QUALIFICATIONS ..................................................... 1 
`II. 
`III.  TASK SUMMARY AND MATERIALS REVIEWED ................................. 5 
`IV.  LEGAL STANDARDS ................................................................................... 5 
`Level of Ordinary Skill in the Art ......................................................... 5 
` 
`Legal Standard for Claim Construction ................................................ 6 
`Obviousness ........................................................................................... 7 
`Priority Date ........................................................................................ 10 
` 
`V.  OVERVIEW OF THE ’289 PATENT .......................................................... 12 
`Priority Date of the ’289 Patent........................................................... 12 
` 
`Subject Matter of the ’289 Patent ........................................................ 13 
`Prosecution History of the ’289 Patent ............................................... 18 
` 
`VI.  LEVEL OF ORDINARY SKILL IN THE ART ........................................... 21 
`VII.  OVERVIEW OF THE PRIOR ART ............................................................. 22 
`Loderer ................................................................................................ 22 
` 
`PoO ...................................................................................................... 28 
`Kane ..................................................................................................... 36 
` 
`VIII.  CLAIM CONSTRUCTION .......................................................................... 37 
`IX.  GROUND 1: CLAIMS 1, 4, 6, 10-11, AND 16 ARE OBVIOUS IN VIEW
`OF LODERER ............................................................................................... 37 
`Loderer Overview ................................................................................ 37 
` 
`Claim 1 ................................................................................................ 44 
`1. 
`Claim element 1[a1]: “1. A computer program product for
`emulating computer instructions from a source machine to produce
`sequences of instructions on a target machine, said computer program
`product comprising:”
`44 
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`IPR of U.S. Patent 8,713,289
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`2. 
`Claim element 1[a2]: “a non-transitory computer readable
`storage medium readable by a processor and storing instructions for
`execution by the processor for performing a method comprising:” 46 
`3. 
`Claim element 1[b]: “obtaining by the target machine a
`computer instruction from the source machine, said source machine
`having a different architecture from said target machine; and”
`47 
`4. 
`Claim element 1[c]: “generating a sequence of target machine
`instructions which together operate to derive an encoding for a target
`machine condition code for the computer instruction, wherein the
`sequence of target machine instructions provides distinguishing
`information to distinguish between a plurality of possible outcomes
`for the target machine condition code, and”
`5. 
`Claim element 1[d]: “directly calculates the target machine
`condition code without using branch instructions, the directly
`calculating comprising:”
`6. 
`Claim element 1[e]: “determining an intermediate condition
`code value, the intermediate condition code value being a provisional
`value for the target machine condition code and subject to change
`based on the distinguishing information; and”.
`7. 
`Claim element 1[f]: “determining, based on the intermediate
`condition code value and based on the distinguishing information, the
`target machine condition code, wherein at least part of said
`distinguishing information is separate from the intermediate condition
`code value.”
`60 
`Claim 4: “The computer program product of claim 1, wherein said
`method further includes executing said generated sequence of target
`machine instructions” .......................................................................... 62 
`Claim 6: “The computer program product of claim 1, wherein the
`sequence of target machine instructions together operate to directly
`calculate the target machine condition code using at least one of
`addition, subtraction, and multiplication.” .......................................... 64 
`
`51 
`
`56 
`
`58 
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`ii
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`IPR of U.S. Patent 8,713,289
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`Claim 10: “The computer program product of claim 1, wherein
`determining the intermediate condition code value comprises storing
`the intermediate condition code value in a condition code storage
`location as the provisional target machine condition code, and wherein
`determining the target machine condition code based on the
`distinguishing information and the intermediate condition code value
`comprises performing at least one operation on the intermediate
`condition code value stored in the condition code storage location to
`obtain the target machine condition code and storing the target
`machine condition code in the condition code storage location.” ...... 65 
`Claims 11 and 16 ................................................................................. 68 
` 
`X.  GROUND 2: CLAIMS 1-4, 6, 10-12, AND 16-17 ARE OBVIOUS TO
`LODERER IN VIEW OF POO, KANE, AND THE KNOWLEDGE OF A
`POSA ............................................................................................................. 77 
`  Motivation to Combine Loderer with PoO and Kane ......................... 77 
`A POSA Would Have Had a Reasonable Expectation of Success
` 
`Applying Loderer’s Technique to Calculate an Overflow Code for an
`ADD Instruction Without Branches .................................................... 86 
`1. 
`Exemplary ADD Instruction Implementation
`86 
`2. 
`Detecting the overflow
`89 
`3. 
`Calculating the overflow condition code
`100 
`Claim 1 ..............................................................................................102 
`Claim 2: The computer program product of claim 1, wherein said
`calculation of the target machine condition code comprises using at
`least one of carry, sign, and overflow codes in the calculation. .......104 
`Claim 3: The computer program product of claim 2, wherein said
`calculation employs temporary locations for storing intermediate
`results. ................................................................................................108 
`Claim 4: The computer program product of claim 1, wherein said
`method further includes executing said generated sequence of target
`machine instructions. .........................................................................109 
`
` 
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` 
`
` 
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`iii
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`IPR of U.S. Patent 8,713,289
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`Claim 6: The computer program product of claim 1, wherein the
`sequence of target machine instructions together operate to directly
`calculate the target machine condition code using at least one of
`addition, subtraction, and multiplication. ..........................................112 
`Claim 10: The computer program product of claim 1, wherein
`determining the intermediate condition code value comprises storing
`the intermediate condition code value in a condition code storage
`location as the provisional target machine condition code, and wherein
`determining the target machine condition code based on the
`distinguishing information and the intermediate condition code value
`comprises performing at least one operation on the intermediate
`condition code value stored in the condition code storage location to
`obtain the target machine condition code and storing the target
`machine condition code in the condition code storage location. ......113 
`Claims 11, 16 .....................................................................................114 
`Claims 12, 17 .....................................................................................116 
` 
`XI.  SECONDARY CONSIDERATIONS .........................................................116 
`XII.  CONCLUSION ............................................................................................116 
`
`
` 
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` 
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`iv
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`LzLabs GmbH. Ex. 1003-5
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`IPR of U.S. Patent 8,713,289
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`LIST OF EXHIBITS
`
`1001 U.S. Patent No. 8,713,289 to Copeland et al (“the ’289 patent”)
`Ian Jestice CV
`Intentionally Blank
`
`1002
`
`1003
`
`1004
`
`1005
`
`File History of U.S. Patent No. 8,713,289 to Copeland
`
`Translation of EP0843256A2 to Loderer and certification of
`translation
`
`1006
`
`EP0843256A2 to Loderer
`
`1007 U.S. Patent 6,049,864 to Liu
`
`1008
`
`Enterprise Systems Architecture/390 Principles of Operation (“PoO”),
`SA22-7201-08, Ninth edition (June 2003)
`
`1009 Kane, G., MIPS RISC Architecture, © 1988 (“Kane”)
`
`1010 U.S. Patent Pub. No. 2006/0036790
`
`1011 U.S. Patent No. 5,889,980
`
`1012 Umeno, H., “New Method for Dispatching Waiting Logical
`Processors in Virtual Machine System,” IEEE 2005
`
`1013
`
`Scheduling Order (Dkt. 26) International Business Machines Corp. v.
`LzLabs GmbH and Texas Wormhole, LLC, Case No. 6:22-cv-00299-
`ADA (W.D. Tex.)
`
`1014 Cragon, H., “Computer Architecture and Implementation,” © 2000,
`Cambridge University Press, ISBN 0-521-65168-9
`
`1015
`
`1016
`
`Enterprise Systems Architecture/390 Principles of Operation, SA22-
`7201-06, Seventh Edition (July 1999)
`
`IBM System/370 Principles of Operation, SA22-7085-07, First
`Edition (March 1983)
`
`1017 Declaration of Jim Mullins, Ph.D
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`1018
`
`1019
`
`Information Disclosure Statement, U.S. Patent Application No.
`09/608750 (June 29, 2005)
`
`Information Disclosure Statement, U.S. Patent Application No.
`09/0924755 (July 1, 2005)
`
`1020 U.S. Patent No. 5,661,674
`
`1021 U.S. Patent No. 5,576,555
`
`1022
`
`Plambeck, K. et al., “Development of attributes of z/Architecture,”
`IBM J. RES. & DEV. VOL. 46 NO. 4/5, (July/September 2002)
`
`1023 U.S. Patent No. 5,481,688
`
`1024 Hennessey, J. et al., “Hardware/Software Tradeoffs for Increased
`Performance,” ACM SIGARCH Computer Architecture News, Vol.
`10, Issue 2, March 1982 (c) 1982
`
`1025
`
`IBM System/360 Principles of Operation, Form A22-6821-0
`
`
`
`ii
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`LzLabs GmbH. Ex. 1003-7
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`IPR of U.S. Patent 8,713,289
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`I. INTRODUCTION
`1. My name is Ian Jestice. I make this declaration based upon my own
`
`personal knowledge and, if called upon to testify, would testify competently to the
`
`matters contained herein.
`
`2.
`
`I have been asked to provide technical assistance in the inter partes
`
`review of U.S. Patent No. 8,713,289, which I may abbreviate as “the ’289 patent”
`
`or refer to as the “Challenged Patent.” This declaration is a statement of my
`
`opinions on issues related to the unpatentability of claims of the ’289 patent. I am
`
`being compensated at my normal rate of $575 per hour for my analysis, plus
`
`reimbursement for expenses. My compensation does not depend on the content of
`
`my opinions or the outcome of this proceeding.
`
`II. EXPERIENCE AND QUALIFICATIONS
`3.
`I hold the equivalent of an undergraduate degree in
`
`Telecommunications and Computer Science from the City and Guilds Institute of
`
`London, which I obtained in 1971. The City and Guilds Institute of London is an
`
`educational organization that was founded in 1878 to develop a national system of
`
`technical education in the UK and its commonwealth. It was the required
`
`educational organization for engineers working for the government run
`
`telecommunications company, the Post Office in the UK. Classes were held at
`
`various universities or colleges around the city of London and were taught by
`
`
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`LzLabs GmbH. Ex. 1003-8
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`IPR of U.S. Patent 8,713,289
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`industry professionals or university staff. At the time of my training, the courses
`
`included data transmission, assembler programming and traffic analysis.
`
`4.
`
`As described in more detail in my curriculum vitae (Ex. 1002) I have
`
`more than 40 years of industry experience. My areas of expertise include system
`
`architecture, software development, diagnostics and testing for IBM 360, 370 and
`
`390 systems, Intel x86 and PowerPC processors and data storage.
`
`5.
`
`I have extensive experience verifying compatibility of hardware and
`
`software systems against architecture of IBM 360, 370 and 390 mainframe
`
`computers. I worked for IBM as a Systems Engineer in the United Kingdom,
`
`Canada and California. As part of that work, I debugged mainframe 360 and 370
`
`mainframes at an instruction level. This included detailed analysis of customer
`
`failures, down to microcode analysis of logic errors including emulation instruction
`
`errors. During this work I frequently had to write machine code level instructions
`
`to debug the hardware and microcode. While working at ITEL (later Hitachi Data
`
`Systems), I was responsible for assuring the compatibility of ITEL AS/5 to the
`
`IBM 370/158 architecture at a machine code level.
`
`6.
`
`As part of my experience, I have worked as a design and systems
`
`engineer at Amdahl Corporation, IBM and Fujitsu, designing, building, testing and
`
`supporting computing environments with storage devices.
`
`7. While working at Amdahl, I was responsible for writing diagnostic
`
`2
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`LzLabs GmbH. Ex. 1003-9
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`IPR of U.S. Patent 8,713,289
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`code to assure that Amdahl 5880 and 5890 computer systems correctly executed
`
`the IBM 370/390 instruction set. I also personally wrote Amdahl’s BUPS (Bring
`
`Up Programs) which was used to test the hardware design and gate level
`
`simulations. These tests included the instructions to test emulation of earlier
`
`architectures such as IBM’s 1401 and IBM’s 360 systems. I also managed the
`
`group that wrote tests to verify memory translation and pipeline management
`
`hardware to verify the integrity of the pipeline as a result of different condition
`
`codes and branch conditions. While at Amdahl I gave a lecture series on the
`
`370/390 architectures to newly hired design engineers unfamiliar with the systems,
`
`particularly in machine check and exception handling.
`
`8. While at Amdahl, I also worked in Japan with Fujitsu, a major
`
`investor in Amdahl, verifying their processors and storage devices conformed to
`
`the IBM mainframe architecture utilizing a staff group of 15 engineers.
`
`9.
`
`I have done considerable work in the area of embedded software
`
`systems for industry and consumer products, and other systems including storage
`
`products (e.g. Flash Memory (Solid State Disks, memory cards, flash drives),
`
`Optical Storage (CD, DVD, WORM, Magneto-Optical), Magnetic Storage (Hard
`
`Disk, Floppy Disk, Tape), RAID/Disk Arrays and jukeboxes; USB, SCSI, iSCSI,
`
`IDE/ATA/ATAPI/SATA, Fibre Channel), as well as PCMCIA devices, game
`
`programming, and software for home appliances and telecommunications devices.
`
`3
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`LzLabs GmbH. Ex. 1003-10
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`IPR of U.S. Patent 8,713,289
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`10.
`
`I have worked with security in the context of storage devices while
`
`working for IBM, Amdahl and Fujitsu. Additionally, while working at Zadian, I
`
`was involved in the testing of secure storage devices.
`
`11.
`
`In addition to experience in developing and testing interoperable
`
`systems that emulated other platforms, I have used emulation systems extensively
`
`in development, including in my work as a diagnostic design engineer at Ciena
`
`Corporation and Infinera Corporation, were I worked with PowerPC emulators,
`
`and in developing code for Android and Apple products, using simulators that
`
`target ARM and Apple Processors on an x86 machine.
`
`12. While at the Ciena Corporation and Infinera Corporation I designed,
`
`developed and coded the BIOS code, which is the first computer instructions
`
`executed after powering on or resetting the system. The BIOS is responsible for
`
`testing and initializing the hardware and was written in PowerPC assembler code. I
`
`also designed and coded file systems that were responsible for reading and writing
`
`data to be saved on persistent storage devices.
`
`13. For these reasons and because of my technical experience and training
`
`as outlined in my curriculum vitae (Ex. 1002), I am capable of offering technical
`
`opinions regarding the design and/or operation of emulation systems, including the
`
`support of low-level hardware and system features by such systems.
`
`4
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`IPR of U.S. Patent 8,713,289
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`III. TASK SUMMARY AND MATERIALS REVIEWED
`14.
`I have been asked to review the ’289 patent and its prosecution
`
`history, to provide an understanding of the technology relevant to the Challenged
`
`Patent, to review certain prior-art references, and analyze whether or not those
`
`references disclose or teach limitations of claims from the Challenged Patent and
`
`whether and why a person of ordinary skill in the art (POSA) would have been
`
`motivated to combine or modify such teachings and/or references to arrive at the
`
`challenged claims. The opinions stated in this declaration are from the perspective
`
`of a POSA.
`
`15.
`
`In forming my opinions, I have reviewed the ’289 patent, its
`
`prosecution history and references cited by the Examiner, the materials cited in the
`
`List of Exhibits, and the materials cited throughout my declaration.
`
`IV. LEGAL STANDARDS
` Level of Ordinary Skill in the Art
`16. When interpreting a patent, I understand that it is important to identify
`
`the relevant art pertaining to the patent as well as the level of ordinary skill in that
`
`art at the time of the claimed invention. The “art” is the field of technology to
`
`which the patent is related.
`
`17.
`
`I have been instructed by counsel that the person of ordinary skill in
`
`the art (“POSA”) is a hypothetical person who is presumed to know the relevant
`
`prior art. I understand that the actual inventor’s skill is not determinative of the
`
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`IPR of U.S. Patent 8,713,289
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`level of ordinary skill. I further understand that the factors that may be considered
`
`in determining the level of skill include: the types of problems encountered in the
`
`art; prior art solutions to those problems; rapidity with which innovations are
`
`made; sophistication of the technology; and educational level of active workers in
`
`the field. I understand that not all such factors may be present in every case, and
`
`one or more of them may predominate.
`
` Legal Standard for Claim Construction
`I understand that the challenged claims of the ’289 patent (Ex. 1001)
`
`18.
`
`are to be construed in accordance with their ordinary and customary meanings, as
`
`would be understood by a person of ordinary skill in the art, in the context of the
`
`patent’s specification and its file history. For the purposes of this proceeding and
`
`the grounds presented herein, Petitioner does not present any constructions and in
`
`my opinion, no constructions are needed for the opinions offered herein.
`
`19.
`
`I understand that to determine how a person or ordinary skill would
`
`understand a claim term, one should look to those sources available that show what
`
`a POSA would have understood the disputed claim language to mean. I understand
`
`that in construing a claim term, one looks primarily to the intrinsic patent evidence,
`
`including the words of the claims themselves, the remainder of the patent
`
`specification, and the patent’s prosecution history. I understand that extrinsic
`
`evidence, which is evidence external to the patent and prosecution history, may
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`IPR of U.S. Patent 8,713,289
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`also be useful in interpreting patent claim language when the intrinsic evidence
`
`itself is insufficient.
`
` Obviousness
`I understand that the prior art may render a patent claim “obvious.” I
`
`20.
`
`understand that two or more prior art references (e.g., prior art articles, patents, or
`
`publications) that each disclose fewer than all elements of a patent claim may
`
`nevertheless be combined to render a patent claim obvious if the combination of
`
`the prior art collectively discloses all elements of the claim and one of ordinary
`
`skill in the art at the time would have been motivated to combine the prior art in
`
`such a way and would have reasonably expected success in doing so.
`
`21.
`
`I understand that this motivation to combine need not be explicit in
`
`any of the prior art, but may be inferred from the knowledge of one of ordinary
`
`skill in the art at the time the patent was filed. I also understand that one of
`
`ordinary skill in the art is not an automaton, but is a person having ordinary
`
`creativity. I further understand that one or more prior art references, articles,
`
`patents or publications that disclose fewer than all of the elements of a patent claim
`
`may render a patent claim obvious if including the missing element would have
`
`been obvious to one of skill in the art (e.g., the missing element represents only an
`
`insubstantial difference over the prior art or a reconfiguration of a known system).
`
`22.
`
`I understand that under the doctrine of obviousness, a claim may be
`
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`IPR of U.S. Patent 8,713,289
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`invalid if the differences between the invention and the prior art are such that the
`
`subject matter as a whole would have been obvious at the time the invention was
`
`made to a POSA to which the subject matter pertains.
`
`23. To assess obviousness, I understand that I am to consider the scope
`
`and content of the prior art, the differences between the prior art and the claim, the
`
`level of ordinary skill in the art, and any secondary considerations to the extent
`
`they exist.
`
`24.
`
`I understand that any evidence of secondary indicia of non-
`
`obviousness should be considered when evaluating whether a claimed invention
`
`would have been obvious to one of ordinary skill at the time of invention. These
`
`secondary indicia of non-obviousness may include, for example:
`
`a. a long felt but unmet need in the prior art that was satisfied by the
`
`claimed invention;
`
`b. commercial success of processes claimed by the patent;
`
`c. unexpected results achieved by the invention;
`
`d. praise of the invention by others skilled in the art;
`
`e. the taking of licenses under the patent by others; and
`
`f. deliberate copying of the invention.
`
`25.
`
`I understand that there must be a nexus between any such secondary
`
`indicia and the claimed invention.
`
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`26.
`
`It is also my understanding that there are additional considerations
`
`that may be used as further guidance as to when the above factors will result in a
`
`finding that a claim is obvious, including the following:
`
`a. the claimed subject matter is simply a combination of prior art
`
`elements according to known methods to yield predictable results;
`
`b. the claimed subject matter is a simple substitution of one known
`
`element for another to obtain predictable results; unexpected results
`
`achieved by the invention;
`
`c. the claimed subject matter uses known techniques to improve
`
`similar devices or methods in the same way;
`
`d. the claimed subject matter applies a known technique to a known
`
`device or method that is ready for improvement to yield predictable
`
`results;
`
`e. the claimed subject matter would have been “obvious to try”
`
`choosing from a finite number of identified, predictable solutions,
`
`with a reasonable expectation of success;
`
`f. there is known work in one field of endeavor that may prompt
`
`variations of it for use in either the same field or a different one
`
`based on design incentives or other market forces if the variations
`
`would have been predictable to a POSA;
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`g. there existed at the time of the invention a known problem for which
`
`there was an obvious solution encompassed by the patent’s claims;
`
`and
`
`h. there is some teaching, suggestion, or motivation in the prior art that
`
`would have led a POSA to modify the prior art reference or to
`
`combine prior art reference teachings to arrive at the claimed subject
`
`matter.
`
`27. Finally, I understand that a claim may be deemed invalid for
`
`obviousness in light of a single prior art reference, without the need to combine
`
`references, if the elements of the claim the reference does not expressly disclose
`
`are suggested by the reference or are within the knowledge or common sense of
`
`one of ordinary skill in the relevant art. In other words, a claim can be obvious in
`
`light of a single prior art reference if (i) the reference discloses or suggests each
`
`element of the claim and/or (ii) it would have been obvious to supplement or
`
`modify the reference based on the knowledge or common sense of a POSA to
`
`arrive at the claimed invention.
`
` Priority Date
`I understand that, subject to the next paragraph, the asserted “priority
`
`28.
`
`date” of a patent is the earlier of: (a) the date on which a patent application is filed;
`
`or (b) the date on which an earlier-filed patent application is filed if the patentee
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`10
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`properly claims the benefit of priority to that earlier-filed patent application.
`
`29.
`
`I understand that it is not enough for a patent to merely claim the benefit of
`
`an earlier-filed application, but that additional criteria must be met. In particular, the
`
`prior application itself must describe the claimed invention, and must do so in
`
`sufficient detail that one skilled in the art can clearly conclude that the inventor
`
`invented the claimed invention as of the filing date sought. First, I understand that a
`
`priority-date analysis is on a claim-by-claim basis. Second, I understand that, for a
`
`patent claim to be entitled to the filing date of an earlier patent application, a “Section
`
`112 analysis” must be conducted. I am informed that a “Section 112” analysis
`
`encompasses looking to the earlier patent application and ascertaining whether that
`
`earlier patent application meets both the written-description and enablement
`
`requirements as of the filing date of the earlier application. I understand that it is not
`
`enough that the claim would have been obvious from the earlier application, but that
`
`application itself must describe the claimed invention.
`
`30.
`
`I understand that to satisfy the written description requirement the
`
`earlier application must reasonably convey to those skilled in the art that the
`
`inventors had possession of the subject matter of the patent as of the filing date of
`
`the earlier application. I have been informed that it is the disclosures of the earlier
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`patent application that count, and that while the meaning of terms, phrases, or
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`diagrams in the earlier patent application must be interpreted from the vantage
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`11
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`LzLabs GmbH. Ex. 1003-18
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`IPR of U.S. Patent 8,713,289
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`point of one skilled in the art, all of the claimed limitations must appear in the
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`specification. Further, I understand that this analysis is not a question of whether
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`one skilled in the art might be able to construct the claimed invention from the
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`teachings of the disclosure. The question is not whether a claimed invention is an
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`obvious variant of that which is disclosed in the specification; rather, I understand
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`that an earlier application must itself describe each of the claim limitations.
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`31.
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`I also understand that to satisfy the enablement requirement, the
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`earlier application must enable a person of ordinary skill in the art to practice the
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`claimed invention without undue experimentation.
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`V. OVERVIEW OF THE ’289 PATENT
` Priority Date of the ’289 Patent
`I have reviewed the ’289 patent, which is entitled “Efficiently
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`32.
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`emulating computer architecture condition code settings without executing branch
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`instructions.” Ex. 1001 (54). I understand the application for the ’289 patent was
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`filed on January 30, 2007, and does not claim priority to an earlier filed
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`application. Ex. 1001, (22). I also understand that, in the district court litigation,
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`Patent Owner contends it is entitled to a priority date of March 22, 2006. For
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`purposes of my analysis, I have assumed that the priority date of the ’289 patent is
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`January 30, 2007, but my opinions would not change if I instead assumed a priority
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`date of March 22, 2006. I understand that the ’289 patent issued on April 29, 2014.
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`12
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`IPR of U.S. Patent 8,713,289
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`Ex. 1001, (45).
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` Subject Matter of the ’289 Patent
`33. The ’289 patent relates to a system that emulates the generation of
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`condition codes for instructions from a computer having a first architecture on a
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`computer having a different architecture, without using branch instructions. “In
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`virtually all modern data processing systems, the execution of various operations
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`such as arithmetic operations, logical operations and even data transfer operations,
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`may result in the generation of several bits of data to indicate the outcome status of
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`instruction execution. These bits are typically referred to as condition codes.” Ex.
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`1001, 1:18-23.
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`34. Because they are bits of data that indicate the outcome of instruction
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`execution, condition codes are often used as flags and they can be hardware-
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`specific. Ex. 1001, 1:18-49. They often include such things as overflow, zero
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`result, carry or borrow, and negative result codes. Condition codes may be set as a
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`side effect of the operation many instructions, and the codes often used by
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`subsequent conditional instructions, to take a particular action such as a branch or
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`to move data, based on the condition set. Thus, programmers who work with
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`assembly or machine language programs on machines whose instruction set
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`architectures have condition codes will often make use of the condition codes and
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`conditional branch instructions in the course of routine programming tasks
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`13
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`LzLabs GmbH. Ex. 1003-20
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`IPR of U.S. Patent 8,713,289
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`involving control flow.
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`35. Many processor instruction set architectures make use of condition
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`codes. Ex. 1024, 2-11; id., 3 (“Many architectures have included condition codes
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`as the primary method of implementing conditional control flow. Condition codes
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`provide an implicit communication between two otherwise disjoint instructions.”).
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`Some processors, such as the MIPS, provide instructions to set registers
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`conditionally, providing an alternate way to set values needed to implement control
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`flow logic. Id., 5.
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`36. The ’289 patent specification explains that when one processor is
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`emulating another, but does not use the same condition codes, emulating the
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`condition codes “adds considerable space and performance overhead to the emulated
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`instructions.” Ex. 1001, 2:59-61.
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`37. By way of example, the specification discusses the “conventional
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`handling of condition code generation,” in which the emulator generates a series of
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`if/then statements to determine and set the correct condition code value for a
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`compare instruction. Id., 1:64-2:7. The patent explains that “[i]n conventional
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`approaches to the emulation of a compare instruction, the result is the construction
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`of a sequence of instructions, which include three branch instructions.” Id., 2:7-10.
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`The specification explains that such branch instructions are undesired because
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`branch prediction may make an incorrect guess as to the path the program should
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`14
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`IPR of U.S. Patent 8,713,289
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`take, and because it may consume branch prediction resources so they are not
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`available for other instruction streams. Id., 2:14-20-32.
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`38. To avoid using branch instructions, the ’289 patent uses sequences of
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`code on the target computer to calculate condition codes that would have been
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`generated on the source computer. “The technique used herein to derive the
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`sequences is to implement very short one or two instruction sequence fragments
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`that set a bit or bits in a result or temporary register to distinguish each possible
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`outcome of a condition code setting. These small code fragments … are tied
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`toget