`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`_________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`_________________
`
`SAMSUNG ELECTRONICS CO., LTD.
`Petitioner
`
`v.
`
`
`CALIFORNIA INSTITUTE OF TECHNOLOGY
`Patent Owner
`
`_________________
`
`Patent No. 7,421,032
`_________________
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 7,421,032
`
`
`
`Petition for Inter Partes Review
`Patent No. 7,421,032
`
`TABLE OF CONTENTS
`I.
`INTRODUCTION ........................................................................................... 1
`II. MANDATORY NOTICES ............................................................................. 1
`III.
`PAYMENT OF FEES ..................................................................................... 3
`IV. GROUNDS FOR STANDING ........................................................................ 3
`V.
`PRECISE RELIEF REQUESTED AND GROUNDS .................................... 3
`VI. LEVEL OF ORDINARY SKILL .................................................................... 5
`VII. OVERVIEW OF THE ’032 PATENT ............................................................ 6
`VIII. CLAIM CONSTRUCTION ............................................................................ 6
`A.
`“repeat” .................................................................................................. 7
`IX. DETAILED EXPLANATION OF GROUNDS .............................................. 8
`A. Ground 1: Claims 1, 3-5, 7-8, 11-12, and 14-16 Are Anticipated
`By Kobayashi ........................................................................................ 8
`1.
`Claim 1 ........................................................................................ 8
`2.
`Claim 3 ...................................................................................... 21
`3.
`Claim 4 ...................................................................................... 21
`4.
`Claim 5 ...................................................................................... 21
`5.
`Claim 7 ...................................................................................... 24
`6.
`Claim 8 ...................................................................................... 25
`7.
`Claim 11 .................................................................................... 25
`8.
`Claim 12 .................................................................................... 30
`9.
`Claim 14 .................................................................................... 31
`10. Claim 15 .................................................................................... 32
`
`i
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`B.
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`C.
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`Petition for Inter Partes Review
`Patent No. 7,421,032
`11. Claim 16 .................................................................................... 32
`Ground 2: Claims 2, 6-7, 10, 13, and 17 Are Obvious Over
`Kobayashi ............................................................................................ 32
`1.
`Claim 2 ...................................................................................... 32
`2.
`Claim 6 ...................................................................................... 34
`3.
`Claim 7 ...................................................................................... 37
`4.
`Claim 10 .................................................................................... 40
`5.
`Claim 13 .................................................................................... 40
`6.
`Claim 17 .................................................................................... 42
`Ground 3: Claims 6, 13, and 18-22 Are Obvious Over Kobayashi
`and McEliece ....................................................................................... 43
`1.
`Claim 6 ...................................................................................... 52
`2.
`Claim 13 .................................................................................... 53
`3.
`Claim 18 .................................................................................... 54
`4.
`Claim 19 .................................................................................... 60
`5.
`Claim 20 .................................................................................... 61
`6.
`Claim 21 .................................................................................... 61
`7.
`Claim 22 .................................................................................... 64
`X. DISCRETIONARY DENIAL IS NOT APPROPRIATE HERE .................. 64
`A.
`The Board Should Not Use Its Discretion to Deny Institution
`Under Fintiv ........................................................................................ 64
`The Board Should Not Exercise Its Discretion Under General
`Plastic .................................................................................................. 70
`The Board Should Not Exercise Its Discretion Under Section
`325(d) .................................................................................................. 72
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`C.
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`B.
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`ii
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`Petition for Inter Partes Review
`Patent No. 7,421,032
`XI. CONCLUSION .............................................................................................. 73
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`iii
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`Petition for Inter Partes Review
`Patent No. 7,421,032
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`LIST OF EXHIBITS
`
`Ex. 1001
`
`U.S. Patent No. 7,421,032
`
`Ex. 1002
`
`Declaration of Matthew C. Valenti, Ph.D., P.E.
`
`Ex. 1003
`
`Curriculum Vitae of Matthew C. Valenti, Ph.D., P.E.
`
`Ex. 1004
`
`Prosecution History of U.S. Patent No. 7,421,032
`
`Ex. 1005
`
`U.S. Patent No. 6,029,264 to Kobayashi et al. (“Kobayashi”)
`
`Ex. 1006 McEliece et al., “Turbo Decoding as an Instance of Pearl’s ‘Belief
`Propogation’ Algorithm,” IEEE Journal On Selected Areas in
`Communication, Vol. 16, No. 2 (February 1998). (“McEliece”)
`
`Ex. 1007 MacKay, “A Free Energy Minimization Framework for Inference
`Problems in Modulo 2 Arithmetic,” Fast Software Encryption, B.
`Preneel, Ed. Berlin, Germany: Springer-Verlag Lecture Notes in
`Computer Science, Vol. 1008 (1995). (“MacKay”)
`
`Ex. 1008
`
`RESERVED
`
`Ex. 1009
`
`Ex. 1010
`
`Ex. 1011
`
`Rorabaugh, Error Coding Cookbook: Practical C/C++ Routines and
`Recipes for Error Detection and Correction (1996). (“Rorabaugh”)
`
`Lin & Costello, Error Control Coding: Fundamentals and
`Applications (1983). (“Lin/Costello”)
`
`the Construction of Efficient Multilevel Coded
`Cheng, “On
`Modulations,” Proceedings 1997 IEEE International Symposium on
`Information Theory (July 1997). (“Cheng I”)
`
`Ex. 1012
`
`Cheng, “Iterative Decoding,” Ph.D. dissertation, California Institute of
`Technology, Pasadena, CA (March 1997). (“Cheng II”)
`
`Ex. 1013
`
`RESERVED
`
`Ex. 1014
`
`RESERVED
`
`iv
`
`
`
`Ex. 1015
`
`Petition for Inter Partes Review
`Patent No. 7,421,032
`Docket Control Order (Dkt. No. 27), from California Institute of
`Technology v. Samsung Electronics Co., Ltd., No. 2-21-cv-00446
`(E.D. Tex.)
`
`Ex. 1016
`
`National Judicial Caseload Profile (June 30, 2022)
`
`First Amended Complaint (Dkt. No. 42), from California Institute of
`Technology v. Samsung Electronics Co., Ltd., No. 2-21-cv-00446
`(E.D. Tex.)
`
`Plaintiff Caltech’s Infringement Disclosures, Exhibit 2 (Preliminary
`Claim Chart for U.S. Patent No. 7,421,032), from California Institute
`of Technology v. Samsung Electronics Co., Ltd., No. 2-21-cv-00446
`(E.D. Tex.)
`
`Ex. 1017
`
`Ex. 1018
`
`
`
`v
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`Petition for Inter Partes Review
`Patent No. 7,421,032
`
`I.
`
`INTRODUCTION
`Samsung Electronics Co., Ltd. (“Petitioner” or “Samsung”) requests inter
`
`partes review of claims 1-8 and 10-22 (“challenged claims”) of U.S. Patent No.
`
`7,421,032 (“the ’032 patent”) (Ex. 1001) assigned to California Institute of
`
`Technology (“PO”). For the reasons below, the challenged claims should be found
`
`unpatentable and canceled.
`
`II. MANDATORY NOTICES
`Real Parties-in-Interest: Petitioner identifies the following as the real
`
`parties-in-interest: Samsung Electronics Co., Ltd., Samsung Electronics America,
`
`Inc.
`
`Related Matters: The ’032 patent is at issue in the following matters:
`
`• California Institute of Technology v. Samsung Electronics Co., Ltd., No.
`
`2-21-cv-00446 (E.D. Tex.) (alleging infringement of the ’032 patent and
`
`also U.S. Patent Nos. 7,116,710; 7,916,781; and 8,284,833) (“E.D. Texas
`
`Litigation”).
`
`• California Institute of Technology v. Microsoft Corp., No. 6-21-cv-00276
`
`(W.D. Tex.).
`
`• California Institute of Technology v. HP Inc. f/k/a/ Hewlett-Packard Co.,
`
`No. 6-20-cv-01041 (W.D. Tex.).
`
`1
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`
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`Petition for Inter Partes Review
`Patent No. 7,421,032
`• California Institute of Technology v. Dell Technologies Inc., No. 6-20-cv-
`
`01042 (W.D. Tex.).
`
`• California Institute of Technology v. Broadcom Ltd., No. 2-16-cv-03714
`
`(C.D. Cal.).
`
`The ’032 patent has previously been at issue in the following matters:
`
`• Apple Inc. v. California Institute of Technology, IPR2017-00700 (“Apple
`
`-700 IPR”).
`
`• Apple Inc. v. California Institute of Technology, IPR2017-00701 (“Apple
`
`-701 IPR”).
`
`• Apple Inc. v. California Institute of Technology, IPR2017-00728 (“Apple
`
`-728 IPR”).
`
`• California Institute of Technology v. Hughes Communications, Inc., No.
`
`2-15-cv-01108 (C.D. Cal.).
`
`• Hughes Communications, Inc. v. California Institute of Technology,
`
`IPR2015-00060 (“Hughes -060 IPR”).
`
`• California Institute of Technology v. Hughes Communications, Inc., No.
`
`2-13-cv-07245 (C.D. Cal.).
`
`Counsel and Service Information: Lead counsel: Robert A. Appleby (Reg.
`
`No. 40,897), and Backup counsel is Greg S. Arovas, P.C. (Reg. No. 38,818). Service
`
`information is Kirkland & Ellis, LLP, 601 Lexington Avenue, New York, NY
`2
`
`
`
`10022,
`
`Telephone:
`
`212.446.4800,
`
`Petition for Inter Partes Review
`Patent No. 7,421,032
`212.446.4900,
`Email:
`
`Facsimile:
`
`Samsung_Caltech_IPR@kirkland.com. Petitioner consents to electronic service.
`
`III. PAYMENT OF FEES
`The PTO is authorized to charge any fees due during this proceeding to
`
`Deposit Account No. 506092.
`
`IV. GROUNDS FOR STANDING
`Petitioner certifies that the ’032 patent is available for review and Petitioner
`
`is not barred/estopped from requesting review on the grounds identified herein.
`
`V.
`
`PRECISE RELIEF REQUESTED AND GROUNDS
`Claims 1-8 and 10-22 should be canceled as unpatentable based on the
`
`following grounds:
`
`Ground 1: Claims 1, 3-5, 7-8, 11-12, and 14-16 are unpatentable under pre-
`
`AIA 35 U.S.C. § 102(e) as anticipated by Kobayashi (Ex. 1005);
`
`Ground 2: Claims 2, 6-7, 10, 13, and 17 are unpatentable under § 103(a) as
`
`obvious over Kobayashi; and
`
`3
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`
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`Petition for Inter Partes Review
`Patent No. 7,421,032
`Ground 3: Claims 6, 13, and 18-22 are unpatentable under § 103(a) as
`
`obvious over Kobayashi and McEliece (Ex. 1006).1
`
`The ’032 patent issued from an application filed October 3, 2006, and claims
`
`priority to, inter alia, a provisional application filed May 18, 2000. Petitioner does
`
`not concede that the priority claim to the provisional application is proper, but for
`
`purposes of this proceeding, assumes the critical date for the ’032 patent is May 18,
`
`2000.
`
`Kobayashi was filed April 28, 1997 and issued on February 22, 2000, and thus
`
`qualifies as prior art at least under pre-AIA 35 U.S.C. §§ 102(a) and 102(e).
`
`McEliece is an article published in February 1998 in the IEEE Journal on
`
`Selected Areas in Communications. (Ex. 1006, Cover; see also id. (Library date
`
`stamp), 2 (“Copyright © 1998”).) The Board has routinely held IEEE publications
`
`like McEliece as printed publications. For example, “[t]he Board has previously
`
`observed that ‘IEEE is a well-known, reputable compiler and publisher of scientific
`
`and technical publications, and we take Official Notice that members in the scientific
`
`and technical communities who both publish and engage in research rely on the
`
`
`1 For the Grounds presented, Petitioner does not rely on any prior art reference other
`
`than those listed here. Any other references discussed are to show the state of the
`
`art.
`
`4
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`Petition for Inter Partes Review
`Patent No. 7,421,032
`information published on the copyright line of IEEE publications.’” Power
`
`Integrations, Inc., v. Semiconductor Components Industries, LLC, IPR2018-00377,
`
`Paper No. 10 at 10 (July 17, 2018) (quoting Ericsson, Inc. v. Intellectual Ventures I
`
`LLC, IPR2014-00527, Paper 41 at 11 (May 18, 2015)). Thus, McEliece qualifies as
`
`prior art at least under pre-AIA 35 U.S.C. § 102(b).
`
`These references were not considered during prosecution or prior IPRs. (See
`
`generally Ex. 1004.)
`
`VI. LEVEL OF ORDINARY SKILL
`A person of ordinary skill in the art at the time of the alleged invention
`
`(“POSITA”) would have had a Ph.D. in mathematics, electrical or computer
`
`engineering, or computer science with an emphasis in signal processing,
`
`communications, or coding, or a master’s degree in the above areas with at least
`
`three years of work experience in the field at the time of the alleged invention. (Ex.
`
`1002, ¶¶21-22.)2 Additional education would compensate for less experience, and
`
`vice versa. (Id.)
`
`
`2 Petitioner submits the declaration of Matthew C. Valenti, Ph.D., P.E. (Ex. 1002),
`
`an expert in the field of the ’032 patent. (Ex. 1002, ¶¶3-20; Ex. 1003.)
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`5
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`Petition for Inter Partes Review
`Patent No. 7,421,032
`
`VII. OVERVIEW OF THE ’032 PATENT
`The ’032 patent relates to “serial concatenation of interleaved convolutional
`
`codes forming turbo-like codes.” (Ex. 1001, Title; Ex. 1002, ¶¶36-39.) The ’032
`
`patent describes a “serial concatenated coder” that “includes an outer coder and an
`
`inner coder,” where the “outer coder irregularly repeats bits in a data block according
`
`to a degree profile and scrambles the repeated bits,” which are then “input to an inner
`
`coder, which has a rate substantially close to one.” (Ex. 1001, Abstract.)
`
`An exemplary embodiment of the alleged invention is disclosed by way of
`
`Figure 2. (Id., 2:35.)
`
`
`
`(Id., FIG. 2.; see also id. ¶¶23-35 (discussing technology background).)
`
`VIII. CLAIM CONSTRUCTION
`For IPR proceedings, the Board applies the claim construction standard set
`
`forth in Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005) (en banc). See 83
`
`Fed. Reg. 51,340-51,359 (Oct. 11, 2018). Petitioner below provides proposed
`
`6
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`Petition for Inter Partes Review
`Patent No. 7,421,032
`constructions under the Phillips standard for certain terms recited in claims 1(c),
`
`5(b), 7(b), 13(b)-(c), and 17 of the ’032 patent. For purposes of this proceeding,
`
`Petitioner believes that other than the term(s) discussed below in Section VIII.A, no
`
`other special constructions are necessary to assess whether the challenged claims are
`
`unpatentable over the asserted prior art, and thus any remaining terms should be
`
`given their plain and ordinary meaning.3 (Ex. 1002, ¶40.)
`
`A.
`“repeat”
`The term “repeat[],” as recited in claims 1(c), 5(b), 7(b), 13(b)-(c), and 17,
`
`should be construed to mean “generation of additional bits, where generation can
`
`include, for example, duplication or reuse of bits.” (See, e.g., Sections IX.A.1(c),
`
`IX.A.4(b), IX.A.5(b), IX.B.3(b), IX.B.5(b)-(c), IX.B.6, IX.C.2(b)-(c); Ex. 1002,
`
`¶41.)
`
`The Federal Circuit affirmed this construction of “repeat” in California Inst.
`
`of Tech. v. Broadcom Ltd., 25 F.4th 976, 986 (Fed. Cir. 2022) (“Broadcom
`
`litigation”). The Federal Circuit agreed with the district court and PO that the claims
`
`simply require bits to be repeated and do not limit how the duplicate bits are
`
`
`3 Petitioner reserves all rights to raise claim construction and other arguments,
`
`including challenges under 35 U.S.C. §§ 101 or 112, in district court as relevant to
`
`those proceedings.
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`7
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`Petition for Inter Partes Review
`Patent No. 7,421,032
`created/stored in memory. Id. Applying this construction, the Federal Circuit found
`
`that passing an input bit through an AND gate (when the other input was “1”) was
`
`“repeating” within the context of the asserted claims. Id. at 986-88.
`
`IX. DETAILED EXPLANATION OF GROUNDS
`A. Ground 1: Claims 1, 3-5, 7-8, 11-12, and 14-16 Are Anticipated By
`Kobayashi
`1.
`Claim 1
`a)
`A method comprising:
`To the extent the preamble of claim 1 is limiting, Kobayashi discloses the
`
`limitations therein. (Ex. 1002, ¶¶56-57; see also id., ¶¶42-48.) For example,
`
`Kobayashi discloses a concatenated system with a transmitter that receives message
`
`bits and uses several encoders that perform an encoding “method” as claimed. (Ex.
`
`1005, FIG. 8, 5:25-27, 7:5-8:34; Ex. 1002, ¶56; see also Sections IX.A.1(b)-(d).) In
`
`particular, Kobayashi discloses that the method (as shown in Figure 8 below)
`
`comprises receiving message bits from a source via a packet transmission system;
`
`encoding the sequence of message bits using the Hamming encoder, interleaver, and
`
`precoder to generate a sequence of parity bits; and transmitting the encoded sequence
`
`to the receiver via duobinary signaling. (Ex. 1005, 7:5-8:34; Ex. 1002, ¶57.)
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`8
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`Petition for Inter Partes Review
`Patent No. 7,421,032
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`(Ex. 1005, FIG. 8 (annotated); see also id., 5:17-24.)
`
`
`
`
`
`(Id., FIGS. 7A, 7B (showing generalized versions of Figure 8); Ex. 1002, ¶57.)
`
`b)
`
`receiving a collection of message bits having a first
`sequence in a source data stream;
`
`9
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`Petition for Inter Partes Review
`Patent No. 7,421,032
`Kobayashi discloses these limitations. (Ex. 1002, ¶58.) For example,
`
`Kobayashi discloses that the transmitter receives a 28-message-bit sequence I1
`
`(“collection of message bits having a first sequence”) in a source data stream (Ex.
`
`1005, 7:46-49 (describing receipt of data via “a simple packet transmission system
`
`in which there are 28 information bits in a packet, an example of which is given by
`
`the
`
`stream:
`
`I1=(0001001000110100010101100000).”)
`
`(emphasis
`
`added).)
`
`Kobayashi depicts the source of the data stream in Figure 8 below.
`
`
`
`(Ex. 1005, FIG. 8 (annotated); Ex. 1002, ¶58.)
`
`c)
`
`the formula (cid:2206)(cid:2192)(cid:3404)(cid:2206)(cid:2192)(cid:2879)(cid:2778)(cid:3397)∑ (cid:2204)(cid:4666)(cid:2192)(cid:2879)(cid:2778)(cid:4667)(cid:2183)(cid:2878)(cid:2191)
`(cid:2183)(cid:2191)(cid:2880)(cid:2778)
`the value of a parity bit “j-1,” and “∑ (cid:2204)(cid:4666)(cid:2192)(cid:2879)(cid:2778)(cid:4667)(cid:2183)(cid:2878)(cid:2191)
`(cid:2183)(cid:2191)(cid:2880)(cid:2778)
`
`generating a sequence of parity bits, wherein each
`parity bit “xj” in the sequence is in accordance with
` where “xj-1” is
`” is
`the value of a sum of “a” randomly chosen irregular
`
`10
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`Petition for Inter Partes Review
`Patent No. 7,421,032
`repeats of the message bits; and4
`Kobayashi discloses these limitations. (Ex. 1002, ¶¶59-72.) Kobayashi
`
`discloses that the received 28-message-bit sequence I1 is encoded in several steps,
`
`as shown below in Figure 8. (Id., ¶59.)
`
`(Ex. 1005, FIG. 8 (annotated); Ex. 1002, ¶59.)5 The 28-bit sequence I1 is “first
`
`segmented into blocks of k=4 bits, and each block is then encoded to a codeword of
`
`length n=7, by using a (7, 4) Hamming code.” (Ex. 1005, 7:50-53.) Kobayashi
`
`
`
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`4 See Certificate of Correction (CoC) appended to the ’032 patent.
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`5 As discussed further for claim 1(d), see infra Section IX.A.1(d), Kobayashi
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`discloses that duobinary signaling is a transmission technique for transmitting the
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`sequence of parity bits to the decoder. (Ex. 1002, ¶59 n.4.)
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`11
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`Patent No. 7,421,032
`discloses that the Hamming code’s parity-check and generator matrices are
`
`represented in systematic form as follows:
`
`
`
`(Id., 7:53-65.) After the Hamming encoder has been applied to all seven blocks of
`
`sequence I1, “the Hamming encoder output is the following 49 bits (commas are
`
`placed between code words for clarity): I2=(0001101, 0010111, 0011010, 0100011,
`
`0101110, 0110100, 0000000).” (Id., 7:66-8:2; Ex. 1002, ¶60.)
`
`Kobayashi’s method then uses a “7x7 block interleaver” to “perform a
`
`permutation action . . . which will store the above 49 bits [of I2] row-wise in the
`
`following array structure.”
`
`(Ex. 1005, 8:3-15.) Kobayashi discloses that the “permutation output is obtained by
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`“reading out the above array column by column as follows: I3=(0000000, 0001110,
`
`0110010, 1010100, 1100110, 0111100, 1101000).” (Id., 8:16-20; Ex. 1002, ¶61.)
`
`
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`12
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`Patent No. 7,421,032
`Kobayashi discloses that the sequence I3 is the input to the precoder. (Ex.
`
`1005, 8:18-27.) “The precoder output is obtained by taking the modulo-2 sum of the
`
`current input and the previous output (where ‘modulo-2 summation’ can be
`
`implemented by Exclusive OR: 0+0=0, 0+1=1, 1+0=1, 1+1=0).” (Id., 8:21-24.) In
`
`other words, “[t]he precoder maps the input binary sequence into another binary
`
`sequence, based on the following rule: when the current input is 0, the output should
`
`remain in the previous value; and when the input is 1, the output changes its value
`
`from the previous one, i.e. either 0 to 1 or from 1 to 0.” (Id., 7:33-37.) The resulting
`
`encoded sequence is “I4=(0000000, 0001011, 1011100, 1100111, 0111011,
`
`1010111, 011000[0]).” (Id., 8:25-27; Ex. 1002, ¶62.)6
`
`
`
`This generated sequence I4 is a “sequence of parity bits” because the precoder
`
`can be represented as a (49, 49) nonsystematic linear block code. (Ex. 1002, ¶63.)
`
`In particular, the precoder operation is equivalent to multiplying the 1x49 vector I3
`
`by a 49x49 generator matrix GA with “1”s both along and above the main diagonal
`
`and “0”s below the main diagonal, such as shown below, and obtaining 1x49 vector
`
`I4 (i.e., the sequence of parity bits) as a result. (Id.; see also Ex. 1009, 44 (“the
`
`
`6 The I4 sequence contains a typographical error and is missing the 49th bit, which is
`
`a “0” bit. (Ex. 1002, ¶62 n.5.)
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`13
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`Petition for Inter Partes Review
`Patent No. 7,421,032
`encoding operation [of a linear block code] is represented mathematically as
`
`v = u ∙ G, where v is a vector of the encoded data bits, u is a vector of k information
`
`bits, and G is the generator matrix” (emphasis in original)), 45 (describing a
`
`nonsystematic code as one that does not contain a k x k identity matrix)7.)
`
`GA = (cid:1743)(cid:1742)(cid:1742)(cid:1742)(cid:1741)1 1 1 ⋯ 1
`0 0 0 ⋯ 1(cid:1746)(cid:1745)(cid:1745)(cid:1745)(cid:1744)
`0 1 1 ⋯ 1
`0 0 1 ⋯ 1
`⋮
`⋮
`⋮
`⋱
`⋮
`
`
`
`(Ex. 1002, ¶63.) For such a nonsystematic linear block code, the bits of the
`
`codeword are parity bits. (See Ex. 1009, 45 (describing a nonsystematic code as
`
`having parity digits, and its corresponding generator matrix as being a matrix of
`
`parity-check coefficients); Ex. 1002, ¶63.)
`
`
`
`Furthermore, “each parity bit ‘xj’ in the sequence” I4 is represented by “the
`
`formula (cid:1876)(cid:3037)=(cid:1876)(cid:3037)(cid:2879)(cid:2869)+∑ (cid:1874)(cid:4666)(cid:3037)(cid:2879)(cid:2869)(cid:4667)(cid:3028)(cid:2878)(cid:3036)
`(cid:3028)(cid:3036)(cid:2880)(cid:2869)
`‘∑ (cid:1874)(cid:4666)(cid:3037)(cid:2879)(cid:2869)(cid:4667)(cid:3028)(cid:2878)(cid:3036)
`(cid:3028)(cid:3036)(cid:2880)(cid:2869)
`
` where ‘xj-1’ is the value of a parity bit ‘j-1,’ and
`
`’ is the value of a sum of ‘a’ randomly chosen irregular repeats of the
`
`message bits.” (Ex. 1002, ¶64.) As described above, in the precoder step, each
`
`parity bit of I4 is generated by taking the mod-2 sum (which is implemented using
`
`an exclusive-OR ‘XOR’ operation) of the previous parity bit of I4 and the current bit
`
`
`7 See n.1.
`
`14
`
`
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`Petition for Inter Partes Review
`Patent No. 7,421,032
`of I3. (Id.) That is, the jth bit of I4 (“xj”) equals the mod-2 sum of the “j-1”th bit of
`
`I4 (“(cid:1876)(cid:3037)(cid:2879)(cid:2869)”) and the jth bit of I3: (cid:1876)(cid:3037)=(cid:1876)(cid:3037)(cid:2879)(cid:2869)+[(cid:1862)(cid:1872)ℎ (cid:1854)(cid:1861)(cid:1872) (cid:1867)(cid:1858) (cid:1835)(cid:2871)]. (Id.)
`The jth bit of I3 is equal to ∑ (cid:1874)(cid:4666)(cid:3037)(cid:2879)(cid:2869)(cid:4667)(cid:3028)(cid:2878)(cid:3036)
`(cid:3028)(cid:3036)(cid:2880)(cid:2869)
`
`
`
`, i.e., “a sum of ‘a’ randomly chosen
`
`irregular repeats of the message bits.” (Id., ¶65.) As described above, in the first
`
`encoding step, each 4-bit block of I1 is multiplied by generator matrix G, and this
`
`process comprises irregular repetition of the message bits under the claim
`
`construction of “repeat” affirmed by the Federal Circuit in the Broadcom litigation.
`
`(See Section VIII.A; Ex. 1002, ¶65.) As discussed supra Section VIII.A, the Federal
`
`Circuit found that passing an input message bit through an AND gate when the other
`
`input is a “1” bit comprises “repeating” the message bit. (Section VIII.A.)
`
`Multiplying a binary message bit by a “1” bit is equivalent to passing the message
`
`bit through an AND gate with a “1” bit, and thus under this construction of “repeat,”
`
`multiplying an message bit by a “1” bit comprises “repeating” the message bit. (Ex.
`
`1002, ¶65; see also Ex. 1009, 7-8 (disclosing that binary/modulo-2 multiplication is
`
`equivalent to a bitwise AND operation).) Accordingly, under this construction, any
`
`type of linear code using a non-zero generator matrix will “repeat” input bits because
`
`the process of multiplying a vector of message bits by the generator matrix will
`
`necessarily involve multiplying input bits by “1” bits. (Ex. 1002, ¶65.)
`
`For example, as described above, Kobayashi’s Hamming encoder multiplies
`
`each 4-bit block of I1 by the 4x7 generator matrix G, resulting in seven 7-bit
`
`15
`
`
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`Petition for Inter Partes Review
`Patent No. 7,421,032
`codewords. (Id., ¶66.) This encoding step performs repetition of each and every
`
`message bit because the process of multiplying each 4-bit block by generator matrix
`
`G involves multiplying each input bits by at least one “1” bit (i.e., repeating the input
`
`bits) and then summing the repeated bits to generate the codeword. (Id.) Moreover,
`
`the message bits are repeated irregularly such that message bits are repeated a
`
`different number of times. (Id., ¶67.) The example below shows the first 4-bit block
`
`of sequence I1 being multiplied by 4x7 generator matrix G, where c1 through c4
`
`represent the first four message bits of I1. (Id.) As shown, the first, second, and
`
`fourth bits of the block are “repeated” (multiplied by a “1” bit) three times because
`
`the first, second, and fourth rows of generator matrix G each have three “1”s (in
`
`blue). (Id.) However, the third bit of the sub-block is repeated four times because
`
`the third row of generator matrix G has four “1”s (in yellow). (Id.) The 7-bit
`
`codeword is comprised of seven sums of “a” irregular repeats of the message bits,
`
`(cid:1855)(cid:2872)](cid:3430)1 0 0 0 1 1 0
`0 1 0 0 0 1 1
`0 0 0 1 1 0 1(cid:3434)=
`0 0 1 0 1 1 1
`
`16
`
`where a=1 (first four bits) and a=3 (last three bits). (Id.)
`
`[(cid:1855)(cid:2869)
`
`(cid:1855)(cid:2870)
`
`(cid:1855)(cid:2871)
`
`
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`Petition for Inter Partes Review
`Patent No. 7,421,032
`
`(cid:1743)(cid:1742)(cid:1742)(cid:1742)(cid:1742)(cid:1742)(cid:1742)(cid:1741)(cid:1855)(cid:2869)(cid:4666)1(cid:4667)+(cid:1855)(cid:2870)(cid:4666)0(cid:4667)+(cid:1855)(cid:2871)(cid:4666)0(cid:4667)+(cid:1855)(cid:2872)(0)
`(cid:1855)(cid:2869)(0)+(cid:1855)(cid:2870)(1)+(cid:1855)(cid:2871)(1)+(cid:1855)(cid:2872)(1)(cid:1746)(cid:1745)(cid:1745)(cid:1745)(cid:1745)(cid:1745)(cid:1745)(cid:1744)(cid:2955)
`
`(cid:1855)(cid:2869)(0)+(cid:1855)(cid:2870)(1)+(cid:1855)(cid:2871)(0)+(cid:1855)(cid:2872)(0)
`(cid:1855)(cid:2869)(0)+(cid:1855)(cid:2870)(0)+(cid:1855)(cid:2871)(1)+(cid:1855)(cid:2872)(0)
`(cid:1855)(cid:2869)(0)+(cid:1855)(cid:2870)(0)+(cid:1855)(cid:2871)(0)+(cid:1855)(cid:2872)(1)
`(cid:1855)(cid:2869)(1)+(cid:1855)(cid:2870)(0)+(cid:1855)(cid:2871)(1)+(cid:1855)(cid:2872)(1)
`(cid:1855)(cid:2869)(1)+(cid:1855)(cid:2870)(1)+(cid:1855)(cid:2871)(1)+(cid:1855)(cid:2872)(0)
`
`=
`
`(cid:1855)(cid:2869)(cid:1855)(cid:2870)(cid:1855)(cid:2871)(cid:1855)(cid:2872)
`(cid:1855)(cid:2870)+(cid:1855)(cid:2871)+(cid:1855)(cid:2872)(cid:1746)(cid:1745)(cid:1745)(cid:1745)(cid:1745)(cid:1745)(cid:1744)(cid:2955)
`(cid:1855)(cid:2869)+(cid:1855)(cid:2871)+(cid:1855)(cid:2872)
`(cid:1855)(cid:2869)+(cid:1855)(cid:2870)+(cid:1855)(cid:2871)
`
`(cid:1743)(cid:1742)(cid:1742)(cid:1742)(cid:1742)(cid:1742)(cid:1741)
`
`
`
`(Id.)
`
`When the full 28-bit sequence I1 is encoded via the Hamming encoder, the 3rd,
`
`7th, 11th, 15th, 19th, 23rd, and 27th bits are repeated four times, while the other 21 bits
`
`are repeated three times. (Id., ¶68.) Each of the 49 bits of sequence I2 is thus “a sum
`
`of ‘a’ . . . irregular repeats of the message bits,” where a=1 (no highlighting)8 or a=3
`
`(green highlighting), as shown below. (Id.)
`
`I1 = (c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16, c17, c18, c19, c20,
`c21, c22, c23, c24, c25, c26, c27, c28)
`I2 = (c1, c2, c3, c4, c1 + c3 + c4, c1 + c2 + c3, c2 + c3 + c4, c5, c6, c7, c8, c5 + c7 +
`c8, c5 + c6 + c7, c6 + c7 + c8, c9, c10, c11, c12, c9 + c11 + c12, c9 + c10 + c11, c10 +
`c11 + c12, c13, c14, c15, c16, c13 + c15 + c16, c13 + c14 + c15, c14 + c15 + c16, c17, c18,
`c19, c20, c17 + c19 + c20, c17 + c18 + c19, c18 + c19 + c20, c21, c22, c23, c24, c21 + c23
`+ c24, c21 + c22 + c23, c22 + c23 + c24, c25, c26, c27, c28, c25 + c27 + c28, c25 + c26 +
`c27, c26 + c27 + c28)
`The interleaver π permutes the sequence I2 to result in sequence I3, as shown
`
`below. (Id., ¶69.) The interleaver does not otherwise alter the bits of I2, and thus
`
`
`8 The specification admits “a” can be 1. (Ex. 1001, 4:42-45 (“IRA codes with a=1”).)
`
`17
`
`
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`Petition for Inter Partes Review
`Patent No. 7,421,032
`each bit of I3 is still “a sum of ‘a’ . . . irregular repeats of the message bits,” where
`
`(cid:2024)=
`
`(cid:1743)(cid:1742)(cid:1742)(cid:1742)(cid:1742)(cid:1742)(cid:1741)(cid:1855)(cid:2869)
`
`(cid:1855)(cid:2873)
`(cid:1855)(cid:2877)
`(cid:1855)(cid:2869)(cid:2871)
`(cid:1855)(cid:2869)(cid:2875)
`(cid:1855)(cid:2870)(cid:2869)
`(cid:1855)(cid:2870)(cid:2873)
`
`(cid:1855)(cid:2870)
`(cid:1855)(cid:2874)
`(cid:1855)(cid:2869)(cid:2868)
`(cid:1855)(cid:2869)(cid:2872)
`(cid:1855)(cid:2869)(cid:2876)
`(cid:1855)(cid:2870)(cid:2870)
`(cid:1855)(cid:2870)(cid:2874)
`
`(cid:1855)(cid:2871)
`(cid:1855)(cid:2875)
`(cid:1855)(cid:2869)(cid:2869)
`(cid:1855)(cid:2869)(cid:2873)
`(cid:1855)(cid:2869)(cid:2877)
`(cid:1855)(cid:2870)(cid:2871)
`(cid:1855)(cid:2870)(cid:2875)
`
`(cid:1855)(cid:2872)
`(cid:1855)(cid:2876)
`(cid:1855)(cid:2869)(cid:2870)
`(cid:1855)(cid:2869)(cid:2874)
`(cid:1855)(cid:2870)(cid:2868)
`(cid:1855)(cid:2870)(cid:2872)
`(cid:1855)(cid:2870)(cid:2876)
`
`(cid:1855)(cid:2869)+(cid:1855)(cid:2871)+(cid:1855)(cid:2872)
`(cid:1855)(cid:2873)+(cid:1855)(cid:2875)+(cid:1855)(cid:2876)
`(cid:1855)(cid:2877)+(cid:1855)(cid:2869)(cid:2869)+(cid:1855)(cid:2869)(cid:2870)
`(cid:1855)(cid:2869)(cid:2871)+(cid:1855)(cid:2869)(cid:2873)+(cid:1855)(cid:2869)(cid:2874)
`(cid:1855)(cid:2869)(cid:2875)+(cid:1855)(cid:2869)(cid:2877)+(cid:1855)(cid:2870)(cid:2868)
`(cid:1855)(cid:2870)(cid:2869)+(cid:1855)(cid:2870)(cid:2871)+(cid:1855)(cid:2870)(cid:2872)
`(cid:1855)(cid:2870)(cid:2873)+(cid:1855)(cid:2870)(cid:2875)+(cid:1855)(cid:2870)(cid:2876)
`
`(cid:1855)(cid:2869)+(cid:1855)(cid:2870)+(cid:1855)(cid:2871)
`(cid:1855)(cid:2873)+(cid:1855)(cid:2874)+(cid:1855)(cid:2875)
`(cid:1855)(cid:2877)+(cid:1855)(cid:2869)(cid:2868)+(cid:1855)(cid:2869)(cid:2869)
`(cid:1855)(cid:2869)(cid:2871)+(cid:1855)(cid:2869)(cid:2872)+(cid:1855)(cid:2869)(cid:2873)
`(cid:1855)(cid:2869)(cid:2875)+(cid:1855)(cid:2869)(cid:2876)+(cid:1855)(cid:2869)(cid:2877)
`(cid:1855)(cid:2870)(cid:2869)+(cid:1855)(cid:2870)(cid:2870)+(cid:1855)(cid:2870)(cid:2871)
`(cid:1855)(cid:2870)(cid:2873)+(cid:1855)(cid:2870)(cid:2874)+(cid:1855)(cid:2870)(cid:2875)
`
`a=1 (no highlighting) or a=3 (green highlighting), as shown below. (Id., ¶69.)
`
`(cid:1855)(cid:2870)+(cid:1855)(cid:2871)+(cid:1855)(cid:2872)
`(cid:1855)(cid:2874)+(cid:1855)(cid:2875)+(cid:1855)(cid:2876)
`(cid:1855)(cid:2869)(cid:2868)+(cid:1855)(cid:2869)(cid:2869)+(cid:1855)(cid:2869)(cid:2870)
`(cid:1855)(cid:2869)(cid:2872)+(cid:1855)(cid:2869)(cid:2873)+(cid:1855)(cid:2869)(cid:2874)
`(cid:1855)(cid:2869)(cid:2876)+(cid:1855)(cid:2869)(cid:2877)+(cid:1855)(cid:287