USOO7421032B2
`
`(12) United States Patent
`Jin et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7.421,032 B2
`Sep. 2, 2008
`
`(54) SERIAL CONCATENATION OF
`INTERLEAVED CONVOLUTIONAL CODES
`FORMING TURBO-LIKE CODES
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`(73) Assignee:
`
`(75) Inventors: Hui Jin, Glen Gardner, NJ (US); Aamod
`Khandekar, Pasadena, CA (US);
`Robert J. McEliece, Pasadena, CA (US)
`California Institute of Technology,
`Pasadena, CA (US)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(*)
`
`Notice:
`
`(21)
`(22)
`(65)
`
`(63)
`
`(60)
`
`(51)
`
`(52)
`
`(58)
`
`Appl. No.:
`
`11/542,950
`
`Filed:
`
`Oct. 3, 2006
`
`Prior Publication Data
`US 2007/OO25450 A1
`Feb. 1, 2007
`
`Related U.S. Application Data
`Continuation of application No. 09/861,102, filed on
`May 18, 2001, now Pat. No. 7,116,710, and a continu
`ation-in-part of application No. 09/922,852, filed on
`Aug. 18, 2000, now Pat. No. 7,089,477.
`Provisional application No. 60/205,095, filed on May
`18, 2000.
`
`Int. C.
`(2006.01)
`H04L 5/2
`U.S. Cl. ....................... 375/262; 375/265; 375/348;
`714/755: 714/786; 714/792: 341/52: 341/102
`Field of Classification Search ................. 375/259,
`375/262, 265, 285,296, 341, 346, 348; 714/746,
`714/752, 755, 756, 786, 792, 794 796: 341/51,
`341/52, 56, 102, 103
`See application file for complete search history.
`
`2f1995 Rhines et al.
`5,392.299 A
`6/1996 Lin ............................ 714/792
`5,530,707 A
`5/1998 Seshadri et al.
`5,751,739 A
`5,802,115 A * 9/1998 Meyer ........................ 375,341
`5,881,093 A
`3/1999 Wang et al.
`6,014,411 A
`1/2000 Wang
`6,023,783 A
`2/2000 Divsalar et al.
`6,031,874 A
`2/2000 Chennakeshu et al.
`6,032,284 A
`2, 2000 Bliss
`6,044,116 A
`3/2000 Wang
`6,094,739 A * 7/2000 Miller et al. ................ 714/792
`
`(Continued)
`OTHER PUBLICATIONS
`
`Appendix A. 1 "Structure of Parity Check Matrices of Standardized
`LDPC Codes.” Digital Video Broadcasting (DVB) User guidelines
`for the second generation system for Broadcasting, Interactive Ser
`vices, News Gathering and other broadband satellite applications
`(DVB-S2) ETSI TR 102376 V1.1.1. (Feb. 2005) Technical Report,
`pp. 64.
`
`(Continued)
`Primary Examiner Dac V. Ha
`(74) Attorney, Agent, or Firm—Fish & Richardson P.C.
`(57)
`ABSTRACT
`
`A serial concatenated coder includes an outer coder and an
`inner coder. The outer coder irregularly repeats bits in a data
`block according to a degree profile and Scrambles the
`repeated bits. The scrambled and repeated bits are input to an
`inner coder, which has a rate Substantially close to one.
`
`23 Claims, 5 Drawing Sheets
`
`Variable Node
`Fraction of nodes
`degree i
`
`Check Node
`degree a
`
`V
`&
`
`
`
`3.
`
`6.
`
`w
`
`X - - i 19
`
`
`
`
`
`
`
`
`
`
`
`e - - -
`302-1 vs.
`
`302- ?
`
`sm w
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`m :
`
`l,
`
`fi
`
`Page 1 of 14
`
`SAMSUNG EXHIBIT 1001
`
`

`

`US 7,421,032 B2
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`6,396.423 B1
`6,437,714 B1
`6,859,906 B2*
`2001/0025358 A1
`
`5/2002 Laumen et al.
`8, 2002 Kim et al.
`2/2005 Hammons et al. ........... T14f786
`9, 2001 Eidson et al.
`
`OTHER PUBLICATIONS
`Benedetto et al., “A Soft-Input Soft-Output Maximum A Posteriori
`(MAP) Module to Decode Parallel and Serial Concatenated Codes.”
`The Telecommunications and Data Acquisition (TDA) Progress
`Report 42-127 for NASA and California Institute of Technology Jet
`Propulsion Laboratory, Jospeh H. Yuen, Ed., pp. 1-20 (Nov. 15.
`1996).
`Benedetto et al., “Bandwidth efficient parallel concatenated coding
`schemes.” Electronics Letters 31(24): 2067-2069 (Nov. 23, 1995).
`Benedetto et al., “Design of Serially Concatenated Interleaved
`Codes.” ICC 97, Montreal, Canada, pp. 710-714, (Jun. 1997).
`Benedetto et al., “Parallel Concatenated Trellis Coded Modulation.”
`ICC'96, IEEE, pp. 974-978, (Jun. 1996).
`Benedetto et al., “Serial Concatenated Trellis Coded Modulation
`with Iterative Decoding.” Proceedings from the IEEE 1997 Interna
`tional Symposium on Information Theory (ISIT), Ulm, Germany, p.
`8, Jun. 29-Jul. 4, 1997.
`Benedetto et al., “Serial Concatenation of Interleaved Codes: Perfor
`mance Analysis, Design, and Iterative Decoding.” The Telecommu
`nications and Data Acquisition (TDA) Progress Report 42-126 for
`NASA and California Institute of Technology Jet Propulsion Labo
`ratory, Jospeh H. Yuen, Ed., pp. 1-26 (Aug. 15, 1996).
`Benedetto et al., “Serial Concatenation of interleaved codes: perfor
`mance analysis, design, and iterative decoding.” Proceedings from
`the IEEE 1997 International Symposium on Information Theory
`(ISIT), Ulm, Germany, p. 106, Jun. 29-Jul. 4, 1997.
`Benedetto et al., "Soft-output decoding algorithms in iterative decod
`ing of turbo codes.” The Telecommunications and Data Acquisition
`(TDA) Progress Report 42-124 for NASA and California Institute of
`Technology Jet Propulsion Laboratory, Jospeh H. Yuen, Ed., pp.
`63-87 (Feb. 15, 1996).
`Benedetto, S. et al., “A Soft-Input Soft-Output APP Module for
`Iterative Decoding of Concatenated Codes.” IEEE Communications
`Letters 1(1): 22-24 (Jan. 1997).
`Berrou et al., “Near Shannon Limit Error-Correcting Coding and
`Decoding: Turbo Codes.” ICC pp. 1064-1070 (1993).
`Digital Video Broadcasting (DVB) User guidelines for the second
`generation system for Broadcasting, Interactive Services, News
`Gathering and other broadband satellite applications (DVB-S2) ETSI
`TR 102376V1.1.1. (Feb. 2005) Technical Report, pp. 1-104 (Feb. 15,
`2005).
`
`Divsalar et al., "Coding Theorems for 'Turbo-Like' Codes.” Proceed
`ings of the 36" Annual Allerton Conference on Communication,
`Control, and Computing, Sep. 23-25, 1998, Allerton House,
`Monticello, Illinois, pp. 201-210 (1998).
`Divsalar et al., “Effective free distance of turbo codes.” Electronics
`Letters 32(5): 445-446 (Feb. 29, 1996).
`Divsalar, D. et al., "Hybrid Concatenated Codes and Iterative Decod
`ing.” Proceedings from the IEEE 1997 International Symposium on
`Information Theory (ISIT), Ulm, Germany, p. 10 (Jun. 29-Jul. 4.
`1997).
`Divsalar, D. et al., “Low-rate turbo codes for Deep Space Commu
`nications.” Proceedings from the 1995 IEEE International Sympo
`sium on Information Theory, Sep. 17-22, 1995, Whistler, British
`Columbia, Canada, pp. 35.
`Divsalar, D. et al., “Multiple Turbo Codes for Deep-Space Commu
`nications.” The Telecommunications and Data Acquisition (TDA)
`Progress Report 42-121 for NASA and California Institute of Tech
`nology Jet Propulsion Laboratory, Jospeh H. Yuen, Ed., pp. 60-77
`(May 15, 1995).
`Divsalar, D. et al., “Multiple Turbo Codes.” MILCOM 95, San Diego,
`CApp. 279-285 (Nov. 5-6, 1995).
`Divsalar, D. et al., “On the Design of Turbo Codes.” The Telecom
`munications and Data Acquisition (TDA) Progress Report 42-123 for
`NASA and California Institute of Technology Jet Propulsion Labo
`ratory, Jospeh H. Yuen, Ed., pp. 99-131 (Nov. 15, 1995).
`Divsalar, D. et al., “Serial Turbo Trellis Coded Modulation with
`Rate-1 Inner Code.” Proceedings from the IEEE 2000 International
`Symposium on Information Theory (ISIT), Italy, pp. 1-14 (Jun.
`2000).
`Divsalar, D. et al., “Turbo Codes for PCS Applications.” ICC 95.
`IEEE, Seattle, WA, pp. 54-59 (Jun. 1995).
`Jin et al., "Irregular Repeat—Accumulate Codes. 2nd International
`Symposium on Turbo Codes & Related Topics, Sep. 4-7, 2000, Brest,
`France, 25 slides, (presented on Sep. 4, 2000).
`Jin et al., “Irregular Repeat—Accumulate Codes. 2" International
`Symposium on Turbo Codes & Related Topics, Sep. 4-7, 2000, Brest,
`France, pp. 1-8 (2000).
`Richardson et al., “Design of capacity approaching irregular low
`density parity check codes.” IEEE Trans. Inform. Theory 47: 619-637
`(Feb. 2001).
`Richardson, T. and R. Urbanke, “Efficient encoding of low-density
`parity check codes.” IEEE Trans. Inform. Theory 47: 638-656 (Feb.
`2001).
`Wilberg, et al., “Codes and Iteratie Decoding on General Graphs”.
`1995 Intl. Symposium on Information Theory, Sep. 1995, p. 468.
`* cited by examiner
`
`Page 2 of 14
`
`

`

`U.S. Patent
`U.S. Patent
`
`Sep. 2, 2008
`Sep. 2, 2008
`
`Sheet 1 of 5
`Sheet 1 of 5
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`US 7.421,032 B2
`US 7,421,032 B2
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`FIG.1 (PriorArt) oS
`
`TANNVHO
`
`s
`
`
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`S&S
`fh
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`U.S. Patent
`U.S. Patent
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`Sep. 2, 2008
`Sep. 2, 2008
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`Sheet 2 of 5
`Sheet 2 of 5
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`US 7.421,032 B2
`US 7,421,032 B2
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`Page 4 of 14
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`

`

`U.S. Patent
`
`Sep. 2, 2008
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`Sheet 3 of 5
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`US 7.421,032 B2
`
`Variable Node
`
`Check Node
`
`
`
`FIG. 3
`
`Page 5 of 14
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`

`

`U.S. Patent
`U.S. Patent
`
`Sep. 2, 2008
`Sep. 2, 2008
`
`Sheet 4 of 5
`Sheet 4 of 5
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`US 7.421,032 B2
`US 7,421,032 B2
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` 304
`
`304
`
`FIG. 5A
`FIG. 5A
`
`
`
`
`
`FIG. 5B
`FIG. 5B
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`Sep. 2, 2008
`Sep. 2, 2008
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`Sheet 5 of 5
`Sheet 5 of 5
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`US 7.421,032 B2
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`U.S. Patent
`U.S. Patent
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`

`

`US 7,421,032 B2
`
`1.
`SERIAL CONCATENATION OF
`INTERLEAVED CONVOLUTIONAL CODES
`FORMING TURBO-LIKE CODES
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This application is a continuation of U.S. application Ser.
`No. 09/861,102, filed May 18, 2001, now U.S. Pat. No. 7,116,
`710, which claims the priority of U.S. provisional application
`Ser. No. 60/205,095, filed May 18, 2000, and is a continua
`tion-in-part of U.S. application Ser. No. 09/922,852, filed
`Aug. 18, 2000, now U.S. Pat. No. 7,089,477.
`
`GOVERNMENT LICENSE RIGHTS
`
`10
`
`15
`
`The U.S. Government has a paid-up license in this inven
`tion and the right in limited circumstances to require the
`patent owner to license others on reasonable terms as pro
`vided for by the terms of Grant No. CCR-9804793 awarded
`by the National Science Foundation.
`
`BACKGROUND
`
`25
`
`30
`
`35
`
`Properties of a channel affect the amount of data that can be
`handled by the channel. The so-called “Shannon limit”
`defines the theoretical limit of the amount of data that a
`channel can carry.
`Different techniques have been used to increase the data
`rate that can be handled by a channel. “Near Shannon Limit
`Error-Correcting Coding and Decoding: Turbo Codes.” by
`Berrou et al. ICC, pp 1064-1070, (1993), described a new
`“turbo code” technique that has revolutionized the field of
`error correcting codes. Turbo codes have sufficient random
`ness to allow reliable communication over the channel at a
`high data rate near capacity. However, they still retain Suffi
`cient structure to allow practical encoding and decoding algo
`rithms. Still, the technique for encoding and decoding turbo
`codes can be relatively complex.
`40
`A standard turbo coder 100 is shown in FIG.1. A block of
`k information bits is input directly to a first coder 102. A kbit
`interleaver 106 also receives the kbits and interleaves them
`prior to applying them to a second coder 104. The second
`coderproduces an output that has more bits than its input, that
`is, it is a coder with rate that is less than 1. The coders 102,104
`are typically recursive convolutional coders.
`Three different items are sent over the channel 150: the
`original kbits, first encoded bits 110, and second encoded bits
`112. At the decoding end, two decoders are used: a first
`constituent decoder 160 and a second constituent decoder
`162. Each receives both the original k bits, and one of the
`encoded portions 110, 112. Each decoder sends likelihood
`estimates of the decoded bits to the other decoders. The esti
`mates are used to decode the uncoded information bits as
`corrupted by the noisy channel.
`
`45
`
`50
`
`55
`
`SUMMARY
`
`A coding system according to an embodiment is config
`ured to receive a portion of a signal to be encoded, for
`example, a data block including a fixed number of bits. The
`coding system includes an outer coder, which repeats and
`scrambles bits in the data block. The data block is apportioned
`into two or more sub-blocks, and bits in different sub-blocks
`are repeated a different number of times according to a
`selected degree profile. The outer coder may include a
`
`60
`
`65
`
`2
`repeater with a variable rate and an interleaver. Alternatively,
`the outer coder may be a low-density generator matrix
`(LDGM) coder.
`The repeated and scrambled bits are input to an inner coder
`that has a rate Substantially close to one. The inner coder may
`include one or more accumulators that perform recursive
`modulo two addition operations on the input bit stream.
`The encoded data output from the inner coder may be
`transmitted on a channel and decoded in linear time at a
`destination using iterative decoding techniques. The decod
`ing techniques may be based on a Tanner graph representation
`of the code.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a schematic diagram of a prior “turbo code'
`system.
`FIG. 2 is a schematic diagram of a coder according to an
`embodiment.
`FIG. 3 is a Tanner graph for an irregular repeat and accu
`mulate (IRA) coder.
`FIG. 4 is a schematic diagram of an IRA coderaccording to
`an embodiment.
`FIG. 5A illustrates a message from a variable node to a
`check node on the Tanner graph of FIG. 3.
`FIG. 5B illustrates a message from a check node to a
`variable node on the Tanner graph of FIG. 3.
`FIG. 6 is a schematic diagram of a coder according to an
`alternate embodiment.
`FIG. 7 is a schematic diagram of a coder according to
`another alternate embodiment.
`
`DETAILED DESCRIPTION
`
`FIG. 2 illustrates a coder 200 according to an embodiment.
`The coder 200 may include an outer coder 202, an interleaver
`204, and inner coder 206. The coder may be used to format
`blocks of data for transmission, introducing redundancy into
`the stream of data to protect the data from loss due to trans
`mission errors. The encoded data may then be decoded at a
`destination in linear time at rates that may approach the chan
`nel capacity.
`The outer coder 202 receives the uncoded data. The data
`may be partitioned into blocks of fixed size, say kbits. The
`outer coder may be an (nk) binary linear block coder, where
`n>k. The coder accepts as input a block u of k data bits and
`produces an output block V of n data bits. The mathematical
`relationship between u and V is V=Tou, where To is an nxk
`matrix, and the rate of the coder is k/n.
`The rate of the coder may be irregular, that is, the value of
`To is not constant, and may differ for sub-blocks of bits in the
`data block. In an embodiment, the outer coder 202 is a
`repeater that repeats the kbits in a block a number of times q
`to produce a block with n bits, where n=qk. Since the repeater
`has an irregular output, different bits in the block may be
`repeated a different number of times. For example, a fraction
`of the bits in the block may be repeated two times, a fraction
`of bits may be repeated three times, and the remainder of bits
`may be repeated four times. These fractions define a degree
`sequence, or degree profile, of the code.
`The inner coder 206 may be a linear rate-1 coder, which
`means that the n-bit output block X can be written as x=Tw,
`where T is a nonsingular nxin matrix. The inner coder 210 can
`have a rate that is close to 1, e.g., within 50%, more preferably
`10% and perhaps even more preferably within 1% of 1.
`In an embodiment, the inner coder 206 is an accumulator,
`which produces outputs that are the modulo two (mod-2)
`
`Page 8 of 14
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`

`

`3
`partial Sums of its inputs. The accumulator may be a truncated
`rate-1 recursive convolutional coder with the transfer func
`tion 1/(1+D). Such an accumulator may be considered a block
`coder whose input block X . . . .X., and output block
`y, ... y, are related by the formula
`y=X
`
`2x1st-2
`
`y’s X&tx2Dx3
`
`yxietx2Dx3D. . . Dix.
`
`US 7,421,032 B2
`
`4
`. .X.), as follows. Each of the information bits is
`.
`(X, .
`associated with one of the information nodes 302, and each of
`the parity bits is associated with one of the parity nodes 306.
`The value of a parity bit is determined uniquely by the con
`dition that the mod-2 sum of the values of the variable nodes
`connected to each of the check nodes 304 is zero. To see this,
`set X-0. Then if the values of the bits on the raedges coming
`out the permutation box are (v. . . . . V.), then we have the
`recursive formula
`
`5
`
`10
`
`15
`
`for i=1,2,..., r. This is in effect the encoding algorithm.
`Two types of IRA codes are represented in FIG. 3, a non
`systematic version and a systematic version. The nonsystem
`atic version is an (rk) code, in which the codeword corre
`sponding to the information bits (u. . . . .u.) is (x1,..., X, ).
`The systematic version is a (k+r, k) code, in which the code
`Word is (u,..., u : X1, ..., X, ).
`The rate of the nonsystematic code is
`
`Rass =
`
`C
`
`i
`
`The rate of the systematic code is
`
`Rss =
`
`C
`
`i
`
`For example, regular repeat and accumulate (RA) codes
`can be considered nonsystematic IRA codes with a-1 and
`exactly one f, equal to 1, say f -1, and the rest Zero, in which
`case R,
`simplifies to R=1/q.
`The IRA code may be represented using an alternate nota
`tion. Let X be the fraction of edges between the information
`nodes 302 and the check nodes 304 that are adjacent to an
`information node of degreei, and let p, be the fraction of such
`edges that are adjacent to a check node of degree i+2 (i.e., one
`that is adjacent to i information nodes). These edge fractions
`may be used to represent the IRA code rather than the corre
`sponding node fractions. Define (x)=X,x' and p(x)=x.p,
`x'' to be the generating functions of these sequences. The
`pair (W, p) is called a degree distribution. For L(X)=X, fix,
`
`25
`
`30
`
`35
`
`where "eD' denotes mod-2, or exclusive-OR (XOR), addition.
`An advantage of this system is that only mod-2 addition is
`necessary for the accumulator. The accumulator may be
`embodied using only XOR gates, which may simplify the
`design.
`The bits output from the outer coder 202 are scrambled
`before they are input to the inner coder 206. This scrambling
`may be performed by the interleaver 204, which performs a
`pseudo-random permutation of an input block V, yielding an
`output block w having the same length as V.
`The serial concatenation of the interleaved irregular repeat
`code and the accumulate code produces an irregular repeat
`and accumulate (IRA) code. An IRA code is a linear code, and
`as such, may be represented as a set of parity checks. The set
`of parity checks may be represented in a bipartite graph,
`called the Tanner graph, of the code. FIG. 3 shows a Tanner
`graph 300 of an IRA code with parameters (f, ..., f: a),
`where fe0, X., f=1 and “a” is a positive integer. The Tanner
`graph includes two kinds of nodes: Variable nodes (open
`circles) and check nodes (filled circles). There are k variable
`nodes 302 on the left, called information nodes. There are r
`variable nodes 306 on the right, called parity nodes. There are
`r=(kX,if)/a check nodes 304 connected between the informa
`tion nodes and the parity nodes. Each information node 302 is
`connected to a number of check nodes 304. The fraction of
`information nodes connected to exactly i check nodes is f.
`For example, in the Tanner graph 300, each of the f, informa
`tion nodes are connected to two check nodes, corresponding
`to a repeat of q2, and each of the f information nodes are
`connected to three check nodes, corresponding to q3.
`Each check node 304 is connected to exactly “a” informa- so
`tion nodes 302. In FIG. 3, a 3. These connections can be
`made in many ways, as indicated by the arbitrary permutation
`of the ra edges joining information nodes 302 and check
`nodes 304 in permutation block 310. These connections cor
`respond to the scrambling performed by the interleaver 204. ss
`In an alternate embodiment, the outer coder 202 may be a
`low-density generator matrix (LDGM) coder that performs
`an irregular repeat of the kbits in the block, as shown in FIG.
`4. As the name implies, an LDGM code has a sparse (low
`density) generator matrix. The IRA code produced by the 60
`coder 400 is a serial concatenation of the LDGM code and the
`accumulator code. The interleaver 204 in FIG. 2 may be
`excluded due to the randomness already present in the struc
`ture of the LDGM code.
`If the permutation performed in permutation block 310 is 65
`fixed, the Tanner graph represents a binary linear block code
`with k information bits (u, .
`.
`. , u) and r parity bits
`
`40
`
`45
`
`Page 9 of 14
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`

`5
`The rate of the systematic IRA code given by the degree
`distribution is given by
`
`US 7,421,032 B2
`
`10
`
`15
`
`“Belief propagation' on the Tanner Graph realization may
`be used to decode IRA codes. Roughly speaking, the belief
`propagation decoding technique allows the messages passed
`on an edge to represent posterior densities on the bit associ
`ated with the variable node. A probability density on a bit is a
`pair of non-negative real numbers p(0), p(1) satisfying p(0)+
`p(1)=1, where p(0) denotes the probability of the bit being 0.
`p(1) the probability of it being 1. Such a pair can be repre
`sented by its log likelihood ratio, m=log(p(0)/p(1)). The out
`going message from a variable node u to a check node V
`represents information about u, and a message from a check
`node u to a variable node V represents information aboutu, as
`shown in FIGS.5A and 5B, respectively.
`The outgoing message from a node u to a node V depends
`on the incoming messages from all neighbors wofu except V.
`If u is a variable message node, this outgoing message is
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`where mo(u) is the log-likelihood message associated with
`u. If u is a check node, the corresponding formula is
`
`tanh
`
`tanh" - it)
`2
`
`wife
`
`Before decoding, the messages m(w->u) and mCu->V) are
`initialized to be Zero, and mo(u) is initialized to be the log
`likelihood ratio based on the channel received information. If
`the channel is memoryless, i.e., each channel output only
`
`65
`
`6
`relies on its input, and y is the output of the channel code bit
`u, then mo(u)=log(p(u=0ly)/p(u=1|y)). After this initializa
`tion, the decoding process may run in a fully parallel and local
`manner. In each iteration, every variable/check node receives
`messages from its neighbors, and sends back updated mes
`sages. Decoding is terminated after a fixed number of itera
`tions or detecting that all the constraints are satisfied. Upon
`termination, the decoder outputs a decoded sequence based
`on the messages m(u) X w(w->u).
`Thus, on various channels, iterative decoding only differs
`in the initial messages mo(u). For example, consider three
`memory less channel models: a binary erasure channel
`(BEC); a binary symmetric channel (BSC); and an additive
`white Gaussian noise (AGWN) channel.
`In the BEC, there are two inputs and three outputs. When 0
`is transmitted, the receiver can receive either 0 oran erasure E.
`An erasure E output means that the receiver does not know
`how to demodulate the output. Similarly, when 1 is transmit
`ted, the receiver can receive either 1 or E. Thus, for the BEC,
`ye {0, E, 1 }, and
`
`+co if y = 0
`if y = E
`mo(u) = - 0
`-co if y = 1
`
`In the BSC, there are two possible inputs (0,1) and two
`possible outputs (0, 1). The BSC is characterized by a set of
`conditional probabilities relating all possible outputs to pos
`sible inputs. Thus, for the BSC ye {0, 1},
`
`no (it) =
`
`log
`
`if y = 0
`
`-log
`
`if y = 1
`
`and
`In the AWGN, the discrete-time input symbols X take their
`values in a finite alphabet while channel output symbols Y can
`take any values along the real line. There is assumed to be no
`distortion or other effects other than the addition of white
`Gaussian noise. In an AWGN with a Binary Phase Shift
`Keying (BPSK) signaling which maps 0 to the symbol with
`amplitude Es and 1 to the symbol with amplitude - Es.
`outputy e R, then
`
`where No/2 is the noise power spectral density.
`
`Page 10 of 14
`
`

`

`US 7,421,032 B2
`
`7
`The selection of a degree profile for use in a particular
`transmission channel is a design parameter, which may be
`affected by various attributes of the channel. The criteria for
`selecting aparticular degree profile may include, for example,
`the type of channel and the data rate on the channel. For
`example, Table 1 shows degree profiles that have been found
`to produce good results for an AWGN channel model.
`
`10
`
`15
`
`TABLE 1.
`
`8.
`
`2
`
`3
`
`4
`
`2
`3
`5
`6
`10
`11
`12
`13
`14
`16
`27
`28
`Rate
`oGA
`cy:
`(Eb/NO) * (dB)
`S.L. (dB)
`
`O.139025
`0.2221555
`
`O.63882O
`
`O.O781.94
`O.12808S
`O.160813
`O.O361.78
`
`O.108828
`O.487902
`
`O.333364
`1.1840
`1.1981
`O.190
`-0.4953
`
`O.333223
`1.2415
`1.26O7
`-O.250
`-0.4958
`
`O.OS4485
`O. 104315
`
`0.126755
`O.229816
`O.O16484
`
`O.4SO3O2
`O.O17842
`O.333218
`1.2615
`1.2780
`-0.371
`-0.4958
`
`where
`“x” is the value of a parity bit j-1 and
`
`2.
`
`is the value of a sum of 'a' randomly chosen irregular repeats
`of the message bits; and
`making the sequence of parity bits available for transmis
`sion in a transmission data stream.
`2. The method of claim 1, wherein the sequence of parity
`bits is generated is in accordance with 'a' being constant.
`3. The method of claim 1, wherein the sequence of parity
`bits is generated is in accordance with “a” varying for differ
`ent parity bits.
`4. The method of claim 1, wherein generating the sequence
`of parity bits comprises performing recursive modulo two
`addition operations on the random sequence of bits.
`5. The method of claim 1, wherein generating the sequence
`of parity bits comprises:
`generating a random sequence of bits that repeats each of
`the message bits one or more times with the repeats of
`the message bits being distributed in a random sequence,
`wherein different fractions of the message bits are each
`repeated a different number of times and the number of
`repeats for each message bit is irregular; and
`XOR Summing in linear sequential fashion a predecessor
`parity bit and “a bits of the random sequence of bits.
`6. The method of claim 5, wherein generating the random
`sequence of bits comprises coding the collection of message
`bits using a low-density generator matrix (LDGM) coder.
`7. The method of claim 5, wherein generating the random
`sequence of bits comprises:
`producing a block of data bits, wherein different message
`bits are each repeated a different number of times in a
`sequence that matches the first sequence; and
`randomly permuting the different bits to generate the ran
`dom sequence.
`8. The method of claim 1, further comprising transmitting
`the sequence of parity bits.
`9. The method of claim 8, wherein transmitting the
`sequence of parity bits comprises transmitting the sequence
`of parity bits as part of a nonsystematic code.
`10. The method of claim 8, wherein transmitting the
`sequence of parity bits comprises transmitting the sequence
`of parity bits as part of a systematic code.
`11. A device comprising:
`an encoder configured to receive a collection of message
`bits and encode the message bits to generate a collection
`of parity bits in accordance with the following Tanner
`graph:
`
`30
`
`35
`
`Table 1 shows degree profiles yielding codes of rate
`approximately /3 for the AWGN channel and with a 2, 3, 4.
`For each sequence, the Gaussian approximation noise thresh
`old, the actual Sum-product decoding threshold and the cor
`responding energy per bit (E)-noise power (No) ratio in dB
`are given. Also listed is the Shannon limit (S.L.).
`As the parameter 'a' is increased, the performance
`improves. For example, for a 4, the best code found has an
`iterative decoding threshold of E/No-0.371 dB, which is
`only 0.12 dB above the Shannon limit.
`The accumulator component of the coder may be replaced
`by a “double accumulator 600 as shown in FIG. 6. The
`40
`double accumulator can be viewed as a truncated rate 1 con
`volutional coder with transfer function 1/(1+D+D).
`Alternatively, a pair of accumulators may be the added, as
`shown in FIG. 7. There are three component codes: the
`“outer code 700, the “middle' code 702, and the “inner
`code 704. The outer code is an irregular repetition code, and
`the middle and inner codes are both accumulators.
`IRA codes may be implemented in a variety of channels,
`including memoryless channels, such as the BEC, BSC, and
`AWGN, as well as channels having non-binary input, non
`symmetric and fading channels, and/or channels with
`memory.
`A number of embodiments have been described. Neverthe
`less, it will be understood that various modifications may be
`made without departing from the spirit and scope of the
`invention. Accordingly, other embodiments are within the
`Scope of the following claims.
`
`45
`
`50
`
`55
`
`The invention claimed is:
`1. A method comprising:
`receiving a collection of message bits having a first
`sequence in a source data stream;
`generating a sequence of parity bits, wherein each parity bit
`“x,” in the sequence is in accordance with the formula
`
`60
`
`65
`
`Page 11 of 14
`
`

`

`US 7,421,032 B2
`
`10
`message passing decoder comprising two or more
`check/variable nodes operating in parallel to receive
`messages from neighboring check/variable nodes and
`send updated messages to the neighboring variable/
`check nodes, wherein the message passing decoder is
`configured to decode the received data stream that has
`been encoded in accordance with the following Tanner
`graph:
`
`Z.
`C
`
`P
`e
`Y
`s
`e
`C
`
`3
`
`:
`
`i (
`
`E t w
`
`10
`
`
`
`15
`
`25
`
`30
`
`Z,
`C
`
`H s Y
`
`>
`O
`2
`3
`
`40
`
`19. The device of claim 18, wherein the message passing
`decoder is configured to decode the received data stream that
`includes the message bits.
`20. The device of claim 18, wherein the message passing
`decoder is configured to decode the received data stream as if
`a number of inputs into nodes V, was not constant.
`21. The device of claim 18, wherein the message passing
`decoder is configured to decode in linear time at rates that
`approach a capacity of a channel.
`22. The device of claim 18, wherein the message passing
`decoder comprises a belief propagation decoder.
`23. The device of claim 18, wherein the message passing
`decoder is configured to decode the received data stream
`without the message bits.
`
`12. The device of claim 11, wherein the encoder is config
`35
`ured to generate the collection of parity bits as if a number of
`inputs into nodes V, was not constant.
`13. The device of claim 11, wherein the encoder comprises:
`a low-density generator matrix (LDGM) coder configured
`to perform an irregular repeat on message bits having a
`first sequence in a source data stream to output a random
`sequence of repeats of the message bits; and
`an accumulator configured to XOR sum in linear sequen
`tial fashion a predecessor parity bit and “a bits of the
`random sequence of repeats of the message bits.
`45
`14. The device of claim 12, wherein the accumulator com
`prises a recursive convolutional coder.
`15. The device of claim 14, wherein the recursive convo
`lutional coder comprises a truncated rate-1 recursive convo
`lutional coder.
`16. The device of claim 14, wherein the recursive convo
`lutional coder has a transfer function of 1/(1+D).
`17. The device of claim 12, further comprising a second
`accumulator configured to determine a second sequence of
`parity bits that defines a second condition that constrains the
`random sequence of repeats of the message bits.
`18. A device comprising:
`a message passing decoder configured to decode a received
`data stream that includes a collection of parity bits, the
`
`50
`
`55
`
`Page 12 of 14
`
`

`

`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`CERTIFICATE OF CORRECTION
`
`: 7421,032 B2
`PATENT NO.
`APPLICATIONNO. : 1 1/542950
`DATED
`: September 2, 2008
`INVENTOR(S)
`: Hui Jin, Aamod Khandekar and Robert J. McEliece
`
`Page 1 of 1
`
`It is certified that error appears in the above-identified patent and that said Letters Patent is
`hereby corrected as shown below:
`
`Title Page, item 73 (Assignee), line 1, please delete “Callifornia and insert
`--California--, therefor.
`
`Claim 11, Column 9, line 28, delete “V” and insert --V--, therefor.
`
`Claim 11, Column 9, line 29, delete “U” and insert --U--, therefor.
`
`Claim 11, Column 9, line 29, delete “X, and insert --X--, therefor.
`
`Claim 18, Column 10, line 35, delete “V” and insert --V--, therefor.
`
`Claim 18, Column 10, line 36, delete “U1 and insert --U--, therefor.
`
`Claim 18, Column 10, line 37, delete “X, and insert --X--, therefor.
`
`Signed and Sealed this
`
`Seventeenth Day of February, 2009
`
`4 (O-e-
`
`JOHN DOLL
`Acting Director of the United States Patent and Trademark Office
`
`Page 13 of 14
`
`

`

`UNITED STATES PATENT AND TRADEMARK OFFICE
`CERTIFICATE OF CORRECTION
`
`7,421,032 B2
`PATENT NO.
`APPLICATION NO. : 1 1/542950
`DATED
`: September 2, 2008