Paper No. ___
`Filed: February 10, 2023
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`_____________________________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________________________
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`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`
`v.
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`CALIFORNIA INSTITUTE OF TECHNOLOGY,
`Patent Owner.
`_____________________________
`
`Case No. IPR2023-00133
`Patent No. 7,421,032
`_____________________________
`
`PATENT OWNER’S PRELIMINARY RESPONSE
`PURSUANT TO 37 C.F.R. § 42.107
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`TABLE OF CONTENTS
`Introduction ....................................................................................................... 1
`I.
`II. Claim Construction ........................................................................................... 3
`III. The Petition is Founded on a Distortion of Kobayashi .................................... 5
`IV. Ground 1 Fails ................................................................................................... 8
`A. Petitioner Fails to Show That Kobayashi Discloses Encoding of
`Message Bits to Generate Parity Bits or Making Parity Bits
`Available for Transmission......................................................................... 9
`1. The bit sequence identified by the petition has not been shown to be a
`collection or sequence of parity bits ...................................................10
`2. Kobayashi does not disclose making the sequence of parity bits
`available for transmission ...................................................................16
`B. Kobayashi Does Not Disclose the Recited Sum of “a” Randomly
`Chosen Irregular Repeats of the Message Bits for Each Parity Bit ......... 18
`1. Kobayashi does not disclose sums of irregular repeats ......................20
`2. Kobayashi does not disclose that the “a” bits are randomly chosen
`repeats of the message bits .................................................................35
`V. Ground 2 Fails ................................................................................................. 39
`A. Ground 2 Fails to Either Remedy Ground 1’s Deficiencies or
`Motivate Its Proposed Modifications ....................................................... 39
`B. Petitioner’s Modifications Fail to Satisfy Claim 7 ................................... 41
`VI. Ground 3 Fails ................................................................................................. 43
`A. Petitioner Fails to Show that Kobayashi in view of McEliece
`Teaches or Suggests the Elements of Claim 18 ........................................ 44
`B. Petitioner Fails to Show That It Would Have Been Obvious in view
`of McEliece to Replace Kobayashi’s Hamming Encoder with an
`LDGM (Claims 6, 13, and 21) .................................................................. 46
`VII. Institution Should be Denied under 35 U.S.C. §314(a) .................................. 47
`A. Fintiv Applies to This Proceeding ............................................................ 48
`B. The Fintiv Factors Weigh in Favor of Denying Institution ...................... 50
`1. Factor 1 favors denial .........................................................................50
`2. Factor 2 favors denial .........................................................................52
`3. Factor 3 favors denial .........................................................................53
`4. Factor 4 does not favor institution ......................................................57
`5. Factor 5 favors denial .........................................................................58
`6. Factor 6 favors denial .........................................................................59
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`VIII. Conclusion ...................................................................................................... 62
`IX. Appendix ......................................................................................................... 64
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`I.
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`INTRODUCTION
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`This is the fifth IPR petition challenging the claims of U.S. Patent No.
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`7,421,032 (“the ’032 patent”). Despite four prior petitions1 and three instituted
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`trials, the Board has never found a single claim of the ’032 patent unpatentable.2
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`The present petition does not warrant a different outcome.
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`Petitioner Samsung Electronics Co., Ltd. advances a challenge premised on
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`anticipation by Kobayashi, yet various aspects of the challenged claims are simply
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`missing from Kobayashi. Rather than meeting its burden to show that Kobayashi
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`discloses each limitation, Petitioner seeks to avoid the claims’ requirements by
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`misreading limitations, ignoring Kobayashi’s disclosure, or simply assuming that
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`Kobayashi meets the claims despite its silence on the issue. For example, each
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`independent claim includes a limitation directed to summing sets of randomly-
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`permuted irregularly repeated bits—expressed either as “a sum of ‘a’ randomly
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`chosen irregular repeats of the message bits” as recited in claim 1, or in the form of
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`a Tanner graph conveying the same requirement as recited in claims 11 and 18.
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`Kobayashi discloses neither irregular repetition nor the random choosing or
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`1 See IPR2017-00700; IPR2017-00701; IPR2017-00728; IPR2015-00060.
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`2 The Federal Circuit summarily affirmed the final written decisions upholding
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`all claims. Apple Inc. v. Cal. Inst. of Tech., 784 F. App’x 759 (Fed. Cir. 2019).
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`-1-
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`permuting that is required by the claims, and Petitioner fails to show that it is
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`inherent. In fact, Petitioner actually provides examples of encoding techniques that
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`undermine the logic on which Petitioner grounds its inherency argument.
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`The petition is similarly deficient with respect to other limitations. The
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`independent claims recite encoding message bits to generate a collection of parity
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`bits, making a sequence of parity bits available for transmission, and receiving
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`parity bits. Yet Kobayashi discloses none of these things, as it is directed to
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`encoding of a duobinary signal consisting of base-3 digits, not bits. Moreover, the
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`petition’s arguments in Grounds 2 and 3 propose combinations that fail to meet the
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`claim limitations, contradict Kobayashi’s teachings, and rely on alleged
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`predictability in an unpredictable field.
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`In addition to these deficiencies, Petitioner’s late filing of this petition
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`warrants discretionary denial in light of the co-pending litigation in the Eastern
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`District of Texas in which Petitioner is a defendant. Petitioner filed the present
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`case less than a year before the scheduled trial. Under even generous estimates, the
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`district court trial will be completed many months before a final written decision
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`would be due in this case. Given the substantial costs that will arise due to
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`duplication of efforts, Petitioner’s unexplained and unexcused delay, and the weak
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`merits of the petition’s grounds, the Board should not institute trial.
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`Accordingly, institution of inter partes review of claims 1-8 and 10-22 of
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`U.S. Patent No. 7,421,032 should be denied.
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`II. CLAIM CONSTRUCTION
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`In an inter partes review, a claim is given its ordinary and customary
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`meaning in light of the specification. 37 C.F.R. §42.100(b); Phillips v. AWH Corp.,
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`415 F.3d 1303, 1312 (Fed. Cir. 2005) (en banc). Petitioner asserts that the term
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`“repeat” should be construed to mean “generation of additional bits, where
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`generation can include, for example, duplication or reuse of bits,” in accordance
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`with a district court construction affirmed by the Federal Circuit. Pet., 7 (citing
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`Cal. Inst. of Tech. v. Broadcom Ltd., 25 F.4th 976, 986 (Fed. Cir. 2022)
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`(“Broadcom litigation”)).
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`However, Petitioner goes on to extend this construction in an unreasonable
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`way and thereby mischaracterize the Federal Circuit’s construction. Petitioner first
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`asserts that (1) the Federal Circuit held that “passing an input message bit through
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`an AND gate when the other input is a ‘1’ bit comprises ‘repeating’ the message
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`bit”; (2) “[m]ultiplying a binary message bit by a “1” bit is equivalent to passing
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`the message bit through an AND gate with a ‘1’ bit,” and (3) therefore,
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`“multiplying an message bit by a “1” bit comprises ‘repeating’ the information
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`bit.” Pet., 15. The Federal Circuit never said this—its claim construction never
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`discussed either multiplication or AND gates. See Broadcom, 25 F.4th at 986.
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`Certainly it never said anything about multiplying by “1” being equivalent to a
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`device that uses an AND gate, let alone whether that would constitute, by itself, a
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`repeat under the claims. To the extent Petitioner implies otherwise, that is a
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`mischaracterization of the Federal Circuit’s decision.
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`Even taking as true Petitioner’s assertion that the Federal Circuit considered
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`whether passing an input bit through an AND gate where the other bit is a “1”
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`comprises repeating the information bit, the Federal Circuit’s discussion related to
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`infringement, not claim construction. See id., 986-88. The Federal Circuit made it
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`clear that it was addressing a very specific system implemented in infringing
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`products, and that the relevant analysis considered the system’s “overall
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`architecture,” not just an individual component. Id., 988. That system involved a
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`device that physically connected input bits via wires to 972 separate AND gates
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`and simultaneously transmitted duplicates of the bits via a number of selected gates
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`ranging from 3 to 12 to be used in forming parity bits. See id., 986-88 (“the
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`physical connection of the first inputs of all 972 AND gates for simultaneous
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`receipt of the information bit stream and the connection of the parity-bit system to
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`the other inputs of the AND gates to selectively enable 3 to 12 of those gates at any
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`time together implement irregular repetition” (emphases original)). In other words,
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`the Federal Circuit merely agreed that a device could be found to “irregularly
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`repeat” if its overall configuration for encoding was arranged to make multiple
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`simultaneous duplicate copies of input bits (in irregular amounts) and to transmit
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`the copied bits via separate wires through a selected set of a varying number of
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`parallel AND gates. The Federal Circuit said nothing about multiplying a bit by
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`“1”.
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`Moreover, as discussed below in §IV.B.1, the petition’s invalidity case falls
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`apart because its fundamental premise—that Kobayashi’s outer encoder
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`necessarily multiplies bits by “1” in a pattern determined by its generator matrix—
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`is unfounded, fatally undermining Petitioner’s inherency case. Even if Petitioner’s
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`interpretation of the Federal Circuit’s construction were accepted, Petitioner’s case
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`fails, as it requires reading the irregular repetition required by the claims into
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`Kobayashi despite it neither teaching nor requiring such repetition.
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`III. THE PETITION IS FOUNDED ON A DISTORTION OF KOBAYASHI
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`The ’032 patent is one of four Caltech patents that resulted from research
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`performed by the inventors, Hui Jin, Aamod Khandekar, and Robert J. McEliece,
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`in 1999-2000. The patents claim inventions directed to a revolutionary class of
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`error-correction codes, dubbed “irregular repeat and accumulate codes,” or “IRA
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`codes,” which rivaled and surpassed the performance of the best known codes at
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`that time. No other code known at the time could boast linear encoding, linear
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`decoding, and performance near the theoretical Shannon limit. See EX1001, 2:8-12
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`(linear time decoding), 7:1-38 (performance near theoretical Shannon limit);
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`EX2005, 7 (linear time encoding).
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`As the Board has previously found, the field of error correction coding is
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`complex and highly unpredictable. E.g., IPR2017-00701, Paper 67 at 19-20, 24-25.
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`The development of IRA codes in spite of this unpredictability represented a
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`significant advancement in encoding technology. Accordingly, the specification
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`and claims focus strongly on precise details of encoding processes that allow the
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`realization of IRA codes’ improved performance.
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`By contrast, Kobayashi focuses almost exclusively on decoding. Its title
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`describes error-correction decoding of a received data stream. Its abstract focuses
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`on its “decoding procedure,” and discusses encoding schemes only to emphasize
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`their unimportance, due to the broad applicability of its decoders, which it says can
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`be “applied to many existing systems” without modifying “the transmitter side.”
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`EX1005, Abstract. The field of invention describes “error correction of a received
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`data stream” and never once mentions encoding. EX1005, 1:7-11. The summary
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`likewise describes decoding, not encoding. EX1005, 4:28-59. Where the
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`specification describes encoding steps, the specification uses simple examples with
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`scant detail. See, e.g., EX1005, 7:46-8:2 (describing a “simple packet transmission
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`system” performing a Hamming encoding of just 4 bits at a time).
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`Petitioner describes Kobayashi’s outer encoder as performing repetitions,
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`and in particular of multiplying input bits by “1” based on the entries in a generator
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`matrix G. Pet., 15. However, as discussed below in §IV.B.1, Kobayashi discloses
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`neither repetition nor multiplying for its outer encoder. Petitioner provides an
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`illustration of the purported multiplications and sums that Kobayashi performs
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`(Pet., 16-17), but this illustration is derived from Petitioner’s imagination, not
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`Kobayashi’s disclosure.
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`Petitioner similarly mischaracterizes Kobayashi’s inner encoder. Petitioner
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`claims that “[d]uobinary signaling, which is shown as part of the ‘inner encoder’ in
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`Figure 8 above, is described as the transmission technique for transmitting the
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`sequence of parity bits I4 to the decoder.” Pet., 20; see also id., 11 n.5. This flatly
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`contradicts Kobayashi. Kobayashi expressly states that there are exactly two codes
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`used on Fig. 8’s transmission side: the “outer code[ is] a (7,4) Hamming code,” and
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`“the inner code is duobinary signaling with a precoder.” EX1005, 7:8-11. Thus, far
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`from being simply a transmission technique, duobinary signaling is a part of the
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`inner code, just as much as the precoder is. Kobayashi confirms this by illustrating
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`the “inner encoder” as being both components together, not just one taken alone.
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`See EX1005, Fig. 8. Kobayashi also provides the encoded sequence that results
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`from the duobinary encoding, labeling it as “I5.” See EX1005, 8:28-33. This
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`duobinary sequence is easily distinguished from earlier binary sequences because it
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`contains “2”s in addition to “1”s and “0”s. Kobayashi’s decoder subsequently uses
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`duobinary sequences (interspersed with error symbols) throughout much of its
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`decoding process, confirming that the duobinary sequence is the inner encoding,
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`just as Kobayashi says it is. See EX1005, 8:55-10:45.
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`This mischaracterization of Kobayashi’s inner encoder underlies the
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`petition’s entire case. The independent claims recite encoding techniques that
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`generate parity bits, the providing of generated parity bits for transmission, and the
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`decoding of received parity bits. In order to characterize the output of Kobayashi’s
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`precoder as a collection of parity bits, Petitioner equates it to a codeword, but this
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`requires rewriting Kobayashi to identify the output of its precoder as the inner
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`code, instead of the duobinary sequence that Kobayashi says is the inner code. As
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`discussed below, the petition’s failure to correctly identify the codeword actually
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`produced by Kobayashi’s inner encoder is fatal not only to Ground 1, but also to
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`each petitioned ground.
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`IV. GROUND 1 FAILS
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`Petitioner fails to show that Kobayashi anticipates claims 1, 3-5, 7-8, 11-12,
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`and 14-16 of the ’032 patent. Yet as discussed below, Petitioner fails to show that
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`Kobayashi discloses multiple limitations in independent claims 1 and 11, from
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`which claims 3-5, 7-8, 12, and 14-16 depend. These limitations include the
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`requirement that the recited encoding operations produce a sequence of parity bits
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`-8-
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`(claim 1) or an encoding of a collection of parity bits (claim 11); make parity bits
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`available for transmission (claim 1); generate each parity bit as a sum of irregular
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`repeats of message bits and the previous parity bit (all claims); and generate parity
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`bits based on a sum of randomly chosen or permuted irregular repeats (all claims).
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`Because Kobayashi has not been shown to disclose any of these limitations,
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`Ground 1 fails.
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`A. Petitioner Fails to Show That Kobayashi Discloses Encoding of
`Message Bits to Generate Parity Bits or Making Parity Bits
`Available for Transmission
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`Claim 1 recites in part “generating a sequence of parity bits” and “making
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`the sequence of parity bits available for transmission in a transmission data
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`stream.” Claim 11 recites “an encoder configured to receive a collection of
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`message bits and encode the message bits to generate a collection of parity bits
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`according to” a Tanner graph. Petitioner fails to show that Kobayashi discloses
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`either of these limitations, because the sequence of bits identified in the petition is
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`neither a collection of parity bits that is generated and made available for
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`transmission as required by claim 1, nor is it the product of an encoder configured
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`encode message bits to generate parity bits as specified in claim 11.
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`1. The bit sequence identified by the petition has not been shown
`to be a collection or sequence of parity bits
`Claims 1 and 11 recite generating a sequence or collection of parity bits. The
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`petition maps each of these limitations to the output of Kobayashi’s precoder, the
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`sequence I4. Pet., 13-14, 29. However, the petition’s mapping requires it to rewrite
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`Kobayashi, asking the Board to ignore what Kobayashi describes as its inner
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`encoder and instead recast one portion of it as an encoder in and of itself.
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`Petitioner’s challenge is untenable in view of the plain disclosure of the reference.
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`As a result, the petition fails to show that Kobayashi’s precoder output discloses
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`the recited “parity bit” limitations.
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`The petition argues that the output of Kobayashi’s precoder is a sequence or
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`collection of parity bits because Kobayashi’s precoder allegedly “can be
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`represented as a…nonsystematic linear block code” and that “[f]or such a
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`nonsystematic linear block code, the bits of the codeword are parity bits.” Pet., 13-
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`14. However, Petitioner fails to show that the precoder in Kobayashi’s system
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`encodes a code. Kobayashi plainly states what its codes are and what its encoders
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`are, and the precoder is not identified as an encoder nor as encoding a code.
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`To begin with, Petitioner presumes that Kobayashi’s precoder encodes a
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`code without actually demonstrating that the reference discloses this. Kobayashi
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`never describes the precoder as encoding a code, nor does it describe sequence I4
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`as a “codeword.” Rather, in the Fig. 8 embodiment relied on by the petition,
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`Kobayashi describes two encoders: an outer (Hamming) encoder, and an inner
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`(duobinary) encoder. EX1005, 7:6-15. Kobayashi expressly describes the outer
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`encoder as producing a “codeword of length n=7.” EX1005, 7:50-55. Likewise,
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`Kobayashi describes its inner encoder’s function as producing an “inner code,”
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`which “is duobinary signaling with a precoder.” EX1005, 7:9-11. By contrast,
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`Kobayashi never describes the output of its precoder as a codeword. In fact,
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`Kobayashi does not describe the precoder itself as an encoder, or as corresponding
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`to a code, so the fundamental premise of Petitioner’s mapping is misplaced.
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`Rather, the precoder is merely one component of Kobayashi’s inner encoder,
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`which produces a code only by the joint operation of both components. Kobayashi
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`states that the “precoder introduces a simple transformation prior to the
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`transmission by duobinary signaling,” and it states that it “maps the input binary
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`sequence into another binary sequence,” but Kobayashi does not describe this
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`sequence as a codeword, nor the precoder, in isolation, as encoding a code.
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`EX1005, 7:30-45; see id., 8:21-27.
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`Kobayashi Fig. 8 (below) confirms that the precoder is not an encoder on its
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`own, as it depicts the inner encoder as including both the precoder and duobinary
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`signaling blocks, not just the precoder:
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`-11-
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`EX1005, Fig. 8. Petitioner’s ground effectively redrafts Kobayashi to draw the
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`“inner encoder” box around just the precoder, excluding the duobinary signaling.
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`This is not what Kobayashi discloses. Petitioner’s mapping is thus unsupported,
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`and its anticipation challenge at odds with the scope and content of the prior art.
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`What’s more, Petitioner’s effort to cast the precoder as an encoder on its
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`own is at odds with the term as used in Kobayashi. Kobayashi selected the word
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`precoder to characterize that component of the inner encoder, suggesting it is a
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`first component that is used prior to forming a code via the operation of a second
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`component.
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`Petitioner attempts to justify its exclusion of the duobinary signaling from
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`the redrafted inner encoder by asserting that Kobayashi “discloses that duobinary
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`signaling is a transmission technique,” rather than part of the inner encoder. Pet.,
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`11 n.5. In particular, Petitioner tries to redefine Kobayashi’s code to match the
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`precoder output I4, not the duobinary output I5, because “[d]uobinary signaling,
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`which is shown as part of the ‘inner encoder’ in Figure 8 above, is described as the
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`transmission technique for transmitting the sequence of parity bits I4 to the
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`decoder.” Pet., 20. This mischaracterizes Kobayashi. Contrary to Petitioner’s
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`characterization, Kobayashi expressly states that its “inner code is duobinary
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`signaling with a precoder.” EX1005, 7:9-11; see also id., 8:28-32 (exemplifying
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`the “duobinary sequence” I5 as the inner encoder’s output).
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`Kobayashi not only characterizes duobinary signaling as part of its encoding,
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`but it also describes how the encoding is performed. In particular, Kobayashi’s
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`duobinary encoder produces an output with “digits equivalent to the sum of the
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`present and preceding digits” from a binary input. EX1005, 7:16-29. This is a
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`“ternary sequence,” or “three-level sequence” with digits of 0, 1, or 2, instead of
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`binary digits (bits), which have values of 0 or 1. Id. Kobayashi never describes the
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`precoder as encoding a code on its own; rather, it describes it as one of two
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`necessary components of the inner encoder, which work in conjunction to produce
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`the “inner code” (i.e., “duobinary signaling with a precoder”). EX1005, 7:9-11.
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`The petition fails to support its assertion that Kobayashi’s duobinary
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`signaling block of the inner encoder is merely a transmission technique to send the
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`precoder output I4. The petition (p. 20) cites to Kobayashi at 8:25-32, 7:30-31,
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`7:43-45, and 2:21-25, yet none of these passages help its case. The first cited
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`portion of Kobayashi directly contradicts Petitioner’s argument, indicating that it is
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`I5, not I4, that is transmitted. EX1005, 8:25-32. That the two sequences are entirely
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`different can be seen merely by comparing the two sequences, reproduced below:
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`Id.
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`The next cited portion of Kobayashi states that the “precoder introduces a
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`simple transformation prior to the transmission by duobinary signaling.” EX1005,
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`7:30-31. This does not state that duobinary signaling is only a “transmission
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`technique” and not part of Kobayashi’s encoding. Indeed, Petitioner’s third
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`citation, at the end of the same paragraph in Kobayashi, confirms that duobinary
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`signaling is a coding technique, not simply a transmission technique: “Duobinary
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`signaling illustrated in this example is a simplest case of partial-response channel
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`coding referred to in the Background of the Art.” 3 EX1005, 7:43-45. The last
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`citation does not help Petitioner: it describes partial-response channel coding as
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`3 All emphasis added unless otherwise indicated.
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`both a “coding technique[]” and a “transmission technique,” and it discusses
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`decoding it. EX1005, 2:21-25. Indeed, Kobayashi confirms that it is using a
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`nonstandard type of coding, generalizing its coding technique into “a system in
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`which the inner encoder is not a conventional error correcting encoder…, but is a
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`special type of signaling scheme or a channel with some constraint or memory.”
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`EX1005, 2:8-16. Thus, far from teaching that duobinary encoding is “simply a
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`transmission technique,” Kobayashi indicates it is used to generate a non-
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`conventional code.
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`Petitioner’s recharacterization of Kobayashi’s precoder as an encoder that
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`outputs a codeword is critical to its case. The actual code produced by Kobayashi’s
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`inner encoder, as illustrated in duobinary sequence I5, does not contain parity bits
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`because it is a sequence of base-3 digits, not bits at all. See EX1005, 7:16-29, 8:28-
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`32. Because the petition fails to show that Kobayashi’s precoder encodes a code, or
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`that its output (I4) is a codeword, it fails to show Kobayashi produces the required
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`sequence or collection of parity bits.
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`The petition’s failure to show that Kobayashi’s precoder encodes a code
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`renders irrelevant its discussion about how the precoder “can be represented.”
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`Petitioner asserts that “I4 is a ‘sequence of parity bits’ because the precoder can be
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`represented as a (49, 49) nonsystematic linear block code,” and that the “precoder
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`operation is equivalent to multiplying” I3 by a generator matrix GA. Pet., 13
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`-15-
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`Because Petitioner fails to show that Kobayashi uses its precoder alone to encode a
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`code in the first place, it makes no difference whether it is linear, or whether it
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`would have been nonsystematic if it were a code. Kobayashi never says its
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`precoder is an encoder, nor that it produces a code, nor that it outputs a codeword,
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`nor that it generates parity bits. The petition assumes what it must prove—that
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`Kobayashi discloses a code encoded by the precoder on its own, rather than by the
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`inner encoder as Kobayashi teaches. Without that unfounded assumption, the
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`petition’s argument that I4 is a sequence or collection of parity bits falls apart.
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`Accordingly, Petitioner fails to show that the output of Kobayashi’s precoder
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`is a codeword, much less a sequence or collection of parity bits as respectively
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`required by claims 1 and 11.
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`2. Kobayashi does not disclose making the sequence of parity bits
`available for transmission
`Claim 1 recites a step of “making the sequence of parity bits available for
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`transmission in a transmission data stream.” Petitioner fails to show that Kobayashi
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`discloses this limitation, as Kobayashi’s Fig. 8 transmitter never makes parity bits
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`available for transmission, nor does it transmit parity bits.
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`The petition asserts that Kobayashi “discloses that the encoded sequence of
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`parity bits I4 is made available for transmission, and transmitted via duobinary
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`signaling, to a decoder.” Pet., 19. This is not so. What is made available for
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`transmission (and transmitted) is the duobinary sequence I5. See EX1005, 8:28-45.
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`Indeed, Petitioner admits that “the decoder receives the transmission data stream in
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`the form of a duobinary sequence ‘I5.’” Pet., 20. This sequence is not the same as
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`sequence I4. It differs from I4 because the duobinary signaling element of the inner
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`encoder generates an entirely different “ternary sequence” by outputting “digits
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`equivalent to the sum of the present and preceding digits” of the sequence I4 that it
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`receives as an input. EX1005, 7:21-29. Indeed, the entire reason that Kobayashi
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`uses a precoder at all is because the mathematical transform introduced by the
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`duobinary signaling component results in a different sequence that can cause “a
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`possible error propagation in the decoded output.” EX1005, 7:30-32. The sequence
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`I5 is thus not merely a different way of expressing I4, but the result of a transform
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`that mathematically alters I4 into an entirely different sequence.
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`While Petitioner asserts that Kobayashi describes duobinary signaling as
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`merely “the transmission technique for transmitting the sequence of parity bits I4 to
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`the decoder,” this misapprehends Kobayashi. Kobayashi is clear that I5, not I4 is the
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`sequence received by the receiver. EX1005, 8:28-45. Indeed, Kobayashi discusses
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`how the receiver deals with deviations from I5, and it describes a decoding
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`procedure that corrects errors and eventually produces a sequence I13 that is
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`identical to I5. EX1005, 8:35-10:45. Compare id., 8:30-32, with id., 10:46-47.
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`Petitioner concedes that Kobayashi discusses its receiver addressing deviations
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`-17-
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`

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`from I5, not I4. See Pet., 20. In fact, whereas Kobayashi’s decoder reproduces the
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`other coded sequences (see EX1005, 7:45-8:20, 8:30-32, 10:44-11:13 (reproducing
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`I1, I2, I3, and I5), Kobayashi never addresses I4 beyond introducing it as the
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`precoder output. This merely underscores the fact that the sequence I4 is never
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`made available for transmission.
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`Accordingly, Petitioner fails to show that Kobayashi discloses “making the
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`sequence of parity bits available for transmission in a transmission data stream” as
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`recited in claim 1.
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`B. Kobayashi Does Not Disclose the Recited Sum of “a” Randomly
`Chosen Irregular Repeats of the Message Bits for Each Parity Bit
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`. The claim further specifies that the last
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`term in this equation “is the value of a sum of ‘a’ randomly chosen irregular
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`repeats of the message bits.” Claim 11 recites an encoder that encodes according to
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`Claim 1 recites that each parity bit, labeled 𝑥𝑗 is equal to a value given by
`the formula 𝑥𝑗=𝑥𝑗−1+∑ 𝑣(𝑗−1)𝑎+𝑖
`𝑎𝑖=1
`a Tanner graph (reproduced below), in which each node (labeled 𝑉𝑖 for i=1 to r) is
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`connected on the left by a plurality of lines to a “Random Permutation” box that
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`also connects to irregularly repeated message bits.
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`-18-
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`

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`Petitioner asserts that claim 11’s Tanner graph should be interpreted to have
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`
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`the same requirements as the set of equations defined in claim 1, and in particular
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`that each “parity check node 𝑉𝑗−1 must satisfy…the requirement that each parity
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`bit be equal to the prior bit plus a “sum of [‘a’] randomly chosen irregular repeats
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`of the message/information bits.” Pet., 28, 30.
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`Petitioner fails to show that Kobayashi discloses multiple aspects of these
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`limitations. To begin with, Petitioner fails to show that Kobayashi discloses
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`irregular repetition at all, much less sums of irregular repeats as required.
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`-19-
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`

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`Furthermore, even for bits supposedly involving a sum of multiple bits, Kobayashi
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`fails to disclose that the bits are randomly chosen (or permuted) repeats of the
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`message bits. Petitioner’s mapping relies on the Kobayashi’s interleaver to provide
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`the “random choosing” or “random permutation” required by the claims, but the
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`interleaver is in the wrong place relative to the Tanner graph, so it never randomly
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`permutes or chooses irregularly repeated message bits.
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`1. Kobayashi does not disclose sums of irregular repeats
`Claim 1 expressly recites a set of equations relating to each parity bit, and
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`requires that the sum in each equation be a sum of “a” randomly chosen irregular
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`repeats of message bits. Claim 11 recites an encoder that encodes according to a
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`Tanner graph, and Petitioner interprets the dashed lines on the left side of the
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`Tanner graph to correspond to irregular repetition and the lines connecting to the
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`left sides of the check nodes (Vi) to be sums of irregular repeats. See Pet., 29-30.
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`Petitioner relies on the same analysis for claim 11 as for claim 1 with respect to
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`this limitation. See id. Yet while Petitioner concedes that the claims require sums
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`of irregular repeats, it fails to show that Kobayashi discloses same.
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`a. Petitioner misinterprets the claims’ construction
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`As discussed above in §II, Petitioner misinterprets the Federal Circuit’s
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`construction of “repeat,” stretching the actual construction to conclude that every
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`act of “multiplying an message bit by a ‘1’ bit comprises ‘repeating’ the message
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`-20-
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`

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`bit,” on the basis that passing a bit through an AND gate can perform an operation
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`“equivalent” to multiplying by “1.” Pet., 15. Petitioner extends this interpretation
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`to argue that if an encoder performs a transform that can be characterized by a non-
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`zero generator matrix with differen