`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`_________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`_________________
`
`SAMSUNG ELECTRONICS CO., LTD.
`Petitioner
`
`v.
`
`
`CALIFORNIA INSTITUTE OF TECHNOLOGY
`Patent Owner
`
`_________________
`
`Patent No. 7,916,781
`_________________
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 7,916,781
`
`

`

`Petition for Inter Partes Review
`Patent No. 7,916,781
`
`TABLE OF CONTENTS
`I.
`INTRODUCTION ........................................................................................... 1
`II. MANDATORY NOTICES ............................................................................. 1
`III.
`PAYMENT OF FEES ..................................................................................... 3
`IV. GROUNDS FOR STANDING ........................................................................ 3
`V.
`PRECISE RELIEF REQUESTED AND GROUNDS .................................... 3
`VI. LEVEL OF ORDINARY SKILL .................................................................... 4
`VII. OVERVIEW OF THE ’781 PATENT ............................................................ 5
`VIII. CLAIM CONSTRUCTION ............................................................................ 6
`IX. DETAILED EXPLANATION OF GROUNDS .............................................. 7
`A. Ground 1: Claims 1-2, 10-14, 17-18, and 21-22 Are Anticipated
`By Kobayashi ........................................................................................ 7
`1.
`Claim 1 ........................................................................................ 7
`2.
`Claim 2 ...................................................................................... 17
`3.
`Claim 10 .................................................................................... 19
`4.
`Claim 11 .................................................................................... 20
`5.
`Claim 12 .................................................................................... 20
`6.
`Claim 13 .................................................................................... 21
`7.
`Claim 14 .................................................................................... 24
`8.
`Claim 17 .................................................................................... 25
`9.
`Claim 18 .................................................................................... 25
`10. Claim 21 .................................................................................... 26
`11. Claim 22 .................................................................................... 28
`
`i
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`

`

`B.
`
`Petition for Inter Partes Review
`Patent No. 7,916,781
`Ground 2: Claims 3-9, 15-16, and 21-22 Are Obvious Over
`Kobayashi ............................................................................................ 29
`1.
`Claim 3 ...................................................................................... 29
`2.
`Claim 4 ...................................................................................... 31
`3.
`Claim 5 ...................................................................................... 32
`4.
`Claim 6 ...................................................................................... 35
`5.
`Claim 7 ...................................................................................... 36
`6.
`Claim 8 ...................................................................................... 37
`7.
`Claim 9 ...................................................................................... 38
`8.
`Claim 15 .................................................................................... 39
`9.
`Claim 16 .................................................................................... 39
`10. Claim 21 .................................................................................... 39
`11. Claim 22 .................................................................................... 42
`Ground 3: Claims 5-9 Are Obvious Over Kobayashi and
`McEliece .............................................................................................. 43
`1.
`Claim 5 ...................................................................................... 43
`2.
`Claim 6 ...................................................................................... 50
`3.
`Claim 7 ...................................................................................... 50
`4.
`Claim 8 ...................................................................................... 53
`5.
`Claim 9 ...................................................................................... 54
`X. DISCRETIONARY DENIAL IS NOT APPROPRIATE HERE .................. 57
`XI. CONCLUSION .............................................................................................. 65
`
`
`
`C.
`
`ii
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`

`

`Petition for Inter Partes Review
`Patent No. 7,916,781
`
`LIST OF EXHIBITS
`
`Ex. 1001
`
`U.S. Patent No. 7,916,781
`
`Ex. 1002
`
`Declaration of Matthew C. Valenti, Ph.D., P.E.
`
`Ex. 1003
`
`Curriculum Vitae of Matthew C. Valenti, Ph.D., P.E.
`
`Ex. 1004
`
`Prosecution History of U.S. Patent No. 7,916,781
`
`Ex. 1005
`
`U.S. Patent No. 6,029,264 to Kobayashi et al. (“Kobayashi”)
`
`Ex. 1006 McEliece et al., “Turbo Decoding as an Instance of Pearl’s ‘Belief
`Propagation’ Algorithm,” IEEE Journal On Selected Areas in
`Communication, Vol. 16, No. 2 (February 1998). (“McEliece”)
`
`Ex. 1007 MacKay, “A Free Energy Minimization Framework for Inference
`Problems in Modulo 2 Arithmetic,” Fast Software Encryption, B.
`Preneel, Ed. Berlin, Germany: Springer-Verlag Lecture Notes in
`Computer Science, Vol. 1008 (1995). (“MacKay”)
`
`Ex. 1008
`
`U.S. Patent No. 5,381,408 to Brent et al.
`
`Ex. 1009
`
`Ex. 1010
`
`Ex. 1011
`
`Rorabaugh, Error Coding Cookbook: Practical C/C++ Routines and
`Recipes for Error Detection and Correction (1996). (“Rorabaugh”)
`
`Lin & Costello, Error Control Coding: Fundamentals and
`Applications (1983). (“Lin/Costello”)
`
`the Construction of Efficient Multilevel Coded
`Cheng, “On
`Modulations,” Proceedings 1997 IEEE International Symposium on
`Information Theory (July 1997). (“Cheng I”)
`
`Ex. 1012
`
`Cheng, “Iterative Decoding,” Ph.D. dissertation, California Institute of
`Technology, Pasadena, CA (March 1997). (“Cheng II”)
`
`Ex. 1013
`
`RESERVED
`
`Ex. 1014
`
`RESERVED
`
`iii
`
`

`

`Ex. 1015
`
`Petition for Inter Partes Review
`Patent No. 7,916,781
`Docket Control Order (Dkt. No. 27), from California Institute of
`Technology v. Samsung Electronics Co., Ltd., No. 2-21-cv-00446
`(E.D. Tex.)
`
`Ex. 1016
`
`National Judicial Caseload Profile (June 30, 2022)
`
`First Amended Complaint (Dkt. No. 42), from California Institute of
`Technology v. Samsung Electronics Co., Ltd., No. 2-21-cv-00446
`(E.D. Tex.)
`
`Plaintiff CalTech’s Infringement Disclosures, Exhibit 3 (Preliminary
`Claim Chart for U.S. Patent No. 7,916,781), from California Institute
`of Technology v. Samsung Electronics Co., Ltd., No. 2-21-cv-00446
`(E.D. Tex.)
`
`Ex. 1017
`
`Ex. 1018
`
`
`
`iv
`
`

`

`Petition for Inter Partes Review
`Patent No. 7,916,781
`
`I.
`
`INTRODUCTION
`Samsung Electronics Co., Ltd. (“Petitioner” or “Samsung”) requests inter
`
`partes review of claims 3-18 and 22 (“challenged claims”) of U.S. Patent No.
`
`7,916,781 (“the ’781 patent”) (Ex. 1001) assigned to California Institute of
`
`Technology ( “PO,”). For the reasons below, the challenged claims should be found
`
`unpatentable and canceled.
`
`II. MANDATORY NOTICES
`Real Parties-in-Interest: Petitioner identifies the following as the real
`
`parties-in-interest: Samsung Electronics Co., Ltd., Samsung Electronics America,
`
`Inc.
`
`Related Matters: The ’781 patent is at issue in the following matters:
`
`• California Institute of Technology v. Samsung Electronics Co., Ltd., No.
`
`2-21-cv-00446 (E.D. Tex.) (alleging infringement of the ’781 patent and
`
`also U.S. Patent Nos. 7,116,710; 7,421,032; and 8,284,833) (“E.D. Texas
`
`Litigation”).
`
`• California Institute of Technology v. Microsoft Corp., No. 6-21-cv-00276
`
`(W.D. Tex.).
`
`• California Institute of Technology v. HP Inc. f/k/a/ Hewlett-Packard Co.,
`
`No. 6-20-cv-01041 (W.D. Tex.).
`
`1
`
`

`

`Petition for Inter Partes Review
`Patent No. 7,916,781
`• California Institute of Technology v. Dell Technologies Inc., No. 6-20-cv-
`
`01042 (W.D. Tex.).
`
`• California Institute of Technology v. Broadcom Ltd., No. 2-16-cv-03714
`
`(C.D. Cal.).
`
`The ’781 patent has previously been at issue in the following matters:
`
`• Apple Inc. v. California Institute of Technology, IPR2017-00297 (“Apple
`
`-297 IPR”).
`
`• Apple Inc. v. California Institute of Technology, IPR2017-00423 (“Apple
`
`-423 IPR”).
`
`• California Institute of Technology v. Hughes Communications, Inc., No.
`
`2-15-cv-01108 (C.D. Cal.).
`
`• Hughes Communications, Inc. v. California Institute of Technology,
`
`IPR2015-00059 (“Hughes -059 IPR”).
`
`• California Institute of Technology v. Hughes Communications, Inc., No.
`
`2-13-cv-07245 (C.D. Cal.).
`
`Counsel and Service Information: Lead counsel: Robert A. Appleby (Reg.
`
`No. 40,897), and Backup counsel is Greg S. Arovas, P.C. (Reg. No. 38,818). Service
`
`information is Kirkland & Ellis, LLP, 601 Lexington Avenue, New York, NY
`
`10022,
`
`Telephone:
`
`212.446.4800,
`
`Facsimile:
`
`212.446.4900,
`
`Email:
`
`Samsung_Caltech_IPR@kirkland.com. Petitioner consents to electronic service.
`2
`
`

`

`Petition for Inter Partes Review
`Patent No. 7,916,781
`
`III. PAYMENT OF FEES
`The PTO is authorized to charge any fees due during this proceeding to
`
`Deposit Account No. 506092.
`
`IV. GROUNDS FOR STANDING
`Petitioner certifies that the ’781 patent is available for review and Petitioner
`
`is not barred/estopped from requesting review on the grounds identified herein.
`
`V.
`
`PRECISE RELIEF REQUESTED AND GROUNDS
`Claims 3-18 and 22 should be canceled as unpatentable based on the following
`
`grounds:
`
`Ground 1: Claims 10-14, 17-18, and 22 are unpatentable under pre-AIA 35
`
`U.S.C. § 102(e) as anticipated by Kobayashi (Ex. 1005);
`
`Ground 2: Claims 3-9, 15-16, and 21-22 are unpatentable under § 103(a) as
`
`being obvious over Kobayashi; and
`
`Ground 3: Claims 5-9 are unpatentable under § 103(a) as obvious over
`
`Kobayashi and McEliece (Ex. 1006).1
`
`The ’781 patent issued March 29, 2011 from Application No. 12/165,606 filed
`
`June 30, 2008, and claims priority to, inter alia, Provisional Application No.
`
`
`1 For the Grounds presented, Petitioner does not rely on any prior art reference other
`
`than those listed here. Any other references are provided to show the state of the art.
`
`3
`
`

`

`Petition for Inter Partes Review
`Patent No. 7,916,781
`60/205,095 filed May 18, 2000. Petitioner does not concede that the priority claim
`
`to the provisional application is proper, but for purposes of this proceeding, assumes
`
`the critical date is May 18, 2000.
`
`Kobayashi was filed April 28, 1997 and issued on February 22, 2000, and thus
`
`qualifies as prior art at least under pre-AIA 35 U.S.C. §§ 102(a) and 102(e).
`
`McEliece is an article published in February 1998 in the IEEE Journal on
`
`Selected Areas in Communications. (Ex. 1006, Cover; see also id. (Library date
`
`stamp), 2 (“Copyright © 1998”).) The Board has routinely held IEEE publications
`
`like McEliece as printed publications. For example, “[t]he Board has previously
`
`observed that ‘IEEE is a well-known, reputable compiler and publisher of scientific
`
`and technical publications, and we take Official Notice that members in the scientific
`
`and technical communities who both publish and engage in research rely on the
`
`information published on the copyright line of IEEE publications.’” Power
`
`Integrations, Inc., v. Semiconductor Components Industries, LLC, IPR2018-00377,
`
`Paper No. 10 at 10 (July 17, 2018). Thus, McEliece qualifies as prior art at least
`
`under pre-AIA 35 U.S.C. § 102(b).
`
`These references were not considered during prosecution or prior IPRs. (See
`
`generally Ex. 1004.) Nor are these references cumulative of references previously
`
`before the Office.
`
`4
`
`

`

`Petition for Inter Partes Review
`Patent No. 7,916,781
`
`VI. LEVEL OF ORDINARY SKILL
`A person of ordinary skill in the art at the time of the alleged invention
`
`(“POSITA”) would have had a Ph.D. in mathematics, electrical or computer
`
`engineering, or computer science with an emphasis in signal processing,
`
`communications, or coding, or a master’s degree in the above areas with at least
`
`three years of work experience in the field at the time of the alleged invention. (Ex.
`
`1002, ¶¶21-22.)2 Additional education would compensate for less experience, and
`
`vice versa. (Id.)
`
`VII. OVERVIEW OF THE ’781 PATENT
`The ’781 patent relates to “serial concatenation of interleaved convolutional
`
`codes forming turbo-like codes.” (Ex. 1001, Title; Ex. 1002, ¶¶36-39.) The ’781
`
`patent describes a “serial concatenated coder” that “includes an outer coder and an
`
`inner coder,” where the “outer coder irregularly repeats bits in a data block according
`
`to a degree profile and scrambles the repeated bits,” which are then “input to an inner
`
`coder, which has a rate substantially close to one.” (Ex. 1001, Abstract.)
`
`An exemplary embodiment of the alleged invention is disclosed by way of
`
`Figure 2. (Id., 2:39.)
`
`
`2 Petitioner submits the declaration of Matthew C. Valenti, Ph.D., P.E. (Ex. 1002),
`
`an expert in the field of the ’781 patent. (Ex. 1002, ¶¶3-20; Ex. 1003.)
`
`5
`
`

`

`Petition for Inter Partes Review
`Patent No. 7,916,781
`
`
`
`(Id., FIG. 2.)
`
`The challenged claims recite limitations relating to some of the features
`
`discussed above, but were known in the prior art. (See Section IX; Ex. 1002, ¶39;
`
`see also id. ¶¶23-35 (discussing technology background.)
`
`VIII. CLAIM CONSTRUCTION
`For IPR proceedings, the Board applies the claim construction standard set
`
`forth in Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005) (en banc). See 83
`
`Fed. Reg. 51,340-51,359 (Oct. 11, 2018). For purposes of this proceeding,
`
`Petitioner believes that no special constructions are necessary to assess whether the
`
`challenged claims are unpatentable over the asserted prior art. 3 (Ex. 1002, ¶40.)
`
`
`3 Petitioner reserves all rights to raise claim construction and other arguments,
`
`including challenges under 35 U.S.C. §§ 101 or 112, in district court as relevant to
`
`those proceedings.
`
`6
`
`

`

`Petition for Inter Partes Review
`Patent No. 7,916,781
`
`IX. DETAILED EXPLANATION OF GROUNDS
`A. Ground 1: Claims 10-14, 17-18, and 22 Are Anticipated By
`Kobayashi
`1.
`Claim 14
`a)
`A method of encoding a signal, comprising:
`To the extent the preamble of claim 1 is limiting, Kobayashi discloses the
`
`limitations therein. (Ex. 1002, ¶¶57-58; see also id., ¶¶41-47.) For example,
`
`Kobayashi discloses a concatenated system with both transmitter and receiver
`
`portions, wherein the transmitter receives a signal from a source and uses several
`
`encoders that perform the “method of encoding a signal” as claimed. (Ex. 1005,
`
`FIG. 8, 5:25-27, 7:5-8:34 (describing the method in the context of Figure 8); see also
`
`Sections IX.A.1(b)-(d).) In particular, Kobayashi discloses that the method (as
`
`shown in Figure 8’s transmitter below) comprises receiving a signal from a source
`
`via a “packet transmission system;” encoding the signal using the Hamming encoder,
`
`interleaver, and precoder components; and transmitting the encoded signal to the
`
`receiver via duobinary signaling. (Ex. 1005, 7:5-8:34; see also id., 7:46-48
`
`
`4 Claims 1-2 and 19-21 were found invalid in the Hughes -059 IPR and Apple -297
`
`IPR. This petition addresses claims 1, 2, and 21 because challenged dependent
`
`claims depend on those claims.
`
`7
`
`

`

`Petition for Inter Partes Review
`Patent No. 7,916,781
`(disclosing a “simple packet transmission system in which there are 28 information
`
`bits in a packet” as the information source); Ex. 1008, Abstract (describing a “packet
`
`transmission system” as a system that “produce[s] packets” by “packetizing an input
`
`signal” (emphasis added))5; Section IX.A.1(d) (discussing Kobayashi’s duobinary
`
`signaling as a transmission technique while being included in Figure 8’s inner
`
`encoder).)
`
`(Ex. 1005, FIG. 8 (annotated); see also id., 5:17-24; Ex. 1002, ¶58.)
`
`
`
`
`5 See n.1.
`
`8
`
`

`

`Petition for Inter Partes Review
`Patent No. 7,916,781
`
`
`
`(Ex. 1005, FIGS. 7A, 7B (showing generalized versions of the transmitter and
`
`receiver sides of Figure 8); Ex. 1002, ¶58.)
`
`b)
`
`receiving a block of data in the signal to be encoded,
`the block of data including information bits;
`Kobayashi discloses these limitations. (Ex. 1002, ¶¶59-61.) For example,
`
`Kobayashi discloses receiving a block of data I1 in the signal to be encoded, the data
`
`block including 28 information bits. (Ex. 1005, 7:46-53; see also id., 7:6-15
`
`(describing Hamming codes), 11:18-19 (“the information source is binary data”).)
`
`In particular, Kobayashi discloses that the concatenated system’s transmitter
`
`receives data via “a simple packet transmission system in which there are 28
`
`information bits in a packet, an example of which is given by the stream:
`
`I1=(0001001000110100010101100000).”
`
` (Ex. 1005, 7:46-49.)
`
` Thus,
`
`the
`
`9
`
`

`

`Petition for Inter Partes Review
`Patent No. 7,916,781
`Kobayashi method comprises “receiving a block of data in the signal” because each
`
`28-bit packet is a binary data block from a signal. (Ex. 1002, ¶60; Ex. 1008,
`
`Abstract.) The 28-bit binary data sequence I1 is encoded by the outer code
`
`(Hamming code), but “[r]ather than encoding the entire packet at once, it is first
`
`segmented into blocks of k=4 bits, and each block is then encoded to a codeword of
`
`length n=7, by using a (7, 4) Hamming code.” (Ex. 1005, 7:50-53.) Kobayashi thus
`
`discloses “receiving a block of data in the signal to be encoded” because after the
`
`concatenated system receives the block of data I1 from an input signal, the block is
`
`subsequently encoded by the Hamming code. (Ex. 1002, ¶61; see also Section
`
`IX.A.1(c)-(d) (describing further encoding steps).) Moreover, “the block of data
`
`includ[es] information bits” because Kobayashi discloses that “there are 28
`
`information bits in a packet,” that is, that the block I1 to be encoded has 28
`
`information bits. (Ex. 1005, 7:46-49; Ex. 1002, ¶61.)
`
`c)
`
`performing a first encoding operation on at least some
`of the information bits, the first encoding operation
`being a linear transform operation that generates L
`transformed bits; and
`Kobayashi discloses these limitations. (Ex. 1002, ¶¶62-66.) Kobayashi
`
`discloses that the 28-bit data block I1 is “first segmented into [sub-]blocks of k=4
`
`bits, and each [sub-]block is then encoded to a codeword of length n=7, by using a
`
`(7, 4) Hamming code.” (Ex. 1005, 7:50-53.) Kobayashi discloses that the Hamming
`
`10
`
`

`

`Petition for Inter Partes Review
`Patent No. 7,916,781
`code’s parity-check and generator matrices are represented in systematic form as
`
`follows:
`
`
`
`(Id., 7:53-65.) After the Hamming encoder has been applied to all seven sub-blocks
`
`of block I1, “the Hamming encoder output is the following 49 bits (commas are
`
`placed between code words for clarity): I2=(0001101, 0010111, 0011010, 0100011,
`
`0101110, 0110100, 0000000).” (Id., 7:66-8:2.) Kobayashi’s method then uses a
`
`“7x7 block interleaver” to “perform a permutation action . . . which will store the
`
`above 49 bits [of I2] row-wise in the following array structure.”
`
`(Id., 8:3-15.) Kobayashi discloses that the “permutation output is obtained by
`
`“reading out the above array column by column as follows: I3=(0000000, 0001110,
`
`0110010, 1010100, 1100110, 0111100, 1101000).” (Id., 8:16-20; Ex. 1002, ¶63.)
`
`
`
`11
`
`

`

`Petition for Inter Partes Review
`Patent No. 7,916,781
`Kobayashi discloses “performing a first encoding operation” on sequence I1
`
`
`
`via a Hamming encoder and interleaver to form an encoded sequence I3 because, as
`
`described above and shown below, the Hamming encoder and interleaver
`
`components comprise the first encoding step of the Kobayashi method before the
`
`method performs a second encoding step. (Ex. 1002, ¶64.) As discussed further
`
`infra Section IX.A.1(d), the encoded data sequence I3 is the input to the second
`
`encoding step of the Kobayashi method. (Section IX.A.1(d).)
`
`(Ex. 1005, FIG. 8 (annotated).) Moreover, Kobayashi discloses “performing a first
`
`encoding operation on at least some of the information bits” because the first
`
`encoding operation is performed on the sequence I1, which has 28 information bits.
`
`
`
`(Ex. 1002, ¶64.)
`
`12
`
`

`

`Petition for Inter Partes Review
`Patent No. 7,916,781
`Kobayashi also discloses “the first encoding operation being a linear
`
`
`
`transform operation” because each of the component parts is obtained by a matrix
`
`multiplication operation, which is a matrix transformation, and all such matrix
`
`transformations are linear transformations. (Id., ¶65.) For example, each Hamming
`
`code is encoded by multiplying the message by a generator matrix, which is a linear
`
`transform operation, and the interleaver operation is a linear transform operation
`
`because it may be represented by a multiplication with a permutation matrix in which
`
`each row and column has exactly one “1,” with the remaining values being “0.” (Id.)
`
`Thus, the overall “first encoding operation” is also a “linear transform operation.”
`
`(Id.) This same “first encoding operation . . . generates L transformed bits” because,
`
`for example, for each 28-bit input I1, the first encoding operation generates a 49-bit
`
`sequence I3 comprised of 28 information bits and 21 transformed bits (i.e., for the
`
`disclosed example of a 28-bit input, L=21 because 3 parity-check bits are appended
`
`to each of the seven 4-bit blocks of I1). (Id.)
`
`
`
`Accordingly, Kobayashi discloses claim 1(c). (Id., ¶66.)
`
`d)
`
`performing a second encoding operation using the L
`transformed bits as an input, the second encoding
`operation including an accumulation operation in
`which the L transformed bits generated by the first
`encoding operation are accumulated, said second
`encoding operation producing at least a portion of a
`codeword, wherein L is two or more.
`
`13
`
`

`

`Petition for Inter Partes Review
`Patent No. 7,916,781
`Kobayashi discloses these limitations. (Ex. 1002, ¶¶67-72.) Kobayashi
`
`discloses that the precoder, shown below in Figure 8, “perform[s] a second encoding
`
`operation” as claimed. (Ex. 1005, 8:18-27.)
`
`(Id., FIG. 8 (annotated); Ex. 1002, ¶67.)6
`
`
`
`
`6 While duobinary signaling is depicted in Figure 8 as part of the “inner encoder,”
`
`Kobayashi discloses that duobinary signaling is simply a transmission technique,
`
`and thus the precoder is the inner encoder component that “perform[s] a second
`
`encoding operation” as claimed. (Ex. 1005, 7:30-31, 7:43-45; see also id., 2:21-25;
`
`Ex. 1002, ¶67 n.3.)
`
`14
`
`

`

`Petition for Inter Partes Review
`Patent No. 7,916,781
`Kobayashi discloses that the precoder “us[es] the L transformed bits as an
`
`
`
`input” because it takes as an input I3, for example, the sequence “I3=(0000000,
`
`0001110, 0110010, 1010100, 1100110, 0111100, 1101000),” which as discussed in
`
`Section IX.A.1(c), includes the “L [21] transformed bits.” (Ex. 1005, 8:18-27; Ex.
`
`1002, ¶68; see also Section IX.A.1(c).) “The precoder output is obtained by taking
`
`the modulo-2 sum of the current input and the previous output (where ‘modulo-2
`
`summation’ can be implemented by Exclusive OR: 0+0=0, 0+1=1, 1+0=1, 1+1=0).”
`
`(Ex. 1005, 8:21-24.) In other words, “[t]he precoder maps the input binary sequence
`
`into another binary sequence, based on the following rule: when the current input is
`
`0, the output should remain in the previous value; and when the input is 1, the output
`
`changes its value from the previous one, i.e. either 0 to 1 or from 1 to 0.” (Id., 7:33-
`
`37.) The resulting encoded sequence is “I4=(0000000, 0001011, 1011100, 1100111,
`
`0111011, 1010111, 011000[0]).” (Id., 8:25-27.) 7 A POSITA would have
`
`understood that this encoded sequence I4 is a codeword because the output of an
`
`encoder such as Kobayashi’s precoder is a codeword. (Ex. 1002, ¶68.) This
`
`
`7 The I4 sequence contains a typographical error and is missing the 49th bit, which a
`
`POSITA would have understood to be a “0” bit based on the overall disclosure of
`
`Kobayashi and the context in the relevant portions. (Ex. 1002, ¶68 n.4.)
`
`15
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`Petition for Inter Partes Review
`Patent No. 7,916,781
`understanding is supported by Kobayashi’s disclosure which refers to the output of
`
`the Hamming encoder as a “code word” or “code words.” (Ex. 1005, 7:50-8:2.)
`
`The precoder is an accumulator that performs an accumulation operation over
`
`the 49 bits of sequence I3 because the precoder’s operations involve taking the
`
`modulo-2 partial sum of the current input in I3 and the immediately previous output
`
`in I4 (i.e., the modulo-2 partial sum of all previous inputs up to the current input).
`
`(Ex. 1002, ¶69.) This understanding is consistent with the accumulation operations
`
`disclosed by the ’781 patent. (Id.; Ex. 1001, 3:3-28 (describing accumulation of bits
`
`using mod-2 operation).) Kobayashi’s precoder accumulates the 49-bit sequence I3,
`
`which necessarily accumulates the 21 transformed bits of I3, and thus “the second
`
`encoding operation includ[es] an accumulation operation in which the L transformed
`
`bits generated by the first encoding operation are accumulated.” (Ex. 1002, ¶70.)
`
`Furthermore, the “said second encoding operation produc[es] at least a portion
`
`of a codeword, wherein L is two or more” because as discussed above, the second
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`encoding operation (precoder) produces codeword I4, and in the disclosed example
`
`where the Kobayashi method takes in 28-bit input sequences, L is equal to 21 (i.e.,
`
`L is two or more). (Id., ¶71; see also Section IX.A.1(c) (discussing how L equals
`
`21).)
`
`Accordingly, Kobayashi discloses claim 1(d). (Ex. 1002, ¶72.)
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`Petition for Inter Partes Review
`Patent No. 7,916,781
`
`2.
`
`Claim 2
`a)
`The method of claim 1, further comprising:
`b)
`outputting the codeword, wherein the codeword
`comprises parity bits.
`Kobayashi discloses these limitations. (Ex. 1002, ¶¶73-75.) As discussed in
`
`Section IX.A.1(d), while duobinary signaling is depicted in Figure 8 (below) as part
`
`of the “inner encoder,” Kobayashi discloses that duobinary signaling is simply a
`
`transmission technique. (See n.6.)
`
`(Ex. 1005, FIG. 8 (annotated).) Kobayashi discloses that the codeword I4 is
`
`transmitted (“output[ted]”) via duobinary signaling. (Ex. 1005, 8:25-34; Ex. 1002,
`
`
`
`¶73.)
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`Petition for Inter Partes Review
`Patent No. 7,916,781
`Furthermore, the “codeword [I4] comprises parity bits” because the precoder
`
`may be represented as a nonsystematic linear block code. (Ex. 1002, ¶74.) In
`
`particular, the accumulation operation is equivalent to multiplying the 1x49 vector
`
`I3 by a 49x49 generator matrix GA with “1”s both along and above the main diagonal
`
`and “0”s below the main diagonal, such as shown below, and obtaining 1x49 vector
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`I4 (i.e., the codeword) as a result. (Id.; see also Ex. 1009, 44 (“the encoding operation
`
`[of a linear block code] is represented mathematically as v = u ∙ G, where v is a
`
`vector of the encoded data bits, u is a vector of k information bits, and G is the
`
`generator matrix” (emphasis in original)), 45 (describing a nonsystematic code as
`
`GA = (cid:1743)(cid:1742)(cid:1742)(cid:1742)(cid:1741)1 1 1 ⋯ 1
`0 0 0 ⋯ 1(cid:1746)(cid:1745)(cid:1745)(cid:1745)(cid:1744)
`0 1 1 ⋯ 1
`0 0 1 ⋯ 1
`⋮
`⋮
`⋮
`⋱
`⋮
`
`one that does not contain a k x k identity matrix)8.)
`
`
`
`(Ex. 1002, ¶74.) For such a nonsystematic linear block code, the bits of the
`
`codeword are parity bits. (See Ex. 1009, 45 (describing a nonsystematic code as
`
`having parity digits, and its corresponding generator matrix as being a matrix of
`
`parity-check coefficients); Ex. 1002, ¶74.)
`
`Accordingly, Kobayashi discloses claim 2. (Ex. 1002, ¶75.)
`
`
`8 See n.1.
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`

`Petition for Inter Partes Review
`Patent No. 7,916,781
`
`3.
`
`Claim 10
`a)
`The method of claim 2, wherein performing the
`second encoding operation comprises using a first of
`the parity bits in the accumulation operation to
`produce a second of the parity bits.
`Kobayashi discloses these limitations. (Ex. 1002, ¶¶76-78.) As discussed for
`
`claim 1(d), the second encoding operation produces codeword I4, and as discussed
`
`for claim 2, each bit of the codeword is a parity bit. (Sections IX.A.1(d), IX.A.2.)
`
`As further explained for claim 1(d), each bit of codeword I4 is equal to the current
`
`input bit of I3 and the previously outputted bit of I4. (Section IX.A.1(d).) Thus, for
`
`any given bit in the first 48 of 49 bits of I4 (i.e., “a first of the parity bits”), there is
`
`another bit of I4 that immediately follows in sequence (i.e., “a second of the parity
`
`bits”) that is equal to the mod-2 sum of that bit of I4 (i.e., “a first of the parity bits”)
`
`and a bit of I3. (Ex. 1002, ¶76.)
`
`To the extent “a first of the parity bits” and “a second of the parity bits” are
`
`read to refer to “the first parity bit” and “the second parity bit” of the codeword I4,
`
`Kobayashi also discloses these limitations under this interpretation. (Id., ¶77.) For
`
`example, the second bit of I4 (“a second of the parity bits”) equals the mod-2 sum of
`
`the second bit of I3 and the first bit of I4 (“a first of the parity bits”). (Id.)
`
`Accordingly, under either interpretation, Kobayashi discloses claim 10. (Id.,
`
`¶78.)
`
`19
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`

`Petition for Inter Partes Review
`Patent No. 7,916,781
`
`4.
`
`Claim 11
`a)
`The method of claim 10, wherein outputting the
`codeword comprises outputting the second of the
`parity bits immediately following the first of the parity
`bits.
`Kobayashi discloses these limitations. (Ex. 1002, ¶79.) As explained for
`
`claim 2, the bits of the codeword are output in the order of sequence I4, i.e.,
`
`outputting the first parity bit, second parity bit, and so on, through the 49th parity bit.
`
`(Section IX.A.2.) As explained for claim 10, under either interpretation of the claim
`
`language, Kobayashi discloses that the “second of the parity bits” immediately
`
`follows the “first of the parity bits” in codeword I4. (Section IX.A.3.) Accordingly,
`
`Kobayashi discloses claim 11. (Ex. 1002, ¶79.)
`
`5.
`
`Claim 12
`a)
`The method of claim 2, wherein performing the
`second encoding operation comprises performing one
`of a mod-2 addition and an exclusive-OR operation.
`Kobayashi discloses these limitations. (Ex. 1002, ¶80.) As explained for
`
`Section IX.A.1(d), “performing
`
`the second encoding operation comprises
`
`performing one of a mod-2 addition and an exclusive-OR operation” because the
`
`precoder, which performs the second encoding operation, operates such that each bit
`
`of codeword I4 is equal to the mod-2 sum of the corresponding current input in I3
`
`and the previously outputted bit in I4. (Section IX.A.1(d); Ex. 1002, ¶80.)
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`20
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`

`Petition for Inter Partes Review
`Patent No. 7,916,781
`
`6.
`
`Claim 13
`a)
`A method of encoding a signal, comprising:
`To the extent the preamble of claim 13 is limiting, Kobayashi discloses the
`
`limitations therein for the same reasons as explained for claim 1(a). (Section
`
`IX.A.1(a); Ex. 1002, ¶81.)
`
`b)
`
`receiving a block of data in the signal to be encoded,
`the block of data including information bits;
`Kobayashi discloses these limitations for the same reasons as explained for
`
`claim 1(b). (Section IX.A.1(b); Ex. 1002, ¶82.)
`
`c)
`
`the
`performing an encoding operation using
`information bits as an input, the encoding operation
`including an accumulation of mod-2 or exclusive-OR
`sums of bits in subsets of the information bits, the
`encoding operation generating at least a portion of a
`codeword,
`Kobayashi discloses these limitations. (Ex. 1002, ¶¶83-86.) As discussed for
`
`claims 1(c) and 1(d), Kobayashi discloses “performing an encoding operation”
`
`which includes component encoding operations, such that the overall encoding
`
`operation includes a Hamming code, interleaver, and precoder. (Sectio