`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`_________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`_________________
`
`SAMSUNG ELECTRONICS CO., LTD.
`Petitioner
`
`v.
`
`
`CALIFORNIA INSTITUTE OF TECHNOLOGY
`Patent Owner
`
`_________________
`
`Patent No. 7,916,781
`_________________
`
`DECLARATION OF MATTHEW C. VALENTI, PH.D., P.E.
`IN SUPPORT OF PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 7,916,781
`
`Page 1 of 100
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`SAMSUNG EXHIBIT 1002
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`

`

`Declaration of Matthew C. Valenti, Ph.D., P.E.
`U.S. Patent No. 7,916,781
`
`V.
`
`TABLE OF CONTENTS
`I.
`INTRODUCTION ........................................................................................... 1
`BACKGROUND AND QUALIFICATIONS ................................................. 2
`II.
`III. MATERIALS REVIEWED ............................................................................ 7
`IV. PERSON OF ORDINARY SKILL IN THE ART AND THE TIME OF
`THE ALLEGED INVENTION ....................................................................... 9
`TECHNICAL BACKGROUND ................................................................... 10
`A.
`Error Control Coding .......................................................................... 10
`B. Matrix Multiplication and Modulo-2 Arithmetic ................................ 12
`VI. THE ’781 PATENT ....................................................................................... 15
`VII. CLAIM CONSTRUCTION .......................................................................... 18
`VIII. OVERVIEW OF THE PRIOR ART ............................................................. 19
`A.
`Kobayashi (Ex. 1005) .......................................................................... 19
`B. McEliece (Ex. 1006) ............................................................................ 24
`IX. THE PRIOR ART DISCLOSES AND/OR SUGGESTS THE
`RECITED FEATURES OF CLAIMS 1-18 AND 21-22 OF THE ’781
`PATENT ........................................................................................................ 29
`A.
`Kobayashi Discloses the Features of Claims 1-2, 10-14, 17-18,
`and 21-22 ............................................................................................. 29
`1.
`Claim 1 ...................................................................................... 29
`2.
`Claim 2 ...................................................................................... 42
`3.
`Claim 10 .................................................................................... 45
`4.
`Claim 11 .................................................................................... 46
`5.
`Claim 12 .................................................................................... 47
`6.
`Claim 13 .................................................................................... 47
`i
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`B.
`
`Declaration of Matthew C. Valenti, Ph.D., P.E.
`U.S. Patent No. 7,916,781
`7.
`Claim 14 .................................................................................... 51
`8.
`Claim 17 .................................................................................... 51
`9.
`Claim 18 .................................................................................... 52
`10. Claim 21 .................................................................................... 52
`11. Claim 22 .................................................................................... 55
`Kobayashi Discloses and/or Suggests the Features of Claims 3-
`9, 15-16, and 21-22.............................................................................. 57
`1.
`Claim 3 ...................................................................................... 57
`2.
`Claim 4 ...................................................................................... 60
`3.
`Claim 5 ...................................................................................... 60
`4.
`Claim 6 ...................................................................................... 67
`5.
`Claim 7 ...................................................................................... 68
`6.
`Claim 8 ...................................................................................... 70
`7.
`Claim 9 ...................................................................................... 71
`8.
`Claim 15 .................................................................................... 72
`9.
`Claim 16 .................................................................................... 72
`10. Claim 21 .................................................................................... 72
`11. Claim 22 .................................................................................... 75
`Kobayashi in View of McEliece Discloses and/or Suggests the
`Features of Claims 5-9 ........................................................................ 78
`1.
`Claim 5 ...................................................................................... 78
`2.
`Claim 6 ...................................................................................... 87
`3.
`Claim 7 ...................................................................................... 87
`4.
`Claim 8 ...................................................................................... 90
`ii
`
`C.
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`Declaration of Matthew C. Valenti, Ph.D., P.E.
`U.S. Patent No. 7,916,781
`5.
`Claim 9 ...................................................................................... 92
`CONCLUSION .............................................................................................. 96
`
`X.
`
`
`
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`iii
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`Declaration of Matthew C. Valenti, Ph.D., P.E.
`U.S. Patent No. 7,916,781
`I, Matthew C. Valenti, Ph.D., P.E., declare as follows:
`
`I.
`
`INTRODUCTION
`1.
`I have been retained by Samsung Electronics Co., Ltd. (“Petitioner”) as
`
`an independent expert consultant in this proceeding before the United States Patent
`
`and Trademark Office (“PTO”) against California Institute of Technology (“Patent
`
`Owner”) regarding U.S. Patent No. 7,916,781 (“the ’781 patent”) (Ex. 1001).1 I
`
`have been asked to consider whether certain references disclose or suggest the
`
`features recited in claims 1-18 and 21-22 (“the challenged claims”) of the ’781
`
`patent. My opinions are set forth below.
`
`2.
`
`I am being compensated at a rate of $525/hour for my work in this
`
`proceeding. My compensation is in no way contingent on the nature of my findings,
`
`the presentation of my findings in testimony, or the outcome of this or any other
`
`proceeding. I have no other interest in this proceeding.
`
`
`
`
`
`
`1 Where appropriate, I refer to exhibits that I understand are to be attached to the
`
`petition for inter partes review of the ’781 patent.
`
`1
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`
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`Declaration of Matthew C. Valenti, Ph.D., P.E.
`U.S. Patent No. 7,916,781
`II. BACKGROUND AND QUALIFICATIONS
`3.
`I presently serve as a Professor in the Lane Department of Computer
`
`Science and Electrical Engineering at West Virginia University. All of my opinions
`
`stated in this declaration are based on my own personal knowledge and professional
`
`judgment. In forming my opinions, I have relied on my knowledge and experience
`
`in signal processing, communications, and coding referenced in this declaration.
`
`4.
`
`I am over 18 years of age and, if I am called upon to do so, I would be
`
`competent to testify as to the matters set forth herein. I understand that a copy of
`
`my current curriculum vitae (CV), which details my education and professional and
`
`academic experience, is being submitted by Petitioner as Exhibit 1003. The
`
`following provides an overview of some of my experience that is relevant to the
`
`matters set forth in this declaration.
`
`5.
`
`I received my Ph.D. in Electrical Engineering from Virginia
`
`Polytechnic Institute & State University (Virginia Tech) in 1999. I also received a
`
`MS in Electrical Engineering from Johns Hopkins University in 1995, and a BS in
`
`Electrical Engineering from Virginia Tech in 1992.
`
`6.
`
`Since receiving my Ph.D., I have been teaching electrical engineering
`
`at West Virginia University. I was an Assistant Professor between August 1999 and
`
`2005, an Associate Professor between 2005 and 2010, and a Professor from 2010 to
`
`
`
`2
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`Declaration of Matthew C. Valenti, Ph.D., P.E.
`U.S. Patent No. 7,916,781
`present. In recent years, I have spent time as Interim Chair (July 2019 to June 2020)
`
`and Raymond J. Lane Department Chair (July 2020 to June 2021) of the Lane
`
`Department of Computer Science and Electrical Engineering.
`
`7.
`
`As described in my CV, I am a licensed Professional Engineer and have
`
`more than 30 years of industry and academic experience, including extensive
`
`experience in the areas of signal processing, communications, and coding. For
`
`example, in addition to my academic experience, I worked as an electronics engineer
`
`at the U.S. Naval Research Laboratory between May 1992 and August 1995, where
`
`I developed systems and algorithms for the processing and analysis of signals such
`
`as those received over antenna arrays.
`
`8.
`
`As also described in my CV, I am a member of the Institute of Electrical
`
`and Electronic Engineers (IEEE), which is the world’s largest technical professional
`
`organization dedicated to advancing technology for the benefit of humanity, and in
`
`2018, I was elevated to the rank of IEEE Fellow, which is an honor reserved for the
`
`top one-tenth of one percent of IEEE members annually.
`
`9.
`
`At West Virginia University, I have taught courses in communications,
`
`signal processing, probability theory, coding theory, systems theory, wireless
`
`networking, and digital signal processing. My coding theory course—EE 567—is a
`
`graduate-level course taught every-other year covering the topics of linear codes,
`
`
`
`3
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`Declaration of Matthew C. Valenti, Ph.D., P.E.
`U.S. Patent No. 7,916,781
`generator and parity-check matrices, Hamming codes, convolutional codes, turbo
`
`codes, LDPC codes, interleaving, Tanner graphs, and iterative decoding. As a
`
`professor, I have been the main advisor to over 50 Master’s and Doctoral students.
`
`10.
`
`I am the author of several book chapters covering the area of channel
`
`coding, including a chapter entitled “The Interplay Between Modulation and
`
`Channel Coding” in the book Transmission Techniques for Digital Communications
`
`(Elsevier, 2016), a chapter entitled “Turbo and LDPC Codes for Digital Video
`
`Broadcasting” in the book Turbo Code Applications: A Journey from a Paper to
`
`Realization (Springer, 2005), and a chapter entitled “Turbo Codes” in the book
`
`Handbook of RF and Wireless Technologies (Newnes Press, 2004).
`
`11.
`
`I have authored, and coauthored, more than 150 papers in the areas of
`
`signal processing, communications, and coding. Many of these papers involve the
`
`design of error-correcting codes. For instance, in the paper “Constellation Shaping
`
`for Bit-Interleaved LDPC Coded APSK,” published in the October 2012 issue of
`
`IEEE Transactions on Communications, I designed a low-density parity check
`
`(LDPC) code to be used with a modulation format commonly utilized by digital
`
`satellite broadcasting systems. In another paper “Coherent continuous-phase
`
`frequency-shift keying: Parameter optimization and code design,” published in the
`
`April 2009 issue of IEEE Transactions on Wireless Communications, I designed a
`
`
`
`4
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`Declaration of Matthew C. Valenti, Ph.D., P.E.
`U.S. Patent No. 7,916,781
`low-density generator matrix (LDGM) code to be used with another modulation
`
`format.
`
`12.
`
`I have received numerous awards for my work from the Benjamin M.
`
`Statler College of Engineering and Mineral Resources, which houses the Lane
`
`Department of Computer Science and Electrical Engineering at West Virginia
`
`University. I was recognized as an Outstanding Researcher by the College of
`
`Engineering and Mineral Resources in 2001, 2002, and 2009; an Outstanding
`
`Advisor in 2005 and 2013; and an Outstanding Teacher in 2002, 2004, 2007, 2010,
`
`and 2013. I also received the West Virginia University Foundation Outstanding
`
`Teaching Award in 2013. In 2019, I received the IEEE Military Communications
`
`Conference (MILCOM) Award for Sustained Technical Achievement.
`
`13. As a Fellow of the IEEE, I am actively involved with the
`
`Communications Society and its organization of several conferences and journals.
`
`For instance, I was the Technical Program Co-Chair for the 2021 IEEE International
`
`Conference on Communications (ICC), a flagship conference organized by the IEEE
`
`Communications Society which attracted nearly 2,000 technical paper submissions
`
`from top researchers around the world.
`
`
`
`5
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`Declaration of Matthew C. Valenti, Ph.D., P.E.
`U.S. Patent No. 7,916,781
`14.
`I am not an attorney and offer no legal opinions, but in the course of
`
`my work, I have had experience studying and analyzing patents and patent claims
`
`from the perspective of a person skilled in the art.
`
`
`
`
`
`6
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`Declaration of Matthew C. Valenti, Ph.D., P.E.
`U.S. Patent No. 7,916,781
`III. MATERIALS REVIEWED
`15. The opinions contained in this declaration are based on the documents
`
`I reviewed, my professional judgment, as well as my education, experience, and
`
`knowledge regarding signal processing, communications, and coding.
`
`16.
`
`In forming my opinions expressed in this declaration, I reviewed the
`
`following materials and information:
`
`Ex. 1001
`Ex. 1004
`Ex. 1005
`
`U.S. Patent No. 7,916,781
`Prosecution History of U.S. Patent No. 7,916,781
`U.S. Patent No. 6,029,264 to Kobayashi et al.
`(“Kobayashi”)
`Ex. 1006 McEliece et al., “Turbo Decoding as an Instance of
`Pearl’s ‘Belief Propagation’ Algorithm,” IEEE Journal
`On Selected Areas in Communication, Vol. 16, No. 2
`(February 1998). (“McEliece”)
`Ex. 1007 MacKay, “A Free Energy Minimization Framework for
`Inference Problems in Modulo 2 Arithmetic,” Fast
`Software Encryption, B. Preneel, Ed. Berlin, Germany:
`Springer-Verlag Lecture Notes in Computer Science,
`Vol. 1008 (1995). (“MacKay”)
`U.S. Patent No. 5,381,408 to Brent et al.
`Rorabaugh, Error Coding Cookbook: Practical C/C++
`Routines and Recipes for Error Detection and
`Correction (1996). (“Rorabaugh”)
`Lin & Costello, Error Control Coding: Fundamentals
`and Applications (1983). (“Lin/Costello”)
`Cheng, “On the Construction of Efficient Multilevel
`Coded Modulations,” Proceedings 1997 IEEE
`International Symposium on Information Theory (July
`1997). (“Cheng I”)
`Cheng, “Iterative Decoding,” Ph.D. dissertation,
`California Institute of Technology, Pasadena, CA
`(March 1997). (“Cheng II”)
`7
`
`Ex. 1008
`Ex. 1009
`
`Ex. 1010
`
`Ex. 1011
`
`Ex. 1012
`
`
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`Declaration of Matthew C. Valenti, Ph.D., P.E.
`U.S. Patent No. 7,916,781
`
`
`
`17.
`
`I also reviewed any other materials I refer to in this declaration in
`
`support of my opinions.
`
`18. My opinions contained in this declaration are based on the documents
`
`I reviewed and my knowledge and professional judgment. My opinions have also
`
`been guided by my appreciation of how a person of ordinary skill in the art would
`
`have understood the state of the art, the prior art, and the claims and the specification
`
`of the ’781 patent at the time of the alleged invention.
`
`19.
`
`I have been asked to consider that the time of the alleged invention of
`
`the ’781 patent is around May 18, 2000, which I understand is the filing date of
`
`Provisional Application No. 60/205,095, to which the ’781 patent claims priority.
`
`(Ex. 1001, 1 (Related U.S. Application Data section).) My opinions reflect how one
`
`of ordinary skill in the art (which I describe below) would have understood the ’781
`
`patent, the prior art to the patent, and the state of the art at the time of the alleged
`
`invention as I was asked to consider, noted above.
`
`20. Based on my experience and expertise, it is my opinion that the prior
`
`art discloses and/or suggests all the features recited in challenged claims 1-18 and
`
`21-22 of the ’781 patent, as I discuss in detail below.
`
`
`
`
`
`8
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`Declaration of Matthew C. Valenti, Ph.D., P.E.
`U.S. Patent No. 7,916,781
`IV. PERSON OF ORDINARY SKILL IN THE ART AND THE TIME OF
`THE ALLEGED INVENTION
`21. Based on my knowledge and experience, I understand what a person of
`
`ordinary skill in the art would have known at the time of the alleged invention, which
`
`I discussed above as being around May 18, 2000. My opinions herein are, where
`
`appropriate, based on my understandings as to a person of ordinary skill in the art at
`
`that time. In my opinion, based on the materials and information I have reviewed,
`
`and based on my experience in the technical areas relevant to the ’781 patent, a
`
`person of ordinary skill in the art at the time of the alleged invention of the ’781
`
`patent would have had a Ph.D. in mathematics, electrical or computer engineering,
`
`or computer science with an emphasis in signal processing, communications, or
`
`coding, or a master’s degree in the above areas with at least three years of work
`
`experience in the field at the time of the alleged invention. Additional education
`
`would compensate for less experience, and vice versa. I apply this understanding in
`
`my analysis herein.
`
`22. All of my opinions in this declaration are from the perspective of one
`
`of ordinary skill in the art, during the relevant timeframe (e.g., the time of the alleged
`
`invention), which I discussed above as being around May 18, 2000. During this
`
`timeframe, I possessed at least the qualifications of a person of ordinary skill in the
`
`art, as defined above.
`
`
`
`
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`Declaration of Matthew C. Valenti, Ph.D., P.E.
`U.S. Patent No. 7,916,781
`V. TECHNICAL BACKGROUND
`23.
`In this section, I discuss the state of the art with respect to certain
`
`technologies relevant to the subject matter of the ’781 patent.
`
`A. Error Control Coding
`24. An error control code, also called a channel code, adds controlled
`
`redundancy to a data transmission for the purpose of allowing the receiver of the
`
`transmission to detect and/or correct errors that will inevitably occur during
`
`transmission. (Ex. 1009, 41; Ex. 1010, 1-3.) Linear block codes, which are a
`
`common type of channel code and are relevant to the technology at issue in this
`
`proceeding, take blocks of k data bits and map them to codewords of length n, where
`
`n > k. (Ex. 1009, 41.) The difference between n and k is the amount of redundancy
`
`introduced by the code, i.e., the number of additional/redundant bits that would need
`
`to be transmitted due to using the code. By using this redundancy, the decoder at
`
`the receiver will be able to detect that errors have occurred during the transmission,
`
`wherein the maximum number of detectable errors is related to the amount of
`
`redundancy. With enough redundancy, the decoder will be able to locate the errors,
`
`which will allow them to be corrected. In general, the more redundancy there is in
`
`the codeword, i.e., the larger the value of (n – k), the more bit errors the decoder will
`
`be able to detect and/or correct. (Id., 42.)
`
`
`
`10
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`Declaration of Matthew C. Valenti, Ph.D., P.E.
`U.S. Patent No. 7,916,781
`25. The rate R of a code is the ratio of k to n; i.e., R = k/n. Since n > k, it
`
`follows that R < 1. (Ex. 1010, 4.) The rate is another way to describe how much
`
`redundancy is added by the code.
`
`26. Codes can be systematic or nonsystematic. If the length-n codeword
`
`can be partitioned into two parts with one part consisting of the k data bits and the
`
`other part consisting of the (n – k) redundant bits, then the code is said to be a
`
`systematic code. (Ex. 1009, 45; Ex. 1010, 54.) For systematic codes, the data bits
`
`are sometimes called the systematic bits and the redundant bits called the parity bits.
`
`Whether to place the parity bits before or after the systematic bits does not change
`
`the error detecting and correcting capabilities of the code and such ordering is at the
`
`discretion of the system designer. Indeed, different authors order the two parts of a
`
`systematic code differently. For instance, in Ex. 1009 (“Rorabaugh”), the
`
`systematic bits come before the parity bits, while in Ex. 1010 (“Lin/Costello”), the
`
`parity bits come before the systematic bits. (Ex. 1009, 45; Ex. 1010, 54.) If a code’s
`
`codewords cannot be so partitioned, then the code is said to be a nonsystematic code.
`
`(Ex. 1009, 45.)
`
`27. The codewords of a linear block code may be generated through a
`
`matrix multiplication operation. (Ex. 1009, 44.) Let u be a row-vector containing
`
`the k information bits (i.e., the message) and v be a row-vector containing the n code
`
`
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`Declaration of Matthew C. Valenti, Ph.D., P.E.
`U.S. Patent No. 7,916,781
`bits (i.e., the codeword). The codewords are related to the messages by a k-by-n
`
`matrix G called the generator matrix. The format of u, v, and G is shown below:
`
`Id. Notice in the above that indexing starts at 0 rather than 1. The codeword v is
`
`found by multiplying the message u by the generator matrix G as follows:
`
`
`
`v = u ∙ G
`
`where the ‘∙’ symbol is here used to denote a matrix multiplication. Id.
`
`B. Matrix Multiplication and Modulo-2 Arithmetic
`28. Matrix multiplications, such as the one used to encode a codeword from
`
`its corresponding message, are commonly used in the fields of coding, signal
`
`processing, and communications. When the operation involves the multiplication of
`
`a row vector by a matrix, then it is typically performed by taking the inner product
`
`of the vector with each of the columns of the matrix. For instance, turning back to
`
`our example of v = u ∙ G, where u is a length-k row vector (1-by-k matrix) and G is
`
`a k-by-n matrix, then the ith component of v is found by taking the inner product of
`
`
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`Declaration of Matthew C. Valenti, Ph.D., P.E.
`U.S. Patent No. 7,916,781
`u with the ith column of G. To understand how to compute the inner product, first
`
`note that u and the ith column of G both have k elements. To perform the inner
`
`product, the same indexed elements of u and the ith column of G are multiplied, and
`
`then these k products are added. This operation is best described by the following
`
`equation:
`
`
`
`(Ex. 1009, 45.) The above operation is performed for each of the n elements of v.
`
`29. Oftentimes, the linear block code is said to be binary. For binary codes,
`
`all the coefficients in the matrix multiplication operation are either 0 or 1. The
`
`message is binary, containing just 0’s and 1’s; the codeword is binary; and the G
`
`matrix also contains only 0’s and 1’s. For such codes, the addition implied by the
`
`summation in the above equation is not ordinary addition, but rather, is modulo-2
`
`(mod-2) addition. Under the rules of modulo-2 addition, 0+0=0, 1+0=1, and 0+1=1
`
`as in ordinary addition; however, under modulo-2 addition, 1+1 = 0 unlike in
`
`ordinary addition. (Id., 6-9.) Modulo-2 addition can be easily implemented in
`
`digital hardware by using an exclusive-or (XOR) gate. (Id., 7.)
`
`30. The concepts of matrix multiplication and modulo-2 arithmetic are best
`
`described by an example. Let’s consider a case where u and G are as follows:
`13
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`Declaration of Matthew C. Valenti, Ph.D., P.E.
`U.S. Patent No. 7,916,781
`
`31. The first element of v would be found by taking the inner product of u
`
`with the first column of G. This involves an element-by-element multiplication,
`
`followed by a summation of the partial products:
`
`32. The second element of v is then found by taking the inner product of u
`
`with the second column of G as follows:
`
`(cid:2203)=(cid:4670)1 0 1(cid:4671)
`(cid:1781)=(cid:3429)1 10 00 1 0 11 11 1(cid:3433)
`(cid:1874)(cid:2868)=(cid:1873)(cid:2868)(cid:1859)(cid:2868)(cid:2868)+(cid:1873)(cid:2869)(cid:1859)(cid:2869)(cid:2868)+(cid:1873)(cid:2870)(cid:1859)(cid:2870)(cid:2868)=(cid:4666)1×1(cid:4667)+(cid:4666)0×0(cid:4667)+(cid:4666)1×0(cid:4667)=1+0+0=1
`(cid:1874)(cid:2869)=(cid:1873)(cid:2868)(cid:1859)(cid:2868)(cid:2869)+(cid:1873)(cid:2869)(cid:1859)(cid:2869)(cid:2869)+(cid:1873)(cid:2870)(cid:1859)(cid:2870)(cid:2869)=(cid:4666)1×1(cid:4667)+(cid:4666)0×0(cid:4667)+(cid:4666)1×1(cid:4667)=1+0+1=0
`
`33. Note in the above that the rules of modulo-2 arithmetic had to be
`
`invoked: 1+1 = 0.
`
`34. The third and fourth elements of v are found in similar fashion:
`
`(cid:1874)(cid:2870)=(cid:1873)(cid:2868)(cid:1859)(cid:2868)(cid:2870)+(cid:1873)(cid:2869)(cid:1859)(cid:2869)(cid:2870)+(cid:1873)(cid:2870)(cid:1859)(cid:2870)(cid:2870)=(cid:4666)1×0(cid:4667)+(cid:4666)0×1(cid:4667)+(cid:4666)1×1(cid:4667)=0+0+1=1
`(cid:1874)(cid:2871)=(cid:1873)(cid:2868)(cid:1859)(cid:2868)(cid:2871)+(cid:1873)(cid:2869)(cid:1859)(cid:2869)(cid:2871)+(cid:1873)(cid:2870)(cid:1859)(cid:2870)(cid:2871)=(cid:4666)1×1(cid:4667)+(cid:4666)0×1(cid:4667)+(cid:4666)1×1(cid:4667)=1+0+1=0
`(cid:2204)=(cid:4670)1 0 1 0(cid:4671)
`
`35.
`
`It thus follows that the codeword v is:
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`Declaration of Matthew C. Valenti, Ph.D., P.E.
`U.S. Patent No. 7,916,781
`VI. THE ’781 PATENT
`36. The ’781 patent relates to “serial concatenation of interleaved
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`convolutional codes forming turbo-like codes.” (Ex. 1001, Title.) For example, the
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`’781 patent describes a “serial concatenated coder” that “includes an outer coder and
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`an inner coder,” where the “outer coder irregularly repeats bits in a data block
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`according to a degree profile and scrambles the repeated bits,” which are then “input
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`to an inner coder, which has a rate substantially close to one.” (Id., Abstract.)
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`37. The specification of
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`the ’781 patent discloses an exemplary
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`embodiment of the alleged invention by way of Figure 2. (Id., 2:39.)
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`(Id., FIG. 2.) The ’781 patent explains that “coder 200 may include an outer coder
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`202, an interleaver 204, and inner coder 206.” (Id., 2:40-41.) “The outer coder 202
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`receives the uncoded data,” which “may be partitioned into blocks of fixed size, say
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`k bits.” (Id., 2:47-78.) The ’781 patent explains that “[t]he outer coder may be an
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`Declaration of Matthew C. Valenti, Ph.D., P.E.
`U.S. Patent No. 7,916,781
`(n, k) binary linear block coder, where n>k,” such that “[t]he coder accepts as input
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`a block u of k data bits and produces an output block v of n data bits.” (Id., 2:48-
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`51.) The outer coder irregularly “repeats the k bits in a block” such that “different
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`bits in the block may be repeated a different number of times.” (Id., 2:54-64.) The
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`’781 patent explains that “[t]he bits output from the outer coder 202 are scrambled”
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`by interleaver 204 “before they are input to the inner coder 206.” (Id., 3:29-33.)
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`“The inner coder 206 may be a linear rate-1 coder,” specifically “an accumulator,
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`which produces outputs that are the modulo two (mod-2) partial sums of its inputs.”
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`(Id., 2:65-3:5.) Together, “[t]he serial concatenation of the interleaved irregular
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`repeat code and the accumulate code produces an irregular repeat and accumulate
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`(IRA) code.” (Id., 3:34-36.)
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`38. The ’781 patent further explains that “[a]n IRA code . . . may be
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`represented as a set of parity checks,” which in turn “may be represented in a
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`bipartite graph, called the Tanner graph, of the code.” (Id., 3:36-39.) The
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`specification of the ’781 patent additionally discloses that “‘[b]elief propagation’ on
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`the Tanner Graph realization may be used to decode IRA codes,” where “the belief
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`propagation decoding technique allows the messages passed on an edge to represent
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`posterior densities on the bit associated with the variable node.” (Id., 5:13-17.)
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`Declaration of Matthew C. Valenti, Ph.D., P.E.
`U.S. Patent No. 7,916,781
`39. However, as I discuss in more detail below, all of the features recited
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`in the challenged claims were already known and disclosed in the prior art. (See my
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`discussions below in Section IX.)
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`Declaration of Matthew C. Valenti, Ph.D., P.E.
`U.S. Patent No. 7,916,781
`VII. CLAIM CONSTRUCTION
`40.
`I understand that claim terms are typically given their ordinary and
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`customary meanings, as would have been understood by a person of ordinary skill
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`in the art at the time of the alleged invention, which as I explained above I have been
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`asked to assume is around May 18, 2000. In considering the meaning of the claims,
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`however, I understand that one must consider the language of the claims, the
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`specification, and the prosecution history of record. I have been asked to consider
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`the claim terms under their plain meanings and thus I have considered the claims,
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`specification and prosecution history for the ’781 patent in doing so in support of
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`my opinions concerning the ’781 patent and the prior art discussed herein. (Ex.
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`1001; Ex. 1004.)
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`Declaration of Matthew C. Valenti, Ph.D., P.E.
`U.S. Patent No. 7,916,781
`VIII. OVERVIEW OF THE PRIOR ART
`A. Kobayashi (Ex. 1005)
`41. U.S. Patent No. 6,029,264 (“Kobayashi”) is titled “System and Method
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`for Error Correcting a Received Data Stream in a Concatenated System,” and my
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`understanding is that Kobayashi issued February 22, 2000, from U.S. Patent
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`Application No. 08/840,383, which was filed on April 28, 1997. (Ex. 1005, Cover.)
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`Kobayashi discloses a concatenated encoding and decoding system with transmitter
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`and receiver portions, shown at the top and bottom, respectively, of Figure 8 below.
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`(Id., FIG. 8.)
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`42. Kobayashi’s transmitter is for “a simple packet transmission system in
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`which there are 28 information bits in a packet, an example of which is given by the
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`stream: I1=(0001001000110100010101100000).” (Id., 7:46-49.)
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`Declaration of Matthew C. Valenti, Ph.D., P.E.
`U.S. Patent No. 7,916,781
`43. After obtaining the 28 information bits for transmission, Kobayashi’s
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`transmitter then performs several encoding steps. “Rather than encoding the entire
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`packet at once, it is first segmented into blocks of k=4 bits, and each block is then
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`encoded to a codeword of length n=7, by using a (7, 4) Hamming code,” which has
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`the following systematic parity-check and generator matrices:
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`
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`(Id., 7:50-65.) The Hamming code output is the following sequence: I2=(0001101,
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`0010111, 0011010, 0100011, 0101110, 0110100, 0000000). (Id., 7:66-8:2.)
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`44. Next, the Kobayashi transmitter “perform[s] a permutation action,”
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`using “a 7x7 block interleaver . . . [to] store the above 49 bits row-wise in the
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`following array structure.”
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`Declaration of Matthew C. Valenti, Ph.D., P.E.
`U.S. Patent No. 7,916,781
`(Id., 8:3-15.) “[T]he permutation output is obtained by reading out the above array,
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`column by column as follows: I3=(0000000, 0001110, 0110010, 1010100, 1100110,
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`0111100, 1101000).” (Id., 8:16-20.)
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`45. The final encoding step is performed by a precoder. “The precoder
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`output is obtained by taking the modulo-2 sum of the current input and the previous
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`output (where ‘modulo-2 summation’ can be implemented by Exclusive OR: 0+0=0,
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`0+1=1, 1+0=1, 1+1=0).” (Id., 8:21-24). The resulting encoded sequence from the
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`precoder is “I4=(0000000, 0001011, 1011100, 1100111, 0111011, 1010111,
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`011000[0]).” (Id., 8:25-27.)2 A person of ordinary skill in the art would have
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`understood that this encoded sequence I4 is a codeword because the output of an
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`encoder such as Kobayashi’s precoder is a codeword. (See Section V.A (background
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`on error control coding).) This understanding is supported by Kobayashi’s
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`2 In my opinion, a person of ordinary skill in the art would have understood based
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`on the overall disclosure of Kobayashi and the context in the relevant portions that
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`the I4 sequence contains a typographical error and is missing the 49th bit. A person
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`of ordinary skill in the art would have understood this missing 49th bit to be a “0”
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`bit.
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`Declaration of Matthew C. Valenti, Ph.D., P.E.
`U.S. Patent No. 7,916,781
`disclosure which refers to the output of the Hamming encoder as a “code word” or
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`“code words.” (Ex. 1005, 7:50-8:2.)
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`46. While duobinary signaling